Valence band structures and optical transitions of Ga1−xInxNyAs1−y/GaAs compressively strained quantum wells

The electronic structures of the Ga_1−xIn_xN_yAs_1−y/GaAs compressively strained quantum wells (QW) are investigated using 6×6 k·p Hamiltonian including the heavy hole, light hole and spin–orbit splitting band. The curves of dependence of transition energy on well width and N mole fraction are obtained. The valence subband energy dispersion curves, density of state and TE and TM squared optical transition matrix elements of three possible QW structures for emitting 1.3 μm wavelength are given.     

Correlation between infrared transmission spectra and the interface trap density of SiO2 films

This work is an attempt to estimate the electrical properties of SiO₂ thin films by recording and analyzing their infrared transmission spectra. In order to study a big variety of films having different infrared and electrical properties, we studied SiO₂ films prepared by low pressure chemical vapor deposition (LPCVD) from SiH₄ + O₂ mixtures at 425 °C and annealed at 750 °C and 950 °C for 30 min. In addition thermally grown gate quality SiO₂ films of similar thickness were studied in order to compare their infrared and electrical properties with the LPCVD oxides. It was found that all studied SiO₂ films have two groups of Si–O–Si bridges. The first group corresponds to bridges located in the bulk of the film and far away from the interfaces, the grain boundaries and defects and the second group corresponds to all other bridges located near the interfaces, the grain boundaries and defects. The relative population of the bulk over the boundary bridges was found equal to 0.60 for the LPCVD film after deposition and increased to 4.0 for the LPCVD films after annealing at 950 °C. Thermally grown SiO₂ films at 950 °C were found to have a relative population of Si–O–Si bridges equal to 3.9. The interface trap density of the LPCVD film after deposition was found equal to 5.47 × 10¹² eV⁻¹ cm⁻² and decreases to 6.50 × 10¹⁰ eV⁻¹ cm⁻² after annealing at 950 °C for 30 min. The interface trap density of the thermally grown film was found equal to 1.27 × 10¹¹ eV⁻¹ cm⁻² showing that films with similar Si–O–Si bridge populations calculated from the FTIR analysis have similar interface trap densities.     

Luminescence and microstructure of Er/O co-doped Si structures grown by MBE using Er and SiO evaporation

Er and O co-doped Si structures have been prepared using molecular-beam epitaxy (MBE) with fluxes of Er and O obtained from Er and silicon monoxide (SiO) evaporation in high-temperature cells. The incorporation of Er and O has been studied for concentrations of up to 2×10²⁰ and 1×10²¹ cm⁻³, respectively. Surface segregation of Er can take place, but with O co-doping the segregation is suppressed and Er-doped layers without any indication of surface segregation can be prepared. Si_1−xGe_x and Si_1−yC_y layers doped with Er/O during growth at different substrate temperatures show more defects than corresponding Si layers. Strong emission at 1.54 μm associated with the intra-4f transition of Er³⁺ ions is observed in electroluminescence (EL) at room temperature in reverse-biased p–i–n-junctions. To optimize the EL intensity we have varied the Er/O ratio and the temperature during growth of the Er/O-doped layer. Using an Er-concentration of around 1×10²⁰ cm⁻³ we find that Er/O ratios of 1 : 2 or 1 : 4 give higher intensity than 1 : 1 while the stability with respect to breakdown is reduced for the highest used O concentrations. For increasing growth temperatures in the range 400–575°C there is an increase in the EL intensity. A positive effect of post-annealing on the photoluminescence intensity has also been observed.     

High breakdown voltage Schottky rectifier fabricated on bulk n-GaN substrate

Vertical Schottky rectifiers have been fabricated on a free-standing n-GaN substrate. Circular Pt Schottky contacts with different diameters (50 μm, 150 μm and 300 μm) were prepared on the Ga-face and full backside ohmic contact was prepared on the N-face by using Ti/Al. The electron concentration of the substrate was as low as 7 × 10¹⁵ cm⁻³. Without epitaxial layer and edge termination scheme, the reverse breakdown voltages (V_B) as high as 630 V and 600 V were achieved for 50 μm and 150 μm diameter rectifiers, respectively. For larger diameter (300 μm) rectifiers, V_B dropped to 260 V. The forward turn-on voltage (V_F) for the 50 μm diameter rectifiers was 1.2 V at the current density of 100 A/cm², and the on-state resistance (R_on) was 2.2 mΩ cm², producing a figure-of-merit (V_B)²/R_on of 180 MW cm⁻². At 10 V bias, forward currents of 0.5 A and 0.8 A were obtained for 150 μm and 300 μm diameter rectifiers, respectively. The devices exhibited an ultrafast reverse recovery characteristics, with the reverse recovery time shorter than 20 ns.     

Texture and electromigration lifetime improvements in layered Al-alloy metallization with underlying Ti by controlling water adsorption on SiO2 substrates

The effect of residual gas constituents and substrate temperature during Ti sputtering on the texture of TiN/Ti films deposited on SiO₂/Si substrates has been investigated. The Ti(002) and TiN(111) preferred texture of the films deposited at 350°C was found to be improved drastically by increasing the H₂O partial pressure from 1×10⁻⁹ to 3×10⁻⁸ Torr. Both of the Ti(002) and TiN(111) textures showed a similar H₂O partial pressure and substrate temperature dependence because of the epitaxial transfer between these planes. The improved Ti(002) texture was attributed to the self-assembly of Ti atoms on the SiO₂ surface, which had a low surface free energy due to the formation of surface OH groups. Two kinds of layered Al-alloy interconnects, AlSiCu/Ti/TiN/Ti and AlCu/TiN/Ti, were fabricated with the highly textured TiN/Ti film, and their Al(111) texture and electromigration lifetime were then evaluated. It was confirmed that both of the interconnects have strong Al(111) texture and longer EM lifetimes.     

Design of a flat field fiber with very small dispersion slope

We have given designs of a small dispersion fiber with large effective area and small dispersion slope. The fiber has flat modal field over the central part of the core, which provides large mode field diameter (8.3 μm at λ₀=1550 nm) leading to the relatively large effective area (A_eff=56.1 μm²) required to reduce nonlinear effects. The total dispersion of the proposed fiber is in the range of 2.7–3.4 ps/km/nm in the wavelength range of 1530 to 1610 nm, which covers the entire C- and L-bands of erbium doped fiber amplifiers. The dispersion slope at λ₀=1550 nm is 0.01 ps/km/nm², which is also very small.     

Silicon dioxide deposited by ECR-PECVD for low-temperature Si devices processing

Silicon dioxide films have been deposited at temperatures less than 270 °C in an electron cyclotron resonance (ECR) plasma reactor from a gas phase combination of O₂, SiH₄ and He. The physical characterization of the material was carried out through pinhole density analysis as a function of substrate temperature for different μ-wave power (E_w). Higher E_w at room deposition temperature (RT) shows low defects densities (<7 pinhole/mm²) ensuring low-temperatures process integration on large area. From FTIR analysis and Thermal Desorption Spectroscopy we also evaluated very low hydrogen content if compared to conventional rf-PECVD SiO₂ deposited at 350 °C. Electrical properties have been measured in MOS devices, depositing SiO₂ at RT. No significant charge injection up to fields 6–7 MV/cm and average breakdown electric field >10 MV/cm are observed from ramps I–V. Moreover, from high frequency and quasi-static C–V characteristics we studied interface quality as function of annealing time and annealing temperature in N₂. We found that even for low annealing temperature (200 °C) is possible to reduce considerably the interface state density down to 5 × 10¹¹ cm⁻² eV⁻¹. These results show that a complete low-temperatures process can be achieved for the integration of SiO₂ as gate insulator in polysilicon TFTs on plastic substrates.     

A study on the improved programming characteristics of flash memory with Si3N4/SiO2 stacked tunneling dielectric

The programming characteristics of memories with different tunneling-layer structures (Si₃N₄, SiO₂ and Si₃N₄/SiO₂ stack) dielectrics are investigated using 2-D device simulator of MEDICI. It is theoretically confirmed that the memory with the SiO₂/Si₃N₄ stacked tunneling layer exhibits better programming characteristics than ones with single tunneling layer of SiO₂ or Si₃N₄ for programming by channel hot electron (CHE) injection. A 10-μs programming time with a threshold-voltage shift of 5 V can be obtained for the memory with SiO₂/Si₃N₄ stacked tunneling layer at V_cg = 10 V and V_ds = 3.3 V. This is attributed to the fact that the floating-gate voltage is close to drain voltage for the stacked tunneling dielectric (TD), and thus the CHE injection current is the largest. Furthermore, optimal substrate concentration is determined to be 5 × 10¹⁶–2 × 10¹⁷ cm⁻³, by considering a trade-off between the programming characteristics and power dissipation/lifetime of the devices. Lastly, the effects of interface states on the programming characteristics are investigated. Low interface-state density gives short programming time and small post-programming control-gate current.     

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) (k<2.7) interconnects for high-performance and low-power applications of a 0.13 μm generation. Aggressive design rules, 0.11 μm gate transistor and 2.2 μm² six-transistor SRAM cell are realized by using KrF 248 nm lithography, optical proximity effect correction, and gate-shrink techniques. Eight-level interconnects are fabricated with seven level of Cu/VLK interconnect and one level of Al/SiO₂ interconnect. Drain current of 0.67 and 0.28 mA/μm are realized for nMOSFET and pMOSFET with 0.11 μm gate, respectively. Propagation delay of two input NAND with the Cu/VLK interconnect is estimated. The delay is improved by more than 70%, compared to 0.18 μm CMOS technology with Cu/FSG interconnects. Functional 288 kbit SRAM circuit is demonstrated with 2.2 μm² cell and Cu/VLK interconnect.     

Low temperature processed hafnium oxide: Structural and electrical properties

In this work hafnium oxide (HfO₂) was deposited by r.f. magnetron sputtering at room temperature and then annealed at 200 °C in forming gas (N₂+H₂) and oxygen atmospheres, respectively for 2, 5 and 10 h. After 2 h annealing in forming gas an improvement in the interface properties occurs with the associated flat band voltage changing from −2.23 to −1.28 V. This means a reduction in the oxide charge density from 1.33×10¹² to 7.62×10¹¹ cm⁻². After 5 h annealing only the dielectric constant improves due to densification of the film. Finally, after 10 h annealing we notice a degradation of the electrical film's properties, with the flat band voltage and fixed charge density being −2.96 V and 1.64×10¹² cm⁻², respectively. Besides that, the leakage current also increases due to crystallization. On the other hand, by depositing the films at 200 °C or annealing it in an oxidizing atmosphere no improvements are observed when comparing these data to the ones obtained by annealing the films in forming gas. Here the flat band voltage is more negative and the hysteresis on the C–V plot is larger than the one recorded on films annealed in forming gas, meaning a degradation of the interfacial properties.     

Examination and evaluation of La2O3 as gate dielectric for sub-100 nm CMOS and DRAM technology

High-k gate dielectric La₂O₃ thin films have been deposited on Si(1 0 0) substrates by molecular beam epitaxy (MBE). Al/La₂O₃/Si metal-oxide–semiconductor capacitor structures were fabricated and measured. A leakage current of 3 × 10⁻⁹ A/cm² and dielectric constant between 20 and 25 has been measured for samples having an equivalent oxide thickness (EOT) 2.2 nm. The estimated interface state density D_it is around 1 × 10¹¹ eV⁻¹ cm⁻². EOT and flat-band voltage were calculated using the NCSU CVC program. The chemical composition of the La₂O₃ films was measured using X-ray photoelectron spectrometry and Rutherford backscattering. Current density vs. voltage curves show that the La₂O₃ films have a leakage current several orders of magnitude lower than SiO₂ at the same EOT. Thin La₂O₃ layers survive anneals of up to 900 °C for 30 s with no degradation in electrical properties.     

Application of polyimide to bending-mode microactuators with Ni/Fe and Fe/Pt magnet

Out-of-plane polyimide (PI) electromagnetic microactuators with different geometries are designed, fabricated and tested. Fabrication of the electromagnetic microactuators consists of 10 μm thick Ni/Fe (80/20) permalloy deposition on PI diaphragm by electroplating process, electroplating of copper planar coil with 10 μm thick, bulk micromachining, and excimer laser selective ablation. They are fabricated by a novel concept to avoid the etching selectivity and residual stress problems during wafer etching. A simulation model is created by ANSYS software to analyze the microactuators. The external magnetic field intensity (H_ext) generated by the planar coil is simulated by this software. Besides, to provide bi-directional and large deflection angles of the microactuators, hard magnet Fe/Pt is deposited at low temperature of 300 °C by sputtering onto the PI diaphragm to produce a perpendicular magnetic anisotropic field. This magnetic field can enhance the interaction with H_ext to induce attractive and repulsive bi-directional force to provide a larger displacement. The results of the magnetic microactuators with and without hard magnetic are compared and discussed, respectively. The preliminary result reveals that the electromagnetic microactuators with hard magnet exhibit a greater deflection angle than that without one.     

LiInS2: A new nonlinear crystal for the mid-IR

Second harmonic generation for fundamental wavelengths between 2.3 and 6 μm and optical parametric generation from 5 to 12 μm in the mid-IR are demonstrated in a new nonlinear crystal, LiInS₂, exhibiting no two-photon absorption near 800 nm. Photoinduced absorption in the visible to near-IR occurring at λ<450 nm excitation can be removed with illumination at λ>500 nm or minimized by annealing in In₂S₃ vapor.     

Hydrogen incorporation, diffusivity and evolution in bulk ZnO

Hydrogen is readily incorporated into bulk, single-crystal ZnO during exposure to plasmas at moderate (100–300°C) temperatures. Incorporation depths of >25 μm were obtained in 0.5 h at 300°C, producing a diffusivity of 8 × 10⁻¹⁰ cm²/V s at this temperature. The activation energy for diffusion is 0.17 ± 0.12 eV, indicating an interstitial mechanism. Subsequent annealing at 500–600 °C is sufficient to evolve all of the hydrogen out of the ZnO, at least to the sensitivity of Secondary Ion Mass Spectrometry (<5 × 10¹⁵ cm⁻³). The thermal stability of hydrogen retention is slightly greater when the hydrogen is incorporated by direct implantation relative to plasma exposure, due to trapping at residual damage.     

Effect of annealing on the properties of low-k nanoporous SiO2 films prepared by sol–gel method with catalyst HF

Using hydrofluoric acid (HF) as catalyst, nanoporous SiO₂ thin film was synthesized by sol–gel method. By scanning electron microscopy, Fourier transform infrared spectra, thermo gravimetric and differential thermal analysis, ellipsometry, capacitance–voltage and current–voltage measurements, the effects of annealing on film properties were discussed in detail. The introduction of HF results in the less polarizability, the preferable microstructures and the improved thermal stability of the nanoporous silica films. After thermal annealing at 450 °C, the crack-free films with strong hydrophobicity, ultra-low dielectric constant of 1.65, porosity of 78%, and leakage current density of 1.3 × 10⁻⁸ A cm⁻² were obtained.     

Investigation of strontium tantalate thin films for high-k gate dielectric applications

Strontium tantalate (STO) films were grown by liquid-delivery (LD) metalorganic chemical vapor deposition (MOCVD) using Sr[Ta(OEt)₅(OC₂H₄OMe)]₂ as precursor. The deposition of the films was investigated in dependence on process conditions, such as substrate temperature, pressure, and concentration of the precursor. The growth rate varied from 4 to 300 nm/h and the highest rates were observed at the higher process temperature, pressure, and concentration of the precursor. The films were annealed at temperatures ranging from 600 to 1000 °C. Transmission electron microscopy (TEM), X-ray diffraction (XRD), and ellipsometry indicated that the as-deposited and the annealed films were uniform and amorphous and a thin (>2 nm) SiO₂ interlayer was found. Crystallization took place at temperatures of about 1000 °C. Annealing at moderate temperatures was found to improve the electrical characteristics despite different film thickness (effective dielectric constant up to 40, the leakage current up to 6×10⁻⁸ A/cm², and lowest midgap density value of 8×10¹⁰ eV⁻¹ cm⁻²) and did not change the uniformity of the STO films, while annealing at higher temperatures (1000 °C) created voids in the film and enhanced the SiO₂ interlayer thickness, which made the electrical properties worse. Thus, annealing temperatures of about 800 °C resulted in an optimum of the electrical properties of the STO films for gate dielectric applications.     

Silicon-based optical receivers in BiCMOS technology for advanced optoelectronic integrated circuits

A double photodiode (DPD) and a phototransistor were implemented in an industrial 0.8 μm bipolar complementary metal oxide semiconductor (BiCMOS) n-well process. Both devices are 100% BiCMOS compatible, so that no process modifications were necessary. A −3 dB bandwidth of more than 200 MHz was measured for the DPD. The rise and fall times of the photodiode are less than 1 ns. By an optimized antireflection coating layer for a wavelength of 638 nm a quantum efficiency of η=95%, which corresponds to a responsivity of R=0.49 A/W, is achievable. A phototransistor with a light-sensitive area of 53×53 μm² was developed. Its current amplification of B=300 results in a much larger responsivity compared to the photodiodes. Measurements have shown a −3 dB bandwidth of 7.8 MHz for the phototransistor.     

High temperature characterization of high-κ dielectrics on SiC

We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO₂ as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 °C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 °C. The results show that at temperatures below 400 °C the capacitors are stable, with a density of interface traps of approximately 6×10¹¹ cm² eV⁻¹. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1×10¹³ cm² eV⁻¹, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 °C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO₂ layer above 300 °C. These results at high temperatures confirms the suitability of the Pd/TiO₂/SiO₂/SiC capacitor structure for stable operation in high temperature environments.     

On the InGaP/InxGa1−xAs pseudomorphic high electron-mobility transistors for high-temperature operations

The high-temperature characteristics of a novel InGaP/In_xGa_1−xAs pseudomorphic transistor with an inverted delta-doped channel are reported. Due to the presented wide-gap InGaP Schottky layer and the V-shaped In_xGa_1−xAs channel structure, the degradation of device performance with increasing the temperature is not so significant. Experimentally, for a 1×100 μm² device, the gate–drain voltages at a gate leakage current of 260 μA/mm and the maximum transconductances g_m,max are 30 (22.2) V and 201 (169) mS/mm at the temperature of 300 (450) K, respectively. Meanwhile, broad and flat drain current operation regimes for g_m, f_T and f_max are obtained.     

Ka-band InP high electron mobility transistor monolithic microwave integrated circuit reliability

The reliability of AlInAs/GaInAs high electron mobility transistor (HEMT) monolithic microwave integrated circuits on InP substrates from HRL Labs has been studied with elevated-temperature lifetests on Ka-band LNAs, as well as ramped-voltage tests on individual capacitors. In the lifetests the LNAs were put under normal DC bias, and aging was accelerated by heating to channel temperatures of 190°C and 210°C. Room-temperature characterizations involved DC tests of HEMT parameters as well as 30 GHz measurements of gain, noise figure and phase. Aging caused the noise figure to drop by a few tenths of a dB, and the phase changed by ±10°. The gain dropped gradually by several dB. Taking 1 dB drop in gain as the failure criterion, we find an activation energy of 1.1 eV, and a mean time to failure (MTTF) at an operating channel temperature of 70°C of 7×10⁶ h. In the ramped-voltage tests, 10×10 μm² capacitors were taken to breakdown at two different temperatures, and several ramp rates. This yielded a voltage acceleration factor of γ=36–39 nm/V, and thermal activation energy of 0.11–0.13 eV. Next, ramped voltage tests were conducted on 200×200 μm² capacitors, typical of those in circuits. These were done at 25°C and 3.0 V/s only, and at least 1000 specimens were tested per wafer. The known acceleration factors were used to find the MTTFs at 70°C, with operating biases of 5 or 10 V. For the majority of the population the MTTFs are about 10⁹ h, while only 0.07% of the population has MTTF less than 1×10⁶ h. The combination of results from elevated-temperature lifetests and ramped-voltage capacitor tests indicates excellent reliability for this MMIC technology in terms of known “wearout” failure mechanisms.