High-Voltage 4H-SiC PiN Diodes With Etched Junction Termination Extension

Implantation-free mesa-etched 4H-SiC PiN diodes with a near-ideal breakdown voltage of 4.3 kV (about 80% of the theoretical value) were fabricated, measured, and analyzed by device simulation and optical imaging measurements at breakdown. The key step in achieving a high breakdown voltage is a controlled etching into the epitaxially grown p-doped anode layer to reach an optimum dopant dose of $sim!! hbox{1.2}times hbox{10}^{13} hbox{cm}^{-2}$ in the junction termination extension (JTE). Electroluminescence revealed a localized avalanche breakdown that is in good agreement with device simulation. A comparison of diodes with single- and double-zone etched JTEs shows a higher breakdown voltage and a less sensitivity to varying processing conditions for diodes with a two-zone JTE.      

High-Current-Gain SiC BJTs With Regrown Extrinsic Base and Etched JTE

This paper describes successful fabrication of 4H-SiC bipolar junction transistors (BJTs) with a regrown extrinsic base layer and an etched junction termination extension (JTE). Large-area 4H-SiC BJTs measuring 1.8 $times$ 1.8 mm (with an active area of 3.24 $hbox{mm}^{2}$) showed a common emitter current gain $beta$ of 42, specific on-resistance $R_{{rm SP}_{rm ON}}$ of 9 $hbox{m}Omegacdothbox{cm}^{2}$, and open-base breakdown voltage $hbox{BV}_{rm CEO}$ of 1.75 kV at room temperature. The key to successful fabrication of high-current-gain SiC BJTs with a regrown extrinsic base is efficient removal of the $hbox{p}^{+}$ regrown layer from the surface of the emitter–base junction. The BJT with $hbox{p}^{+}$ regrown layer has the advantage of lower base contact resistivity and current gain that is less sensitive to the distance between the emitter edge and the base contact, compared to a BJT with ion-implanted base. Fabrication of BJTs without ion implantation means less lifetime-reducing defects, and in addition, the surface morphology is improved since high-temperature annealing becomes unnecessary. BJTs with flat-surface junction termination that combine etched regrown layers show about 250 V higher breakdown voltage than BJTs with only etched flat-surface JTE.      

Fabrication and Characterization of High-Current-Gain 4H-SiC Bipolar Junction Transistors

This paper reports on newly developed high-performance 4H-SiC bipolar junction transistors (BJT) with improved current gain and power handling capabilities based on an intentionally designed continuously grown 4H-SiC BJT wafer. The measured dc common-emitter current gain is as high as 70, the specific on -state resistance $(R_{{rm SP}hbox{-}{rm ON}})$ is as low as 3.0 $hbox{m}Omegacdothbox{cm}^{2}$, and the open-base breakdown voltage $(V_{rm CEO})$ reaches 1750 V. Large-area 4H-SiC BJTs with a footprint of 4.1 $times$ 4.1 mm have been successfully packaged into a high-gain $(beta = hbox{50.8})$ high-power (80 A $times$ 700 V) all-SiC copack and evaluated at high temperature up to 250 $^{circ}hbox{C}$. Small 4H-SiC BJTs have been stress tested under a continuous collector current density of 100 $hbox{A}/hbox{cm}^{2}$ for 24 h and, for the first time, have shown no obvious forward voltage drift and no current gain degradation. Numerical simulations and experimental results have confirmed that simultaneous high current gain and high open-base breakdown voltage could be achieved in 4H-SiC BJTs.      

1580-V–40-$hbox{m}Omegacdot hbox{cm}^{2}$ Double-RESURF MOSFETs on 4H-SiC $(hbox{000}bar{hbox{1}})$

Double-reduced-surface-field (RESURF) MOSFETs with $hbox{N}_{2}hbox{O}$ -grown oxides have been fabricated on the 4H-SiC $(hbox{000} bar{hbox{1}})$ face. The double-RESURF structure is effective in reducing the drift resistance, as well as in increasing the breakdown voltage. In addition, by utilizing the 4H-SiC $(hbox{000}bar{hbox{1}})$ face, the channel mobility can be increased to over 30 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, and hence, the channel resistance is decreased. As a result, the fabricated MOSFETs on 4H-SiC $( hbox{000}bar{hbox{1}})$ have demonstrated a high breakdown voltage $(V_{B})$ of 1580 V and a low on-resistance $(R_{rm ON})$ of 40 $hbox{m}Omega cdothbox{cm}^{2}$. The figure-of-merit $(V_{B}^{2}/R_{rm ON})$ of the fabricated device has reached 62 $hbox{MW/cm}^{2}$, which is the highest value among any lateral MOSFETs and is more than ten times higher than the “Si limit.”      

A 10-kV Monolithic Darlington Transistor With $beta_{ rm forced}$ of 336 in 4H-SiC

4H-SiC bipolar Darlington transistors with a record-high current gain have been demonstrated. The dc forced current gain was measured up to 336 at 200 $hbox{W/cm}^{2}$ ( $J_{C} = hbox{35} hbox{A/cm}^{2}$ at $V_{rm CE} = hbox{5.7} hbox{V}$) at room temperature. The current gain exhibits a negative temperature coefficient and remains as high as 135 at 200 $^{circ}hbox{C}$. The specific on-resistance is 140 $hbox{m}Omegacdothbox{cm}^{2}$ at room temperature and increases at elevated temperatures. An open-emitter breakdown voltage $(BV_{rm CBO})$ of 10 kV was achieved at a leakage current density of $≪hbox{1} hbox{mA/cm}^{2}$. The device exhibits an open-base breakdown voltage $(BV_{rm CEO})$ of 9.5 kV. The high current gain of SiC Darlington transistors can significantly reduce the gate-drive power consumption with the same forward-voltage drop as that of 10-kV SiC bipolar junction transistors, thus making the device attractive for high-power high-temperature applications.      

Performance and Stability of Large-Area 4H-SiC 10-kV Junction Barrier Schottky Rectifiers

The forward and reverse bias dc characteristics, the long-term stability under forward and reverse bias, and the reverse recovery performance of 4H-SiC junction barrier Schottky (JBS) diodes that are capable of blocking in excess of 10 kV with forward conduction of up to 10 A at a forward voltage of less than 3.5 V (at 25 $^{circ}hbox{C}$) are described. The diodes show a positive temperature coefficient of resistance and a stable Schottky barrier height of up to 200 $^{circ}hbox{C}$. The diodes show stable operation under continuous forward current injection at 20 $hbox{A/cm}^{2}$ and under continuous reverse bias of 8 kV at 125 $^{circ}hbox{C}$. When switched from a 10-A forward current to a blocking voltage of 3 kV at a current rate-of-fall of 30 $hbox{A}/muhbox{s}$, the reverse recovery time and the reverse recovery charge are nearly constant at 300 ns and 425 nC, respectively, over the entire temperature range of 25 $^{circ}hbox{C}$–175 $^{circ}hbox{C}$.      

A Floating-Gate-Based Programmable CMOS Reference

We describe a compact programmable CMOS reference, where the reference is determined by the charge difference between two floating-gate transistors, thereby making the reference insensitive to temperature and other environmental effects. Using floating-gate transistors adds programmability making a wide range of reference voltages possible with negligible long-term drift. A prototype circuit has been implemented in a 0.35-$mu{hbox {m}}$ CMOS process, and reference voltages ranging from 50 mV to 0.6 V have been achieved. We demonstrate a voltage reference programming accuracy of $pm40 muhbox{V}$ . Experimental results indicate a temperature sensitivity of approximately 53 $muhbox{V}/^{circ}hbox{C}$ for a nominal reference voltage of 0.4 V over a temperature range of $-60 ^{circ}hbox{C}$–$140 ^{circ}hbox{C}$.      

Electrical Properties of $hbox{Bi}_{5}hbox{Nb}_{3} hbox{O}_{15}$ Thin Film Grown on $hbox{TiN}/hbox{SiO}_{2}/ hbox{Si}$ at Room Temperature for Metal–Insulator–Metal Capacitors

Buckling was observed in $hbox{Bi}_{5}hbox{Nb}_{3}hbox{O}_{15}$ (BiNbO) films grown on $hbox{TiN}/hbox{SiO}_{2}/hbox{Si}$ at 300 $^{circ}hbox{C}$ but not in films grown at room temperature and annealed at 350 $^{circ}hbox{C}$. The 45-nm-thick films showed a high capacitance density and a low dissipation factor of 8.81 $hbox{fF}/muhbox{m}^{2}$ and 0.97% at 100 kHz, respectively, with a low leakage current density of 3.46 $hbox{nA}/hbox{cm}^{2}$ at 2 V. The quadratic and linear voltage coefficients of capacitance of this film were 846 $hbox{ppm}/hbox{V}^{2}$ and 137 ppm/V, respectively, with a low temperature coefficient of capacitance of 226 $hbox{ppm}/^{circ}hbox{C}$ at 100 kHz. This suggests that a BiNbO film grown on a $hbox{TiN}/ hbox{SiO}_{2}/hbox{Si}$ substrate is a good candidate material for high-performance metal–insulator–metal capacitors.      

12-kV p-Channel IGBTs With Low On-Resistance in 4H-SiC

SiC bipolar devices are favored over SiC unipolar devices for applications requiring breakdown voltage in excess of 10 kV. We have designed and fabricated p-channel insulated-gate bipolar transistors (IGBTs) in 4H-SiC with 12-kV blocking voltage for high-power applications. A differential on-resistance of 18.6 $hbox{m}Omegacdothbox{cm}^{2}$ was achieved with a gate bias of 16 V, corresponding to a forward voltage drop of 5.3 V at 100 $ hbox{A/cm}^{2}$, indicating strong conductivity modulation in the p-type drift region. A moderately doped current enhancement layer grown on the lightly doped drift layer effectively reduces the JFET resistance while maintaining a high carrier lifetime for conductivity modulation. The p-channel IGBT (p-IGBT) exhibits a transconductance that is $hbox{3}times$ higher than that of the 12-kV n-channel SiC IGBTs. An inductive switching test was done at 1.5 kV and 0.55 A $(sim !!hbox{140} hbox{A/cm}^{2})$ for the p-IGBTs, and a turn-on time of 40 ns and a turn-off time of $sim !!hbox{2.8} muhbox{s}$ were measured.      

Low Turn-On Voltage and High-Current $hbox{InP}/ hbox{In}_{0.37}hbox{Ga}_{0.63}hbox{As}_{0.89}hbox{Sb}_{0.11}/hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Double Heterojunction Bipolar Transistors

We report on the dc and microwave characteristics of an $ hbox{InP/In}_{0.37}hbox{Ga}_{0.63}hbox{As}_{0.89}hbox{Sb}_{0.11}/hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ double heterojunction bipolar transistor grown by solid-source molecular beam epitaxy. The pseudomorphic $hbox{In}_{0.37}hbox{Ga}_{0.63}hbox{As}_{0.89}hbox{Sb}_{0.11}$ base reduces the conduction band offset $Delta E_{C}$ at the emitter/base junction and the base band gap, which leads to a very low $V_{rm BE}$ turn-on voltage of 0.35 V at 1 $hbox{A/cm}^{2}$ . A current gain of 125 and a peak $f_{T}$ of 238 GHz have been obtained on the devices with an emitter size of $hbox{1}times hbox{10} muhbox{m}^{2}$, suggesting that a high collector average velocity and a high current capability are achieved due to the type-II lineup at the InGaAsSb/InGaAs base/collector junction.      

Cooperative Quantum Cutting in Yb $^{3+}$–Tb $^{3+}$ Codoped Borosilicate Glasses

Quantum cutting down-conversion (DC) with the emission of two near-infrared photons for each blue photon absorbed is realized in $hbox{Yb}^{3+}hbox{–}hbox{Tb}^{3+}$ codoped borosilicate glasses. With the excitation of $hbox{Tb}^{3+}$ ion by a 484-nm monochromatic light, emission from the $^{2} hbox{F} _{5/2}rightarrow ^{2} hbox{F} _{7/2}$ transition of $hbox{Yb}^{3+}$ ions is observed and this emission is proved to originate from the DC between $hbox{Tb}^{3+}$ ions and $hbox{Yb}^{3+}$ ions. Results shows that maximum quantum efficiency reach as high as 153%, which is comparable with that in oxyfluoride glass ceramics in this system. With the advantages of excellent transparence, easy shaping, good stability, and low cost, $hbox{Yb}^{3+}hbox{–}hbox{Tb}^{3+}$ codoped borosilicate glasses are potentially used as down-converter layer in silicon-based solar cells.      

Flexible Full-Color AMOLED on Ultrathin Metal Foil

Full-color active-matrix organic light-emitting diode panels, driven by poly-Si thin-film transistors (poly-Si TFTs), were successfully fabricated on thin metal foil substrates. The p-channel poly-Si TFTs on metal foil showed a field-effect mobility of 82.9 $hbox{cm}^{2}/hbox{V}cdothbox{s}$ , subthreshold slope of 0.34 V/dec, threshold voltage of $-$ 1.67 V, and off-current of $ hbox{6.6} times hbox{10}^{-14} hbox{A}/muhbox{m}$. The 5.6-in panel had 160 $times$ RGB $times$ 350 pixels, each of which had a pixel circuit of two TFTs and one capacitor.      

Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

This letter demonstrates a vertical silicon-nanowire (SiNW)-based tunneling field-effect transistor (TFET) using CMOS-compatible technology. With a $hbox{Si} hbox{p}^{+}{-}hbox{i}{-} hbox{n}^{+}$ tunneling junction, the TFET with a gate length of $sim$200 nm exhibits good subthreshold swing of $sim$ 70 mV/dec, superior drain-induced-barrier-lowering of $sim$ 17 mV/V, and excellent $I_{rm on} {-} I_{rm off}$ ratio of $sim!!hbox{10}^{7}$ with a low $I_{rm off} (sim!!hbox{7} hbox{pA}/muhbox{m})$. The obtained 53 $muhbox{A}/muhbox{m} I_{rm on}$ can be further enhanced with heterostructures at the tunneling interface. The vertical SiNW-based TFET is proposed to be an excellent candidate for ultralow power and high-density applications.      

Effect of Gate Dopant Diffusion on Leakage Current in n+Poly-Si/HfO2 and Examination of Leakage Paths by Conducting Atomic Force Microscopy

The effect of gate dopant diffusion on leakage current has been investigated in $hbox{n}^{+}hbox{poly-Si}/hbox{HfO}_{2}$ capacitors. The $hbox{HfO}_{2}$ films with low gate doping concentration exhibited very low leakage currents, whereas the films with heavy gate doping concentration showed excessive leakage currents. Conducting atomic force microscopy was applied to examine the current images of the $hbox{HfO}_{2}$ films showing excessive leakage currents, and evident leakage paths with annular shape were observed. The leakage paths observed in the $hbox{HfO}_{2}$ films with heavy doping poly-Si gate may be related to the diffusion of the excessive dopant from the $hbox{n}^{+}$ poly-Si gate into the $hbox{HfO}_{2}$ , particularly through the grain boundaries in the films. This may significantly increase the leakage currents in the $hbox{n}^{+}hbox{poly-Si}/hbox{HfO}_{2}$ devices.      

Electrical Properties of $hbox{Ga}_{2}hbox{O}_{3}/ hbox{GaAs}$ Interfaces and GdGaO Dielectrics in GaAs-Based MOSFETs

Electrical properties of $hbox{Ga}_{2}hbox{O}_{3}/hbox{GaAs}$ interfaces with GdGaO cap dielectrics used in recent enhancement-mode GaAs-based NMOSFETs which perform in line with theoretical model predictions are presented. Capacitors with GdGaO thickness ranging from 3.0 to 18 nm ($hbox{0.9} leq hbox{EOT} leq hbox{3.9} hbox{nm}$) have been characterized by capacitance–voltage measurements. Midgap interface state density $D_{rm it}$, effective workfunction $phi_{m}$, fixed charge $Q_{f}$, dielectric constant $kappa$, and low field leakage current density are $hbox{2} times hbox{10}^{11} hbox{cm}^{-2} cdot hbox{eV}^{-1}$, 4.93 eV, $-hbox{8.9} times hbox{10}^{11} hbox{cm}^{-2}$, 19.5, and $hbox{10}^{-9}{-} hbox{10}^{-8} hbox{A/cm}^{2}$, respectively. The presence of interfacial Gd was confirmed to dramatically degrade electrical interface properties. The data illuminate the intimate interplay between heterostructure and interface engineering to achieve optimum MOSFET operation.      

The Electrical and Interfacial Properties of Metal-High-$kappa$ Oxide-Semiconductor Field-Effect Transistors With $hbox{LaAlO}_{3}$ Gate Dielectric

$hbox{LaAlO}_{3}$ is a promising candidate for gate dielectric of future VLSI devices. In this letter, n-channel metal–oxide–semiconductor field-effect transistors with $hbox{LaAlO}_{3}$ gate dielectric were fabricated, and the electron mobility degradation mechanisms were studied. The leakage current density is $hbox{7.6} times hbox{10}^{-5} hbox{A/cm}^{2}$ at $-!$ 1 V. The dielectric constant is 17.5. The surface-recombination velocity, the minority-carrier lifetime, and the effective capture cross section of surface states were extracted from gated-diode measurement. The rate of threshold voltage change with temperature $(Delta V_{T} / Delta T)$ from 11 K to 400 K is $-!$ 1.51 mV/K, and the electron mobility limited by surface roughness is proportional to $E_{rm eff}^{-0.66}$.      

Effective Modulation of Quadratic Voltage Coefficient of Capacitance in MIM Capacitors Using $hbox{Sm}_{2}hbox{O}_{3}/hbox{SiO}_{2}$ Dielectric Stack

We report the first demonstration of metal–insulator–metal (MIM) capacitors with $hbox{Sm}_{2}hbox{O}_{3}/hbox{SiO}_{2}$ stacked dielectrics for precision analog circuit applications. By using the “canceling effect” of the positive quadratic voltage coefficient of capacitance (VCC) of $hbox{Sm}_{2}hbox{O}_{3}$ and the negative quadratic VCC of $hbox{SiO}_{2}$, MIM capacitors with capacitance density exceeding 7.3 $hbox{fF}/muhbox{m}^{2}$ , quadratic VCC of around $-hbox{50} hbox{ppm/V}^{2}$ , and leakage current density of $hbox{1} times hbox{10}^{-7} hbox{A/cm}^{2}$ at $+$3.3 V are successfully demonstrated. The obtained capacitance density and quadratic VCC satisfy the technical requirements specified in the International Technology Roadmap for Semiconductors through the year 2013 for MIM capacitors to be used in precision analog circuit applications.      

Effect of Oxygen Pressure on the Electrical Properties of $hbox{Bi}_{5} hbox{Nb}_{3}hbox{O}_{15}$ Films Grown by RF Magnetron Sputtering

$hbox{Bi}_{5}hbox{Nb}_{3}hbox{O}_{15} (hbox{B}_{5}hbox{N}_{3})$ films grown under a low oxygen partial pressure (OP) of 1.7 mtorr showed a high leakage current density of 0.1 $hbox{A/cm}^{2}$ at 1.0 MV/cm. However, the leakage current density decreased with increasing OP to a minimum of $hbox{5.8} times hbox{10}^{-9} hbox{A/cm}^{2}$ for the film grown under 5.1 mtorr due to the decreased number of oxygen vacancies. This film also showed an improved breakdown field of 2.2 MV/cm and a large capacitance density of 24.9 $hbox{fF}/muhbox{m}^{2}$. The electrical properties of the film, however, deteriorated with a further increase in OP, which is probably due to the formation of oxygen interstitial ions. Therefore, superior electrical properties for the $ hbox{B}_{5}hbox{N}_{3}$ film can be obtained by careful control of OP.      

Novel Design of a 2.5-GHz Fully Integrated CMOS Butler Matrix for Smart-Antenna Systems

This paper presents a novel design of monolithic 2.5-GHz 4 $,times,$4 Butler matrix in 0.18- $mu$m CMOS technology. To achieve a full integration of smart antenna system monolithically, the proposed Butler matrix is designed with the phase-compensated transformer-based quadrature couplers and reflection-type phase shifters. The measurements show an accurate phase distribution of ${hbox{45}}{pm}{hbox{3}}^{circ}, ~{hbox{135}} pm {hbox{4}}^{circ}, ~ -{hbox{45}} pm {hbox{3}}^{circ}, ~{hbox{and}}~ -{hbox{135}} pm {hbox{4}}^{circ}$ with amplitude imbalance less than 1.5 dB. The antenna beamforming capability is also demonstrated by integrating the Butler matrix with a 1$,times,$ 4 monopole antenna array. The generated beams are pointing to $-{hbox{45}}^{circ}, ~ -{hbox{15}}^{circ}$ , 15$^{circ}$, and 45$^{circ}$, respectively, with less than 1$^{circ}$ error, which agree very well with the predictions. This Butler matrix consumes no dc power and only occupies the chip area of 1.36 $,times,$1.47 mm$^{2}$ . To our knowledge, this is the first demonstration of the single-chip Butler matrix in CMOS technology.      

Endurance Reliability of Multilevel-Cell Flash Memory Using a $ hbox{ZrO}_{2}/hbox{Si}_{3}hbox{N}_{4}$ Dual Charge Storage Layer

The mechanisms of programming/erasing (P/E) and endurance degradation have been investigated for multilevel-cell (MLC) Flash memories using a $hbox{Si}_{3}hbox{N}_{4}$ (NROM) or a $hbox{ZrO}_{2}/hbox{Si}_{3}hbox{N}_{4}$ dual charge storage layer (DCSL). Threshold-voltage $(V_{rm th})$ -level disturbance is found to be the major endurance degradation factor of NROM-type MLCs, whereas separated charge storage and step-up potential wells give rise to a superior $V_{rm th}$ -level controllability for DCSL MLCs. The programmed $V_{rm th}$ levels of DCSL MLCs are controlled by the spatial charge distribution, as well as the charge storage capacity of each storage layer, rather than the charge injection. As a result, DCSL MLCs show negligible $V_{rm th}$-level offsets ($ ≪ $ 0.2 V) that are maintained throughout the $hbox{10}^{5}$ P/E cycles, demonstrating significantly improved endurance reliability compared to NROM-type MLCs.