Development of radio frequency transmitters including on‐chip antenna for intelligent human sensing systems

This paper presents the essentials of the development of an integrated smart microsensor system that has been developed to monitor the motion and vital signs of humans in various environments. Integration of RF transmitter technology with complementary metal‐oxide‐semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize wireless smart microsensors for the monitoring system. Sensors for the measurement of body temperature, perspiration, heart rate (pressure sensor), and motion (accelerometers) are candidates for integration on the wireless smart microsensor system. In this paper, the development of radio frequency transmitter (RF) that will be integrated on wireless smart microsensors is presented. A voltage controlled RF‐CMOS oscillator (VCO) has been fabricated for the 300‐MHz frequency band applications. Also, spiral inductors for an LC resonator and an integrated antenna have been realized with a CMOS‐compatible metallization process. The essential RF components have been fabricated and evaluated experimentally. The fabricated CMOS VCO showed a conversion factor from voltage to frequency of about 81 MHz/V. After matching the characteristic impedance (50 Ω) of the on‐chip integrated antenna and the VCO output, more than 5 m signal transmission from the microchip antenna has been observed. The transmitter showed remarkable improvement in transmission power efficiency by correct matching with the microchip antenna. Essential technologies of the RF transmitter for the wireless smart microsensors have been successfully developed. Also, for the 300‐MHz band application, the integrated RF transmitter, with the CMOS oscillator and the on‐chip antenna, has been successfully demonstrated for the first time. Copyright © 2007 Institute of Electrical Engineers of Japan© 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A novel,low‐complexity,high‐speed envelope detector and its applications

A compact and effective transmission envelope detector (TED), which can detect whether the absolute amplitude of an input differential signal is larger than a threshold or not, is proposed. The TED has been demonstrated to be applicable for received signal strength indicator circuit in wireless communication receivers or power management systems, and mode‐control circuit in bidirectional optical transceivers. Implemented in a 0.18 µm CMOS technology, the TED has a response time of 210 ps at 5 Gbps, occupies an active area of 0.05 mm², and consumes 1 mA from 1.8 V supply. Copyright © 2011 John Wiley & Sons, Ltd.     

Wireless power charger for wearable medical devices with in‐band communication

A wireless power charger integrated circuit has been developed for wearable medical devices in a 0.18‐µm Bipolar, Complementary metal‐oxide‐semiconductor, and Lightly‐Doped Metal‐Oxide‐Semiconductor (BCDMOS) process. A passive full‐wave rectifier consisting of Schottky diodes and cross‐coupled n‐type Metal‐Oxide‐Semiconductor (nMOS) transistors performs the alternating current to direct current power conversion without any reverse leakage current. To charge a battery, a linear charger circuit follows the passive rectifier instead of a switching charger circuit for the small form factor of wearable medical devices. An in‐band communication circuit notifies the proper connection of the wireless power receiver and the battery charging status to the charging pad (wireless power transmitter) through the wireless power transmission channel. The wireless power charger integrated circuit occupies 1.44‐mm² silicon area and shows 31.7% power efficiency when the charging current is 26.6 mA. Copyright © 2015 John Wiley & Sons, Ltd.     

基于Linux的RF芯片驱动程序设计和实现

本文介绍了一种以S3C2410为CPU,采用RF芯片CC2500实现短距离无线通信的方法.在ARM920T内核上移植嵌入式Linux操作系统,并开发了基于Linux的CC2500驱动程序和图形界面应用程序,实现了低功耗无线数据传输.本系统应用于海关运输车辆防止非法开锁的安全检测,相对于传统的安全管理方法而言,不仅可以提高安全性、节省操作时间,而且便于数据管理与分析.     

一种单片高稳振荡器芯片设计

针对传统Pierce振荡器改进了振荡器的起振电路结构,采用负阻起振理论基于0.35μm CMOS工艺设计了一种单片高稳振荡器芯片。芯片主要包含起振电路、缓冲器电路、驱动电路、使能电路及分频器电路,输出频率范围为4 MHz^30 MHz可调,应用cohesion及Hspice软件完成了电路设计与仿真,使用Cadence软件进行了芯片的版图设计,LVS验证后完成了芯片的后仿真工作,仿真结果表明在设定的6种晶体参数下,电路在800μs时完成了起振且在tt、ff、ss 3种模式下输出平稳,该芯片能适用于无线收发信机中。     

A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC

This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm _* 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.     

360-μW 4.1-dB NF CMOS MedRadio receiver RF front-end with current-reuse Q-boosted resistive feedback LNA for biomedical IoT applications

In this paper, a low-power low-noise complementary metal-oxide semiconductor (CMOS) receiver RF front-end (RFFE) that employs a current-reuse Q-boosted resistive feedback low-noise amplifier (RFLNA) is proposed for 401 to 406 MHz medical device radio-communication service band IoT applications. By employing a series RLC input matching network, the proposed RFLNA has the advantages of both the conventional RFLNA and the inductively degenerated common-source LNA without using large on-chip spiral inductors at the sources of the main transistors. The proposed active mixer utilizes a current-reuse transconductor, in which a p-channel metal-oxide semiconductor (PMOS) transistor performs a current-bleeding function to reduce direct current (DC) and flicker noise in the switching stage of the active mixer. The proposed receiver RFFE is implemented in a 65-nm CMOS process and achieves a voltage gain of 30.9 dB, noise figure of 4.1 dB, S11 of less than −10 dB, and IIP3 of −22.9 dBm. It operates at a supply voltage of 1 V with bias currents of 360 μA. The active die area is 0.4 mm × 0.35 mm.     

Hybrid integration of smart pixels by using polyimide bonding:demonstration of a GaAs p-i-n photodiode/CMOS receiver

The fabrication procedure of smart pixels based on a hybrid integration of compound semiconductor photonic devices with silicon CMOS circuits is described. According to the 0.8-μm design rule, CMOS receiver/transmitter circuits are designed for use in vertical-cavity surface-emitting laser (VCSEL)-based smart pixels, and 16×16 and 2×2 Banyan-switch smart-pixel chips are also designed. By using our polyimide bonding technique, we integrated GaAs pin-photodiodes hybridly on the CMOS circuits. The photodetector (PD)/CMOS hybrid receiver operated error free at up to 800 Mb/s. Successful optical/optical (O/O) operation (a bit rate up to 311 Mbit/s) of the 2×2 Banyan-switch smart-pixel chip implemented with another VCSEL chip is also demonstrated     

A wirelessly powered low-power digital temperature sensor

A wirelessly powered temperature sensor is presented in complementary metal-oxide-semiconductor (CMOS) 180-nm process. The wireless power transfer (WPT) is performed using resonant magnetic coupling, and a diode-less AC to DC conversion is achieved through a quadrature-oscillator with native-MOS. The quadrature-signals are subsequently used to control the diode-less rectifier switches. The on-chip temperature sensor exploits the subthreshold region temperature, and the sensed temperature is converted to frequency using a ring-oscillator, which is implemented using differential cross coupled oscillator-based delay cells. The temperature sensor architecture also employs a temperature-insensitive replica circuit to minimize process dependence and enhance power-supply rejection ratio (PSRR) of the sensing process. The application-specific integrated circuit has been designed and fabricated in 180-nm CMOS process and has dimensions of 2 mm × 2 mm. The measurement results demonstrate that the WPT circuit generates a DC voltage of 1V with a power transfer efficiency of 85% for distances 2 to 8 mm with settling time of microseconds to milliseconds. The temperature sensor demonstrates a resolution of < ±0.6C with a sensitivity of 0.52 mV/C and 126.9 Hz/C along with PSRR of −63dB and Integral Non-Linraity (INL) of 5% measured across six different dies. The back-scattering communication demonstrates a −53-dB signal at a distance of 4 mm without affecting the WPT efficiency. The total power consumption of the temperature sensor along with the integrated biases is 120 nW.     

Explosive growth calls for more mixed-voltage analog integrated circuits

The explosive growth of the consumer electronics market in the last two decades has led to a great demand of low-cost, high-performance integrated systems. The most effective way for cost minimization is by manufacturing the system chips in advanced nanoscale complementary metal oxide semiconductor (CMOS) technologies, given that most modern microsystems are dominated by digital circuits. Entered into the nanoscale CMOS regime, 90-, 65- or 45-nm processes are expected to deliver substantial improvements in speed and power reduction for digital circuits in comparison to the current sub-micron-scale technologies.     

A new two‐step single slope A/D converter for using in CMOS image sensors

This paper presents a high‐speed, high‐resolution column parallel analog‐to‐digital converter (ADC) with global digital error correction. Proposed A/D converter is suitable for using in high‐frame‐rate complementary metal–oxide–semiconductor (CMOS) image sensors. This new method has more advantages than conventional ramp ADC from viewpoint of speed and resolution. A prototype 11‐bit ADC is designed in 0.25‐µm CMOS technology. Moreover, an overall signal‐to‐noise ratio of 63.8 dB can be achieved at 0.5Msample/s. The power dissipation of all 320 column‐parallel ADCs with the peripheral circuits consume 76 mW at 2.5‐V supplies. Copyright © 2012 John Wiley & Sons, Ltd.     

Energy Efficient Medium Access Protocol for Wireless Medical Body Area Sensor Networks

This paper presents a novel energy-efficient MAC Protocol designed specifically for wireless body area sensor networks (WBASN) focused towards pervasive healthcare applications. Wireless body area networks consist of wireless sensor nodes attached to the human body to monitor vital signs such as body temperature, activity or heart-rate. The network adopts a master-slave architecture, where the body-worn slave node periodically sends sensor readings to a central master node. Unlike traditional peer-to-peer wireless sensor networks, the nodes in this biomedical WBASN are not deployed in an ad hoc fashion. Joining a network is centrally managed and all communications are single-hop. To reduce energy consumption, all the sensor nodes are in standby or sleep mode until the centrally assigned time slot. Once a node has joined a network, there is no possibility of collision within a cluster as all communication is initiated by the central node and is addressed uniquely to a slave node. To avoid collisions with nearby transmitters, a clear channel assessment algorithm based on standard listen-before-transmit (LBT) is used. To handle time slot overlaps, the novel concept of a wakeup fallback time is introduced. Using single-hop communication and centrally controlled sleep/wakeup times leads to significant energy reductions for this application compared to more “flexible” network MAC protocols such as 802.11 or Zigbee. As duty cycle is reduced, the overall power consumption approaches the standby power. The protocol is implemented in hardware as part of the Sensium™ system-on-chip WBASN ASIC, in a 0.13- $mu{hbox {m}}$ CMOS process.      

Multiple-valued logic

The ultimate usefulness of a number system depends on its implementation. Multiple-valued logic has been implemented in charge-coupled devices (CCD). In this technology, logic values are encoded as charge. For example, prototype four-valued logic devices have been implemented at the University of Twente (Enschede, Holland). Hitachi has implemented a 16-valued memory that stores the equivalent of 10⁶ bits. CCD is more compact than any other VLSI technology. Although it is slower than CMOS (complementary metal oxide semiconductor), it is much faster than the disk and has the potential of replacing the disk. The use of multiple-valued logic in CCD increases its storage capacity significantly. Multiple-valued logic has also been implemented in current-mode CMOS     

An Ultra Low-Power CMOS Automatic Action Potential Detector

We present a low-power complementary metal–oxide semiconductor (CMOS) analog integrated biopotential detector intended for neural recording in wireless multichannel implants. The proposed detector can achieve accurate automatic discrimination of action potential (APs) from the background activity by means of an energy-based preprocessor and a linear delay element. This strategy improves detected waveforms integrity and prompts for better performance in neural prostheses. The delay element is implemented with a low-power continuous-time filter using a ninth-order equiripple allpass transfer function. All circuit building blocks use subthreshold OTAs employing dedicated circuit techniques for achieving ultra low-power and high dynamic range. The proposed circuit function in the submicrowatt range as the implemented CMOS 0.18- $mu{rm m}$ chip dissipates 780 nW, and it features a size of 0.07 ${rm mm}^{2}$. So it is suitable for massive integration in a multichannel device with modest overhead. The fabricated detector succeeds to automatically detect APs from underlying background activity. Testbench validation results obtained with synthetic neural waveforms are presented.      

HSPICE model and circuit simulation for a single-event effect caused by ions at different incident positions

A 3D model of the negative-channel metal-oxide semiconductor (NMOS) structure in a 65-nm complementary metal-oxide semiconductor (CMOS) inverter was built based on technology computer-aided design (TCAD) three-dimensional (3D) device simulation software. The single-event effect caused by a heavy ion at different incident positions was simulated and analyzed using the TCAD–HSPICE mixed-mode simulation. Then, an analytical model was established to describe the relationship between the incident position of the ion and the charge collected by the NMOS drain. Finally, an HSPICE simulation approach based on this model was developed and verified by simulations.     

An Energy-Efficient ASIC for Wireless Body Sensor Networks in Medical Applications

An energy-efficient application-specific integrated circuit (ASIC) featured with a work-on-demand protocol is designed for wireless body sensor networks (WBSNs) in medical applications. Dedicated for ultra-low-power wireless sensor nodes, the ASIC consists of a low-power microcontroller unit (MCU), a power-management unit (PMU), reconfigurable sensor interfaces, communication ports controlling a wireless transceiver, and an integrated passive radio-frequency (RF) receiver with energy harvesting ability. The MCU, together with the PMU, provides quite flexible communication and power-control modes for energy-efficient operations. The always-on passive RF receiver with an RF energy harvesting block offers the sensor nodes the capability of work-on-demand with zero standby power. Fabricated in standard 0.18-$mu$ m complementary metal–oxide semiconductor technology, the ASIC occupies a die area of 2 mm $times$ 2.5 mm. A wireless body sensor network sensor-node prototype using this ASIC only consumes $≪$ 10-nA current under the passive standby mode, and $≪10 mu$A under the active standby mode, when supplied by a 3-V battery.      

Low-Power Circuits for the Bidirectional Wireless Monitoring System of the Orthopedic Implants

This paper proposes an architecture of the wireless monitoring system for the real-time monitoring of the orthopedic implants, which monitors the implant duty cycle, detects abnormal asymmetry, high amounts of force, and other conditions of the orthopedic implants. Data for diagnosis are communicated wirelessly by the radio-frequency (RF) signal between the embedded chip and the remote circuit. In different working modes, the system can be powered by the RF signal or stiff lead zirconate–titanate (PZT) ceramics which are able to convert mechanical energy inside the orthopedic implant into electrical energy. The power circuits with a variable ratio switched-capacitor (SC) dc–dc converter have been taped out with 0.35-$mu$m complementary metal–oxide semiconductor (CMOS) technology. The test results show that the SC converter can transfer the input voltage that ranges from 5 V to 14 V from the PZT ceramics into the voltage ranging from 2 V to 2.5 V which will be dealt with by a low drop-out circuit in the future work. The total efficiency of the SC converter is from 28% to 42% at full-time working mode. The analog-to-digital converter (ADC) circuits have been fabricated in a 0.18-$mu$m 1P6M CMOS process. The test results show that the ADC chip consumes only 12.5 $mu$W in working mode and 150 nW in the sleep mode. The circuits, including RF circuits, ADC, and the microcontrol unit, have been implemented in a 0.18-$mu$ m CMOS process. Future work includes some clinical experiments test in the application where PZT elements are used for power generation in total knee-replacement implants.      

超宽带无线通信技术及其应用

通过将超宽带（UWB）无线通信技术应用于组建无线个人局域网（PAN）和无线多媒体网络,可实现数据在近距离范围内的高速传输,并有效地解决了信道衰减、成本高和功耗大等难题,同时,UWB技术也可应用于探测、定位、成像等方面.文章通过介绍UWB无线通信技术的基本概念,分析了它的2种调制方式以及性能特点,最后详细介绍了其在无线通信中的应用.     

A miniaturized neuroprosthesis suitable for implantation into the brain

This paper presents current research on a miniaturized neuroprosthesis suitable for implantation into the brain. The prosthesis is a heterogeneous integration of a 100-element microelectromechanical system (MEMS) electrode array, front-end complementary metal-oxide-semiconductor (CMOS) integrated circuit for neural signal preamplification, filtering, multiplexing and analog-to-digital conversion, and a second CMOS integrated circuit for wireless transmission of neural data and conditioning of wireless power. The prosthesis is intended for applications where neural signals are processed and decoded to permit the control of artificial or paralyzed limbs. This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring. The neuroprosthetic system design has strict size and power constraints with each of the front-end preamplifier channels fitting within the 400 /spl times/ 400-/spl mu/m pitch of the 100-element MEMS electrode array and power dissipation resulting in less than a 1/spl deg/C temperature rise for the surrounding brain tissue. We describe the measured performance of initial micropower low-noise CMOS preamplifiers for the neuroprosthetic.     

1-Gb/s integrated optical detectors and receivers in commercialCMOS technologies

The ability to produce a high-performance monolithic CMOS photoreceiver, including the photodetector, could enable greater use of optics in short-distance communication systems. Such a receiver requires the ability to simultaneously produce a photodetector compatible with a high-volume high-yield CMOS process, as well as the entire receiver circuit. The quest for this element has yet to produce a clear winner, and has proven quite challenging. We review some of the work in this field with the goal of informing the reader as to the origin of the challenges and the implementation tradeoffs. Finally, we report experimental results from a monolithic CMOS photoreceiver realized in a 0.35-μm production CMOS process, including a CMOS photodiode. Operating at 1 Gb/s, the receiver requires an average input power of -6.3 dBm at 850 nm to obtain a measured bit error rate of 1×10^-9, and dissipates 1.5 mW at 2.2 V, increasing to 6 mW at 3.3 V