Compact low-power implementation for continuous-time ΣΔ modulators

This paper presents a low-area continuous time (CT) sigma–delta (ΣΔ) modulator implementation based on a local feedback. The proposed structure provides a very low impedance node without the need of classical op-amps, which leads to a reduction in power and area consumption. Two versions of a conventional first-order CT ΣΔ modulator prototype have been fabricated with the purpose of evaluating the idea. The modulator requirements have been set for a passive RFID tag with sensing capability application, so that achieving minimum active area and very low power consumption are the main objectives for the presented design. Experimental results of the first version of the modulator show 8 bits of Effective-Number-Of-Bits (ENOB) in a 25 kHz signal bandwidth with 7 μW of power consumption. The proposed implementation has also shown to be very robust against supply voltage and bias current variations. A second approach has also been designed, using the same principle of operation, in order to increase the input voltage range without any power consumption penalty at the expense of decreasing the input impedance and stingily increased area. This second approach shows 9 bits of ENOB in the same signal bandwidth with a power consumption of 4.35 μW. A Figure Of Merit (FOM) of 0.267 pJ/state has been achieved with a total area consumption (without pads) of 110 μm×125 μm in a 0.35 μm CMOS technology.     

Design techniques of low-power embedded EEPROM for passive RFID tag

This paper presents an optimized embedded EEPROM design approach which has reduced the power significantly in a short-range passive RFID tag. The proposed array control circuit employs an improved structure to minimize the leakage of memory bit cells. With the proposed array circuit design, the passive RFID tag can operate drawing a low quiescent current. The RFID tag with the proposed EEPROM was fabricated in a standard 0.35-μm four-metal two-poly CMOS process. Measurement results show that the erasing/writing current is 45 μA, and reading current consumption is 3 μA with a supply voltage of 3.3 V. The data read time is 300 ns/bit.     

A novel ultra low power ASK demodulator for a passive UHF RFID tag compatible with C1 G2 EPC standard protocol

In order to reduce the power consumption of RFID tags and increase the reading range of RFID systems, this paper proposes an ASK demodulator that uses a new approach to reduce the threshold voltage of diode connected MOS transistors as an obstacle in the design of the envelope detector. Also, an ultra low power comparator is used for further power reduction. This circuit has been simulated in a 0.18 μm CMOS technology to satisfy EPC Class 1 Generation 2 standard protocol emphasizing on the reduction of power consumption. The proposed circuit can correctly demodulate the minimum input RF signal amplitude of 180 mV for modulation depths of 55–100 % with 40–160 kb/s data rates. A total power consumption of less than 290 nW is achieved at a 1.2 V power supply. Effects of the input signal additive white noise as well as the process and temperature variations on the signal demodulation is also investigated in this paper.     

Ultra-low power PSK backscatter modulator for UHF and microwave RFID transponders

An integrated circuit implementation of a PSK backscatter modulator for passive radio frequency identification (RFID) transponders is proposed. Such modulator offers a significant reduction of the power consumption with respect to other schemes already presented in the literature. Furthermore, the topology of the proposed modulator allows us to control its output resistance so that only a negligible fraction of the active power at the antenna goes to the modulator.     

超高频无源RFID标签的一些关键电路的设计

本文针对超高频无源RFID标签芯片的设计,给出了一些关键电路的设计考虑。文章从UHFRFID标签的基本组成结构入手,先介绍了四种电源恢复电路结构,以及在标准CMOS工艺下制作肖特基二极管来组成倍压电路的解决方案。然后针对电源稳压电路,提出了串联型和并联型两种稳压电路。文章针对ASK包络解调电路,提出了新的泄流源的设计。最后,文章介绍了启动信号产生电路的设计考虑。     

A 0.6 V and 0.395 pJ/bit nonius TDC for a passive RFID pressure sensor tag

This work presents a nonius time to digital converter (TDC) adapted to a passive RF identification (RFID) pressure sensor tag. The proposed converter exploits the characteristics of time-based sensor interfaces and allows reducing voltage supply and power consumption while maintaining resolution and conversion efficiency. The nonius TDC has been designed and fabricated using the TSMC 90 nm standard CMOS technology. The main blocks of the converter are described and both the resolution adjustment and measurement processes are explained in detail. Measurement results show 10.49 bits of effective resolution for an input time range from 28.19 to 42.93 μs. With a sampling rate of 19 KS/s the converter has a conversion efficiency of 0.395 pJ/bit with a voltage supply of only 0.6 V. This characteristics in the proposed nonius TDC enables an increased reading range of the passive RFID pressure sensor tag.     

智能滑套内低频段RFID 标签识别率的研究

实际应用中智能滑套内低频段RFID 标签存在识别率低的问题,从射频识别技术的工作机理出发,借助MATLAB 仿真软件,对低频螺线管天线感应电压特性进行了仿真分析,讨论了读写器天线长度和内径对识别率的影响,提出了基于井下智能滑套的RFID 通信系统最佳天线部署。同时为减弱井下复杂工况环境对标签识别率的影响,设计了读写器天线自适应阻抗匹配系统,建立一套基于井下RFID 通信系统识别率的模拟试验平台,验证仿真设计结果的正确性。     

无源UHF RFID标签的低成本阻抗匹配网络设计

提出了一种符合ISO/IEC18000-6C标准的无源RFID(射频识别)标签的低成本阻抗匹配网络。该设计基于复功率波反射系数的概念,修正芯片输入阻抗,在片内添加阻抗匹配电路。通过变化芯片阻抗和天线共轭匹配及失配间切换,有效完成信号的调制反射。提出的电路结构简单,易于实现,在读写器、标签天线和芯片之间实现了功率传输的最大化,提高了芯片输入电压以及读写器对标签反射信号的识别率。采用该阻抗匹配网络的芯片基于chartered 0.35μm CMOS工艺实现。测试结果表明,在923MHz频带下,倍压电路输出可达1.47V,标签满足系统设计要求。     

应用于无源UHF RFID传感器接口的低功耗低压转换器设计

为了增加射频识别（RFID）传感器的识读范围,针对无源超高频（ultra high frequency,UHF）RFID标签的传感器接口,提出了一种新的低功耗低压时间数字转换器设计。该传感器接口采用基于游标原理的高效时数转换器,在保证分辨率和转换效率的同时,能够实现较低的功耗和较大的动态范围。采用TSMC 90nm标准CMOS技术设计并制造。测量结果显示相比其他类似结构,提出接口在输入时间范围28.18-42.94 时有效分辨率为10.48bits。采样率为20 KS/s时,转换器转化效率为0.396 pJ/bit,且功耗和电压供应分别仅为3.84 和0.6V,能够有效增强无源UHF RFID压力传感器标签的识读范围。     

A low power reconfigurable multi-mode continuous time Delta Sigma modulator for seven different mobile standards with VCO-based quantizer

In this research a novel low power multi-mode continuous time Delta Sigma modulator was designed to be compatible with many mobile wireless standards. This modulator has a reconfigurable structure to adapt to various standards from 0.2 to 20 MHz. The designed modulator uses a VCO-based quantizer not only for lowering power consumption, but also for reducing the required chip area. The presented modulator can function with up to third order of noise shaping, or in a low power mode in which the loop filter is disabled and only the VCO-based quantizer is used. The proposed modulator was implemented and simulated in transistor level in 180 nm technology. This modulator can digitize at least seven standards (LTE (20 MHz)/WLAN/LTE (9 MHz)/WCDMA/UMTS/Bluetooth/GSM) with a favorable dynamic range (65–89 dB) and power consumption (9.1 mW–670 μW).     

An RFID Tag Using a Planar Inverted‐F Antenna Capable of Being Stuck to Metallic Objects

This letter presents the design for a low‐profile planar inverted‐F antenna (PIFA) that can be stuck to metallic objects to create a passive radio frequency identification (RFID) tag in the UHF band. The designed PIFA, which uses a dielectric substrate for the antenna, consists of a U‐slot patch for size reduction, several shorting pins, and a coplanar waveguide feeding structure to easily integrate with an RFID chip. The impedance bandwidth and maximum gain of the tag antenna are about 0.3% at 914 MHz for a voltage standing wave ratio (VSWR) of less than 2 and 3.6 dBi, respectively. The maximum read range is about 4.5 m as long as the tag antenna is on a metallic object.     

UHF RFID无源标签的芯片供电机理

介绍了UHF RFID无源标签的供电特点,即采用无线功率传输供电,或利用片上储能电容充放电实现对芯片电路供电。同时为保证通信需求,应该做到充电与放电供需平衡,可取的设计是将标签所接收的射频能量大部分用于浮充供电;为集中更多能量用于浮充供电,应当尽量减少射频能量的其它应用消耗,包括接收时段的解调解码、应答时段的调制和发送。     

无源UHFRFID标签芯片基带处理器的低功耗设计

在分析ISO18000-6C标准内容的基础上,提出了一种基带处理器的结构,设计了一款符合ISO18000-6C标准的UHF RFID标签芯片的基带处理器。该基带处理器可支持协议规定的所有强制命令。设计通过降低工作电压、降低工作频率、使用门控时钟、增加功耗管理模块等一系列低功耗设计以降低处理器的功率消耗。在Xillinx的Virtex-4FPGA上验证满足协议功能要求,并在工作电压为1V,时钟为1.92MHz时,功耗仿真结果为9.9μW,很好的完成了低功耗电子标签的基带处理器设计。     

Power reflection coefficient analysis for complex impedances in RFID tag design

Kurokawa's method of calculating the power reflection coefficient from the Smith chart in the situation when one complex impedance is directly connected to another is applied to passive RFID tag design, where power reflection is important, as it determines the tag characteristics. The performance analysis of a specific RFID tag is presented together with experimental data, which is in close agreement with the theory.     

UHF RFID标签基带处理器的低功耗设计

随着超高频RFID标签的应用越来越广泛,在提高其性能上的需求也越来越迫切.对于无源标签,工作距离是一个非常重要的指标.要提高工作距离,就要降低标签的功耗.着重从降低功耗方面阐述了一款基于ISO18000-6 Type C协议的UHF RFID标签基带处理器的设计.简要介绍了设计的结构,详细阐述了各种低功耗设计技术,如动态控制时钟频率、寄存器复用、使用计数器和组合逻辑代替移位寄存器、异步计数器、门控时钟等的应用.结果证明,这些措施有效地降低了功耗,仿真结果为在工作电压为1 V,时钟为2.5 MHz时,功耗为4.8 μW;目前实现了前三项措施的流片,测试结果表明工作电压为1 V,时钟为2.5 MHz时,功耗为8.03 μW.     

用于金属表面的UHF RFID标签天线优化设计

UHF RFID 标签天线置于金属表面会引起阻抗变化以及阻抗失配,因此为了减小金属表面的影响,提出一种用于金属表面的UHF RFID 标签天线阻抗匹配优化设计方法。首先在折叠偶极子天线臂上附加短路段来调整标签天线的输入阻抗,通过粗略调节短路段的位置使天线和RFID 标签芯片在金属表面达到阻抗的基本匹配,然后利用遗传算法优化得到天线最优的长度、宽度和短路段位置,使天线和RFID 标签芯片在金属表面达到准确的阻抗匹配。所设计天线阻抗及方向图的仿真和测试结果表明该优化设计方法能够使RFID 标签天线在金属表面正常工作。     

集成高效率电荷泵的无源电子标签芯片射频前端设计

提出了一种满足ISO/IEC18000-6C标准的无源超高频RFID(射频识别)标签芯片的射频前端结构,该结构包括高效率电荷泵、解调器、调制器、阻抗匹配网络和ESD保护电路。电荷泵通过阈值补偿原理及精确控制补偿电压有效抑制反向漏电流,消除了传统电荷泵中的阈值损失。芯片经TSMC0.18μm CMOS mixed signal工艺流片,实测结果表明,标签最远读距离达7m,写距离为3m,可应用于识别与定位,同时满足HBM2 000V的抗静电指标。     

一种低功耗有源射频识别系统的设计

研究了一种低功耗有源射频识别系统组网与设计技术,该系统可在软硬件两方面实现低功耗设计。在硬件方面,采用NORDIC公司的nRF24LE1芯片作为有源标签,nRF24L01+芯片作为节点射频芯片,STM32单片机作为节点控制芯片,实现了芯片与节点的注册与通信;软件方面,采用时分复用方法,合理分配有源芯片的时隙,设计了防冲突机制,使得芯片在极端的时间内工作,实现了低功耗组网通信。     

Multilevel outphasing system using six-port modulators and doherty power amplifiers

In this paper, a simple and efficient architecture for implementation of multilevel outphasing systems is presented. The architecture consists of a six-port modulator and a Doherty power amplifier in each outphasing branch. Pin diodes are used as variable impedances of the six-port modulator and their parasitic elements are analytically compensated. A prototype of the variable load is fabricated and the results show the effectiveness of compensation method to prepare pin diodes as variable loads for a six-port modulator. As a proof of concept, a standard 2.4 GHz Doherty power amplifier is designed with 65% efficiency at peak power and 46% efficiency at 6 dB back off. The proposed system is simulated in advanced design system using a 20 MHz WLAN signal with 7.5 dB PAPR and 5 level outphasing. Simulation results show 31.6% power added efficiency for the Doherty-Outphasing system.     

Analysis and design of power efficient semi-passive RFID tag

The analysis and design of a semi-passive radio frequency identification(RFID) tag is presented.By studying the power transmission link of the backscatter RFID system and exploiting a power conversion efficiency model for a multi-stage AC-DC charge pump,the calculation method for semi-passive tag's read range is proposed.According to different read range limitation factors,an intuitive way to define the specifications of tag's power budget and backscatter modulation index is given.A test chip is implemen...