A novel ultra low power ASK demodulator for a passive UHF RFID tag compatible with C1 G2 EPC standard protocol

In order to reduce the power consumption of RFID tags and increase the reading range of RFID systems, this paper proposes an ASK demodulator that uses a new approach to reduce the threshold voltage of diode connected MOS transistors as an obstacle in the design of the envelope detector. Also, an ultra low power comparator is used for further power reduction. This circuit has been simulated in a 0.18 μm CMOS technology to satisfy EPC Class 1 Generation 2 standard protocol emphasizing on the reduction of power consumption. The proposed circuit can correctly demodulate the minimum input RF signal amplitude of 180 mV for modulation depths of 55–100 % with 40–160 kb/s data rates. A total power consumption of less than 290 nW is achieved at a 1.2 V power supply. Effects of the input signal additive white noise as well as the process and temperature variations on the signal demodulation is also investigated in this paper.     

Ultra-low power PSK backscatter modulator for UHF and microwave RFID transponders

An integrated circuit implementation of a PSK backscatter modulator for passive radio frequency identification (RFID) transponders is proposed. Such modulator offers a significant reduction of the power consumption with respect to other schemes already presented in the literature. Furthermore, the topology of the proposed modulator allows us to control its output resistance so that only a negligible fraction of the active power at the antenna goes to the modulator.     

A low power CMOS compatible embedded EEPROM for passive RFID tag

A 512-bit low-voltage CMOS-compatible EEPROM is developed and embedded into a passive RFID tag chip using 0.18 μm CMOS technology. The write voltage is halved by adopting a planar EEPROM cell structure. The wide Vth distribution of as-received memory cells is mitigated by an initial erase and further reduced by an in-situ regulated erase operation using negative feedback. Although over-programmed charges leak from the floating gates over several days, the remaining charges are retained without further loss. The 512-bit planar EEPROM occupies 0.018 mm² and consumes 14.5 and 370 μW for read and write at 85 °C, respectively.     

应用于无源UHF RFID传感器接口的低功耗低压转换器设计

为了增加射频识别（RFID）传感器的识读范围,针对无源超高频（ultra high frequency,UHF）RFID标签的传感器接口,提出了一种新的低功耗低压时间数字转换器设计。该传感器接口采用基于游标原理的高效时数转换器,在保证分辨率和转换效率的同时,能够实现较低的功耗和较大的动态范围。采用TSMC 90nm标准CMOS技术设计并制造。测量结果显示相比其他类似结构,提出接口在输入时间范围28.18-42.94 时有效分辨率为10.48bits。采样率为20 KS/s时,转换器转化效率为0.396 pJ/bit,且功耗和电压供应分别仅为3.84 和0.6V,能够有效增强无源UHF RFID压力传感器标签的识读范围。     

用于超高频标签芯片的低功耗高稳定时钟电路

提出一种适用于无源超高频射频识别(UHF RFID)标签芯片的时钟产生电路。电路使用N型金属-氧化物-半导体(NMOS)栅极电压取代了复杂的比较器电路作为比较电平,精简了电路结构,降低了电路功耗,减小了版图面积;使用二极管方式连接的NMOS管作温度及工艺补偿感应管,利用其栅压变化控制充放电电流,使其在不同工艺角下,当温度在较大范围内变化时,均能实现输出频率稳定。采用中芯国际0.18 μm工艺进行仿真验证,结果表明：当电源电压为1 V,基准电流为130 nA时,电路功耗仅为447 nW;在工艺角由ss变化到ff的过程中,输出频率偏差不超过2.43%,;温度在-40~90 ℃范围变化时,输出频率偏差小于0.99%,适合无源射频识别标签芯片使用。     

Design of a passive UHF RFID tag for the ISO18000-6C protocol

This paper presents a new fully integrated wide-range UHF passive RFID tag chip design that is compatible with the ISO18000-6C protocol.In order to reduce the die area,an ultra-low power CMOS voltage regulator without resistors and an area-efficient amplitude shift keying demodulator with a novel adaptive average generator are both adopted.A low power clock generator is designed to guarantee the accuracy of the clock under±4%. As the clock gating technology is employed to reduce the power consumption of the baseband processor,the total power consumption of the tag is about 14μW with a sensitivity of-9.5 dBm.The detection distance can reach about 5 m under 4 W effective isotropic radiated power.The whole tag is fabricated in TSMC 0.18μm CMOS technology and the chip size is 880×880μm~2.     

面向ISO18000-6C协议的无源超高频射频识别标签芯片设计

本文提出了一种面向ISO18000-6C协议的无源超高频射频识别标签芯片设计。为了降低芯片的成本和功耗,本文设计了一种低功耗且不含电阻的稳压电路,一种低功耗且频率精度达到4%的时钟产生电路,以及一种新颖的具有大动态范围的ASK解调电路。本文还阐述了基于门控时钟技术的低功耗数字基带电路设计。该标签芯片的总功耗约为14微瓦,灵敏度达到-9.5dBm,读取距离可达5米。整个标签采用TSMC 0.18um CMOS工艺实现,芯片尺寸为880um880um。     

基于EPC C1G2协议的RFID系统数据编码

针对在EPC C1G2协议下的UHF RFID系统数据编码方式的实现进行研究。对于该系统前向链路PIE码的编码,提出了一种利用读写器的MPU调用软件进行编码的方法。再进行信号调制。该系统反向链路采用FM0码或采用Miller码调制副载波。提出了一种新的FM0码的编码方法,并在Simulink平台中使用数字逻辑器件和触发器搭建了其仿真模型且进行了仿真实现。同样运用该思路实现了Miller码的编码仿真。另外还实现了含有多个副载波周期的Miller码编码。这些解决方案有利于提高系统性能。     

基于EPC C1G2协议的RFID系统数据解码

RFID系统中数据解码模块的性能对整个系统影响极大。对基于EPC C1G2协议的UHF RFID系统数据解码进行研究,讨论了目前该系统前向链路的PIE码解码的主要理论基础。该系统的反向链路采用FM0码或采用Miller码调制副载波,提出了一种新的解码实现方法,即利用时钟信号将收到的每个数据的前半个周期分解为一路信号,后半个周期分解为另一路信号然后再运用基本数字逻辑器件进行解码。在Simulink平台下运用该方法分别搭建仿真模型实现了FM0码的解码和含有多个副载波周期的Miller码的解码。     

符合EPC C1G2标准的UHF RFID阅读器数字基带ASIC实现

为了实现UHF RFID单芯片阅读器,提出了一种UHF RFID阅读器数字基带的电路结构.该数字基带基于EPC Global Classl Gen2标准,对PIE编码、升余弦滤波器、希尔伯特滤波器、CRC5/16校验单元、FIR和IIR信道滤波器、采样电路、FM0译码、碰撞检测、控制单元等模块进行算法级、RTL级、网表级和物理级版图设计,后仿各项功能正确,符合系统要求.按照标准ASIC设计流程进行物理设计实现,并采用IBM 0.13 μm 8金属的RF数模混合工艺流片.设计的RFID数字基带系统约27万门,面积为3 mm×3 mm,可应用于单芯片RFID阅读器.     

High Security FeRAM‐Based EPC C1G2 UHF (860 MHz‐960 MHz) Passive RFID Tag Chip

The metal‐ferroelectric‐metal (MFM) capacitor in the ferroelectric random access memory (FeRAM) embedded RFID chip is used in both the memory cell region and the peripheral analog and digital circuit area for capacitance parameter control. The capacitance value of the MFM capacitor is about 30 times larger than that of conventional capacitors, such as the poly‐insulator‐poly (PIP) capacitor and the metal‐insulator‐metal (MIM) capacitor. An MFM capacitor directly stacked over the analog and memory circuit region can share the layout area with the circuit region; thus, the chip size can be reduced by about 60%. The energy transformation efficiency using the MFM scheme is higher than that of the PIP scheme in RFID chips. The radio frequency operational signal properties using circuits with MFM capacitors are almost the same as or better than with PIP, MIM, and MOS capacitors. For the default value specification requirement, the default set cell is designed with an additional dummy cell.     

一种符合EPC C1G2标准的RFID随机化密钥双向认证协议

RFID系统已广泛地应用于自动识别领域等,但RFID系统也给使用者的隐私和安全带来新的威胁.现有已提出的安全协议方案,基本上都存在着某种安全隐患或不符合EPC ClG2(electronicproduct code class1 generation2)标准要求,无法成为实际可用的RFID系统安全机制,本文在介绍了两种符合EPC ClG2标准的安全协议并分析其存在的弱点后,提出一种新的设计方案--随机化密钥双向认证协议,并分析其安全性能.     

Full passive UHF RFID Tag with an ultra-low power,small area,high resolution temperature sensor suitable for environment monitoring

An UHF RFID Tag with an ultra-low power, small area, high resolution temperature sensor which adopted double voltage-controlled oscillators (VCO) has been designed and implemented using the SMIC CMOS 0.18 μm EEPROM 2P4M process. The core area of the tag (excluding the test bounding pad) is only 756×967 μm². The power-optimized tag allows a communication range of more than 6 m from a 1 W effective radiated output power reader.     

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags in conformance with ISO/IEC 18000-3 protocol

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags is presented in this paper. The design of the RF analog front-end and digital control is based on ISO/IEC 18000-3 MODE 1 protocol. This paper mainly focuses on RF analog front-end circuits. In order to supply voltage for the whole tag chip, a high efficiency power management circuit with a rather wide input range is proposed by utilizing 15.5 V high voltage MOS transistors. Furthermore, a high sensitivity, low power consumption 10% ASK demodulator with a subthreshold-mode hysteresis comparator is introduced for reader-to-tag communication. The tag chip is fabricated in 0.18-μm 2-poly 5-metal mixed signal CMOS technology with EEPROM process. An on-chip 1 kb EEPROM is used to support tag identification, data writing and reading. The core size of the analog front-end is only 0.94×0.84 mm² with a power consumption of 0.42 mW. Measured results show that the power management circuit is able to maintain a proper working condition with an input antenna voltage range of 5.82–12.3 V; the maximum voltage conversion ratio of the rectifier reaches 65.92% when the tag antenna voltage is 9.42 V. Moreover, the power consumption of the 10% ASK demodulator is only 690.25 nW.     

符合EPC C1G2标准的阅读器数字基带编解码模块设计和FPGA验证

编解码模块是RFID阅读器数字基带的重要模块,负责对来自数据存储单元的信号编码以及对来自采样模块的信号解码.本文设计了符合EPC C1G2标准的阅读器数字基带部分的编解码模块,并且在FPGA上验证.编解码模块包括CRC编码和校验,PIE编码,FM0解码.FFGA验证结果显示该设计能够在协议规定的频率范围内正常工作.