A low-powerlow-voltage slew-rate enhancement circuit for two-stage operational amplifiers

正A novel circuit is presented in order to enhance the slew rate of two-stage operational amplifiers.The enhancer utilizes the class-AB input stage to improve current efficiency,while it works on an open loop with regard to the enhanced amplifier so that it has no effect on the stability of the amplifier.During the slewing period,the enhancer detects input differential voltage of the amplifier,and produces external enhancement currents for the amplifier,driving load capacitors to charge/discharge faster.Simulation results show that,fora large input step,the enhancerreduces settling time by nearly 50%.When the circuit is employed in a sample-and-hold circuit,it greatly improves the spur-free dynamic range by 44.6 dB and the total harmonic distortion by 43.9 dB.The proposed circuit is very suitable to operate under a low voltage(1.2 V or below) with a standby current of 200μA.     

基于Marx发生器的快速Q开关驱动电路设计

针对电光Q开关要求速度快的特点,提出基于Marx发生器的高压快速调Q驱动电路的设计方法。利用高压模块产生一级高压为并联电容充电,采用变压器隔离驱动8路MOS管。当触发信号引入时,功率MOS管导通使电容串联同时放电,从而电压倍增获得快速的高压脉冲。实验结果表明:通过该方法获得了上升沿12 ns,幅值3 000~4 000 V数字可调的高压脉冲波形。相比于传统脉冲变压器法的波形,上升时间减小了近35 ns。此调Q电路已应用于激光二极管（LD）泵浦的固体Nd:YAG激光器中,且长期稳定工作。     

Gain and offset correction methods for analog-to-digital converters

This paper describes a simple offset error (OEC) and two gain error (GEC) correction methods for an analog–digital converter (ADC), which use a dedicated sample-and-hold (S/H) circuit. These three methods are specifically proposed for switched- capacitor (SC) S/H circuits. In these methods, few unit capacitors of main S/H-capacitor are separated for correction. OEC method and one of GEC method uses bottom-plate sampling to correct the sampled voltage. The second GEC method uses charge sharing method between capacitors.     

High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design

In a modern high density VLSI design, with higher operating frequency and technology scaling, small critical charge in circuit nodes significantly increases susceptibility to radiation induced transient faults. In this paper, we propose a high efficiency hardened latch using the undesired delay of Schmitt trigger circuit and a special feedback loop to a comparator to build a low overhead time redundancy scheme. The proposed structure masks internal node transient faults also improves the recovery of the output node by transferring the faulty output in two different paths to the comparison circuit’s inputs. Experimental results, simulated in 45 nm CMOS technology, show an acceptable increase in the critical charge compared with the previous hardened latches, with a fair increase in power, delay and area. Monte Carlo simulations have also confirmed the proposed latch resistance to the process, voltage and temperature variations.     

基于拱形结构的摩擦-压电复合式能量采集器

随着纳米技术和加工工艺的发展,纳米发电机被提出用于将自然界中微弱低频振动机械能转化为电能,进而为小型传感系统长续航工作提供可能.基于摩擦纳米发电机和压电纳米发电机的电荷积累与转移规律,设计了拱形结构并构建了摩擦-压电复合式能量采集器,将两种力-电转换模式有效整合,并突破了以往能量采集器只能收集垂直方向机械能的限制.搭建...     

电容电荷守恒和电感磁链守恒的条件

动态电路换路时，若存在由纯电容和理想电压源构成的回路，则电容电压就有可能跃变，在含电压可能跃变的电容支路的割集中，若除电容支路外的支路中无冲激电流存在，则电容电荷守恒，否则电容电荷有可能不守恒；若存在由纯电感和理想电流源构成的割集，则电感电流就有可能跃变，在含电流可能跃变的电感支路的回路中，若除电感支路外的支路中无冲激电压存在，则电感磁链守恒，否则电感磁链有可能不守恒。文中同时给出了电容电荷不守恒和电感磁链不守恒时电路初始条件的求解方法。     

A 1-GHz Charge Pump PLL Frequency Synthesizer for IEEE 1394b PHY

The design procedure of an 1-GHz phase-locked loop (PLL)-based frequency synthesizer used in IEEE 1394b physical (PHY) system is presented in this paper. The PLL’s loop dynamics are analyzed in depth and theoretical relationships between all loop parameters are clearly described. All the parameters are derived and verified by Verilog-A model, which ensures the accuracy and efficiency of the circuit design and simulation. A 4-stage ring oscillator is employed to generate 1-GHz oscillation frequency and is divided into low frequency clocks by a feedback divider. The architecture is a third-order, type-2 charge pump PLL. The simulated settling time is less than 4μs. The RMS value of period jitter of the PLL’s output is 2.1 ps. The PLL core occupies an area of 0.12 mm2, one fourth of which is occupied by the MiM loop capacitors. The total current consumption of the chip is 16.5 mA. The chip has been sent for fabrication in 0.13 m complementary metal oxide semiconductor (CMOS) technology.     

Trap‐Assisted Recombination via Integer Charge Transfer States in Organic Bulk Heterojunction Photovoltaics

Organic photovoltaics are under intense development and significant focus has been placed on tuning the donor ionization potential and acceptor electron affinity to optimize open circuit voltage. Here, it is shown that for a series of regioregular‐poly(3‐hexylthiophene):fullerene bulk heterojunction (BHJ) organic photovoltaic devices with pinned electrodes, integer charge transfer states present in the dark and created as a consequence of Fermi level equilibrium at BHJ have a profound effect on open circuit voltage. The integer charge transfer state formation causes vacuum level misalignment that yields a roughly constant effective donor ionization potential to acceptor electron affinity energy difference at the donor–acceptor interface, even though there is a large variation in electron affinity for the fullerene series. The large variation in open circuit voltage for the corresponding device series instead is found to be a consequence of trap‐assisted recombination via integer charge transfer states. Based on the results, novel design rules for optimizing open circuit voltage and performance of organic bulk heterojunction solar cells are proposed.     

自偏置锁相环结构及其稳定性条件分析

给出了基于自偏置技术的电荷泵锁相环电路,压控振荡器的工作频率动态地建立了电路内部所有的偏置电压和电流,从而实现了固定衰减因子,固定环路带宽与工作频率之比,这二者由电容的比率决定,极大地实现了电路设计的工艺无关性,同时也得到了小的相位抖动,最后,对这种锁相环的稳定性进行了一定的分析。     

A new inverter-based charge pump circuit with high conversion ratio and high power efficiency

The current paper presents a new inverter-based charge pump circuit with high conversion ratio and high power efficiency. The proposed charge pump, which consists of a PMOS pass transistor, inverter-based switching transistors, and capacitors, can improve output voltage and conversion ratio of the circuit. The proposed charge pump was fabricated with TSMC 0.35 μm 2P4M CMOS technology. The chip area without pads is only 0.87 mm×0.65 mm. The measured results show that the output voltage of the four-stage charge pump circuit with 1.8 V power supply voltage (V_DD=1.8 V) can be pumped up to 8.2 V. The proposed charge pump circuit achieves efficiency of 60% at 80 μA.     

A novel interface circuit for triboelectric nanogenerator

For most triboelectric nanogenerators (TENGs), the electric output should be a short AC pulse, which has the common characteristic of high voltage but low current. Thus it is necessary to convert the AC to DC and store the electric energy before driving conventional electronics. The traditional AC voltage regulator circuit which commonly consists of transformer, rectifier bridge, filter capacitor, and voltage regulator diode is not suitable for the TENG because the transformer''s consumption of power is appreciable if the TENG output is small. This article describes an innovative design of an interface circuit for a triboelectric nanogenerator that is transformerless and easily integrated. The circuit consists of large-capacity electrolytic capacitors that can realize to intermittently charge lithium-ion batteries and the control section contains the charging chip, the rectifying circuit, a comparator chip and switch chip. More important, the whole interface circuit is completely self-powered and self-controlled. Meanwhile, the chip is widely used in the circuit, so it is convenient to integrate into PCB. In short, this work presents a novel interface circuit for TENGs and makes progress to the practical application and industrialization of nanogenerators.     

A Fundamental 90-GHz CMOS VCO Using New Ring-Coupled Quad

A new circuit topology, named ring-coupled quad for millimeter-wave voltage controlled oscillator (VCO) design, is proposed. The proposed circuit topology provides higher open loop voltage gain than conventional cross-coupled pair. The layout of the proposed ring-coupled quad is fully symmetric without additional interconnection lines. A 90-GHz VCO using 90-nm CMOS process is implemented with this ring-coupled quad. This 90-GHz oscillator demonstrates a 2.5-GHz tuning range and higher than -20dBm output power. The proposed ring-coupled quad is suitable for the realization of high frequency VCOs     

2.488 Gbit/s时钟数据恢复电路的设计

利用Cadence集成电路设计软件,基于SMIC 0.18 μm 1P6M CMOS工艺,设计了一款2.488 Gbit/s三阶电荷泵锁相环型时钟数据恢复(CDR)电路.该CDR电路采用双环路结构实现,为了增加整个环路的捕获范围及减少锁定时间,在锁相环(PLL)的基础上增加了一个带参考时钟的辅助锁频环,由锁定检测环路实时监控频率误差实现双环路的切换.整个电路由鉴相器、鉴频鉴相器、电荷泵、环路滤波器和压控振荡器组成.后仿真结果表明,系统电源电压为1.8V,在2.488 Gbit/s速率的非归零(NRZ)码输入数据下,恢复数据的抖动峰值为14.6 ps,锁定时间为1.5μs,功耗为60 mW,核心版图面积为566 μm×448μm.     

CMOS PWM D类音频功率放大器的过流保护电路

基于Class-D音频功率放大器的应用,采用失调比较器及单边迟滞技术,提出了一种过流保护电路,其核心为两个CMOS失调比较器。整个电路基于CSMC0.5μmCMOS工艺的BSIM3V3Spice典型模型,采用Hspice对比较器的特性进行了仿真。失调比较器的直流开环增益约为95dB,失调电压分别为0.25V和0.286V。仿真和测试结果显示,当音频放大器输出短路或输出短接电源时,过流保护电路都能正常启动,保证音频放大器不会受到损坏,能完全满足D类音频放大器的设计要求。过流保护电路有效面积为291μm×59.5μm。     

基于Matlab的三相桥式SPWM逆变器建模与仿真

对三相桥式逆变电路原理及其SPWM控制原理进行简单的分析,针对开环SPWM电压的不稳定提出一种电压闭环SPWM控制模型。在Matlab/Simulink软件环境中分别建立了三相SPWM逆变器开环仿真模型和具有电压调节作用的SPWM闭环仿真模型,分别对其进行仿真分析。仿真结果表明电压闭环SPWM控制比开环SPWM控制具有更好的动静态特性。得出的结论对三相桥式逆变器的原理的理解、参数的确定、电路的设计有一定的参考价值和指导意义。     

双腔准分子激光器脉冲充电电源的研究

为了满足工业用振荡-放大双腔结构的准分子激光器放电激励技术的要求,设计了高重频高精度的脉冲充电电源.该电源采用LC谐振倍压的方式,同时为双腔准分子激光器的充电电容器进行充电,倍压比为1.87.通过对电源工作时序的调节,实现千赫兹高重频放电激励,在电源输出电压约为1300V时,充电电压精度为0.18%.结果表明,通过充电电压精度控制单元,对充电电压反馈调节,可以实现充电电压的高精度.     

一种动态补偿、高稳定性的LDO设计

设计并实现了一种动态补偿、高稳定性的LDO.针对LDO控制环路稳定性随负载电流变化的特点,给出一种新颖的动态补偿电路.这种补偿电路能很好地跟踪负载电流的变化,从而使控制环路的稳定性几乎与负载电流无关.设计采用CSMC 0.5μm标准CMOS工艺,利用Cadence的EDA工具完成电路设计、版图绘制和流片测试,最终芯片面...     

一种适用于低ESR应用的高精度RBCOT环路

提出了一种适用于低ESR电容、具有快速瞬态响应和高输出精度的纹波控制COT(RBCOT)实现电路,并利用改进的等效三端开关模型,对包含分压网络的控制环路进行了精确的小信号建模。该环路在保持快速瞬态响应能力的同时,利用SW点的1阶滤波信号来产生虚拟电感电流纹波,避免了次谐波振荡现象。通过谷值采样电路,对滤波信号的谷值进行采样。采样电路在每个开关周期执行刷新操作,并在上电和瞬态变化阶段进行加速充电。纹波叠加电路将增强纹波和谷值采样信号精确地叠加到反馈电压端,保证电路输出精度较高。采用0.35μm 18 V BCD工艺,对纹波控制COT控制环路进行仿真。结果表明,在4.5~18 V输入电压范围内,输出电压的失调在1 mV范围以内,控制环路可以对瞬态变化进行快速调整。     

A CMOS micro power switched-capacitor DC–DC step-up converter for indoor light energy harvesting applications

This paper presents a micro power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si:H PV) cells, processed by a switched capacitor (SC) voltage doubler circuit with maximum power point tracking (MPPT), and finally stored in a large capacitor. The MPPT fractional open circuit voltage (V_OC) technique is implemented by an asynchronous state machine (ASM) that creates and dynamically adjusts the clock frequency of the step-up SC circuit, matching the input impedance of the SC circuit to the maximum power point condition of the PV cells. The ASM has a separate local power supply to make it robust against load variations. In order to reduce the area occupied by the SC circuit, while maintaining an acceptable efficiency value, the SC circuit uses MOSFET capacitors with a charge sharing scheme for the bottom plate parasitic capacitors. The circuit occupies an area of 0.31 mm² in a 130 nm CMOS technology. The system was designed in order to work under realistic indoor light intensities. Experimental results show that the proposed system, using PV cells with an area of 14 cm², is capable of starting-up from a 0 V condition, with an irradiance of only 0.32 W/m². After starting-up, the system requires an irradiance of only 0.18 W/m² (18 μW/cm²) to remain operating. The ASM circuit can operate correctly using a local power supply voltage of 453 mV, dissipating only 0.085 μW. These values are, to the best of the authors’ knowledge, the lowest reported in the literature. The maximum efficiency of the SC converter is 70.3 % for an input power of 48 μW, which is comparable with reported values from circuits operating at similar power levels.     

A feedback loop regulated bootstrap driver circuit with improved drive capability for high voltage buck DC–DC converter

A novel bootstrap driver circuit applied to high voltage buck DC–DC converter is proposed. The gate driver voltage of the high side switch is regulated by a feedback loop to obtain accurate and stable bootstrapped voltage. The charging current of bootstrap capacitor is provided by the input power of the DC–DC converter directly instead of internal low voltage power source, so larger driver capability of the proposed circuit can be achieved. The bootstrap driver circuit starts to charge the bootstrap capacitor before the switch node SW drop to zero voltage at high-side switch off-time. Thus inadequate bootstrap voltage is avoided. The proposed circuit has been implemented in a high voltage buck DC–DC converter with 0.6 µm 40 V CDMOS process. The experimental results show that the bootstrap driver circuit provides 5 V stable bootstrap voltage with higher drive capability to drive high side switch. The proposed circuit is suitable for high voltage, large current buck DC–DC converter.