A novel open-loop high-speed CMOS sample-and-hold

A new open-loop high-speed CMOS sample-and-hold is presented. Based on new method for further reduction of voltage-dependent charge injection, a new CMOS sample-and-hold was designed. Simulation results confirm the effectiveness of this method. Over 10 dB improvement in signal-to-noise ratio, compared to the signal-to-noise ratio of conventional bottom plate sampling S/Hs was achieved with this method. A comparison between newly designed S/H and the bottom-plate sampling S/H is presented.     

A highly linear open-loop high-speed CMOS sample-and-hold

This paper presents an open loop high speed CMOS sample and hold with improved linearity. Previously, an open-loop S/H and a method of charge injection cancellation were introduced (Hadidi et al. in The 2006 International Conference on Solid State Devices and Materials 604–605, 2006). However, it requires many clock phases. In this paper a new charge injection cancellation scheme and switch linearization method is introduced. The proposed S/H could be implemented in a simple manner in contrast with the previous one while its linearity has been improved (especially in near nyquist frequencies). The proposed S/H with sampling rate of 500 MS/s achieves SNDR of 76 dB at nyquist single-tone input signal and SNDR of 72.5 dB at near nyquist dual-tone input signal. The sample and hold is implemented using TSMC 0.35 μm dual-poly quadruplet metal CMOS technology.     

Progress in high-speed and high-resolution CMOS data converters

This paper presents an overview of the status of high-speed and high-resolution CMOS data converters. Techniques and achieved performance are compared using power consumption per step of resolution as a key parameter. The effort in optimizing this quality factor is evident, because of urgency of portable system requirements. Trends towards low-power design and bit-stream processing are also considered.     

Design techniques for low-voltage high-speed pseudo-differential CMOS track-and-hold circuit with low hold pedestal

A low-voltage pseudo-differential double-sampled track-and-hold circuit with low hold pedestal based on the Miller-effect scheme is proposed. Rail-to-rail operation of bootstrapped switches allows the low-voltage T/H circuit implementation. Simulation results confirm that the proposed circuit is effective in low-voltage applications with low hold pedestal.     

Precise CMOS current sample/hold circuits using differential clockfeedthrough attenuation techniques

New CMOS current sample/hold (CSH) circuits capable of overcoming the accuracy limitations in conventional circuits without significantly reducing operating speed are proposed and analyzed. A novel differential clock feedthrough attenuation (DCFA) technique is developed to attenuate the signal-dependent clock feedthrough errors. Unlike conventional techniques, the DCFA circuit allows the use of dynamic mirror techniques, and results in no additional finite output resistance errors or device mismatch errors. The test chip of the proposed fully differential CSH circuit with multiple outputs has been fabricated in 1.2-μm CMOS technology. Using a single 5-V power supply, experimental results show that the signal-dependent clock feedthrough error current is less than ±0.4 μA for the input currents from -550 μA to 550 μA. The acquisition time for a 900-μA step transition to 0.1% settling accuracy is 150 ns. For a 410-μA_p-p input at 250 MHz with the fabricated fully-differential CSH circuit clocked at 4 MHz, a total harmonic distortion of -60 dB, and a signal-to-noise ratio of 79 dB have been obtained. The active chip area and power consumption of the fabricated CSH circuit are 0.64 mm² and 20 mW, respectively. Both simulation and experimental results have successfully verified the functions and performance of the proposed CSH circuits     

A bridge type optoelectronic sample and hold circuit

A novel bridge-type optoelectronic (OE) sample-and-hold circuit based on current steering is proposed and experimentally tested. Experimental comparison between this circuit and the conventional direct OE sample-and-hold circuit shows that the bridge type is clearly superior in performance to the direct OE circuit. When a high speed signal is sampled with high accuracy, the bridge-type OE sample-and-hold is potentially more advantageous over the conventional electronic sample and hold in terms of large charging current capability, commanding signal isolation, fabrication simplicity, accurate timing control, and less time jitter     

A precision autozeroing sample and hold integrated circuit

A precision sample and hold integrated circuit with autozeroing of all DC errors is described. Experimental data have shown that it provides the accuracy necessary for use in 12 bit data acquisition systems. Application of noise-optimized silicon gate FET devices for the input circuitry of amplifiers which buffer the hold capacitor results in a low droop rate and allows the sample/hold to operate without external components. Common mode rejection is optimized through implementation of a modified current source offering extremely high output impedance at high operating currents. The device includes all digital control and switching circuitry.     

A high-speed high-resolution ultrasonic inspection machine

Ultrasonic inspection of tires has previously been performed using low frequencies in air, which results in low spatial resolution. In addition, the tire has not typically been completely inspected. The limited scanning area and scanning resolution in previous work has been the result of difficulties in acquiring and handling large data sets, difficulties in positioning transducers in a large number of locations over a complex shape, and display or interpretation of the large amount of data which would be generated in such a system. A new design is presented which combines a low-cost multiple processor design to perform motion control, data acquisition, and data transfer. The design is generally useful in a number of different nondestructive evaluation and other large-data-set data acquisition and control applications     

A complete monolithic sample/hold amplifier

A monolithic sample/hold amplifier is described which includes the holding capacitor on the chip. System design considerations and tradeoffs are discussed, as well as the circuit design details. High performance is achieved by the use of a process which produces bipolar transistors and p-channel silicon-gate FET's (SIGFET's) on the same chip. Performance characteristics obtained include an acquisition time of 10 /spl mu/s (20-V step), an aperture delay time of 80 ns, and a droop rate of 30 mV/s.     

A novel low-power,low-offset,and high-speed CMOS dynamic latched comparator

A novel dynamic latched comparator with offset voltage compensation is presented. The proposed comparator uses one phase clock signal for its operation and can drive a larger capacitive load with complementary version of the regenerative output latch stage. As it provides a larger voltage gain up to 22 V/V to the regenerative latch, the input-referred offset voltage of the latch is reduced and metastability is improved. The proposed comparator is designed using 90 nm PTM technology and 1 V power supply voltage. It demonstrates up to 24.6% less offset voltage and 30.0% less sensitivity of delay to decreasing input voltage difference (17 ps/decade) than the conventional double-tail latched comparator at approximately the same area and power consumption. In addition, with a digitally controlled capacitive offset calibration technique, the offset voltage of the proposed comparator is further reduced from 6.03 to 1.10 mV at 1-sigma at the operating clock frequency of 3 GHz, and it consumes 54 μW/GHz after calibration.     

A low-power,fast-settling reference circuit for high-speed high-resolution ADC

A low-power, fast-settling reference buffer used for high-speed high-resolution ADC is proposed. A replica buffer forms a closed loop to stabilise the operating point and a cascaded gm-boosting technique provides sufficient low output impedance, all of which ensure a high performance for the proposed buffer. The measured results show that the proportion of power consumption by the proposed buffer over ADC is only 2.7%, while settling to 12-bit accuracy within 0.13 ns.     

一种运用于高速ADC的采样保持电路设计

设计了一种用于Pipelined ADCs中的前置采样保持电路.从理论上推导了12bit、100MHz的模数转换器对采样保持电路各个子电路的性能指标要求,按此要求设计了增益增强型运放、自举开关等子电路.基于SMIC 0.13μm,3.3V工艺,Spectre仿真结果表明,在采样频率为100MS/s,输入信号频率为9.7656M时实现了81.9dB的信噪失真比(SINAD)和13.3位的有效位数(ENOB),无杂散动态范围(SFDR)可达94.9dB,功耗仅为24mW.输入直到奈奎斯特频率,仍能保持81.5dB的信噪失真比和13.2位的有效位数,SFDR可达到92.67dB.     

一种低失调CMOS比较器设计

本文在研究各种比较器失调消除技术基础上,提出了一种用于ADC电路的高速高精度比较器失调消除技术.该比较器由主动复位和共模箝位的预放大器和输出锁存器构成,通过负反馈自适应调整比较器输入失调电压,降低了开关电容沟道电荷注入和时钟馈通对比较器精度的影响.仿真结果表明,在Chartered 0.35μm COMS工艺下,电源电压3.3V,调整后的比较器失调误差为34μV,比较速率100MHz.     

A high-speed, 240-frames/s, 4.1-Mpixel CMOS sensor

This paper describes a large-format 4-Mpixel (2352/spl times/1728) sensor with on-chip parallel 10-b analog-to-digital converters (ADCs). The chip size is 20/spl times/20 mm with a 7-/spl mu/m pixel pitch. At a 66-MHz master clock rate and 3.3-V operating voltage, it achieves a high frame rate of 240 frames/s delivering 9.75 Gb/s of data with power dissipation of less than 700 mW. The principal architectural features of the sensor are discussed along with the results of sensor characterization.     

A high-resolution and high-speed ferroelectric liquid-crystalshutter array print head

A 1-in-wide, 577-dot/in, and 4:1 multiplex ferroelectric-liquid-crystal (FLC) shutter array has been fabricated and tested for optical performance. The array has a cell gap of 2.8 μm and is surface stabilized with an FLC material of high spontaneous polarization (140 nC/cm²) and fast switching time (16 μs) at room temperature. It is capable of operating at a speed of 6.5 in/s (24 p.p.m. printing speed) with optical contrast ratios of better than 4. Using tungsten-halogen illumination, a prototype print head has been made, and print samples have been obtained on an electrophotographic printer engine     

A novel sample and hold system using an optical modulator

A novel sample and hold (S/H) system that uses an optical intensity modulator as a sampling head is proposed. Experiments as well as the theoretical studies are carried out to evaluate the system performance. At least a 1-GHz bandwidth and up to a 250-Msps operation of the S/H is verified experimentally. The potential of this new system for broadband and high-speed operation is discussed in comparison with conventional diode-bridge-type S/H circuitry     

C/SUP 2/L: A new high-speed high-density bulk CMOS technology

C/SUP 2/L, or closed COS/MOS logic, is a new structural approach to high-speed bulk-silicon COS/MOS logic. C/SUP 2/L is a self-aligned silicon-gate CMOS technology where the gate completely surrounds the drain. The use of such geometry maximises the transconductance to capacitance ratio for devices and thus allows high on-chip speed. The CDP 1802 single-chip 8-bit microprocessor, as well as several memory and I/O circuits announced recently by the RCA Solid State Division, are fabricated in this new technology. Generally, C/SUP 2/L devices show an improvement in packing density by a factor of 3 over standard CMOS and operate at frequencies approximately 4 times faster than standard CMOS. The fabrication sequence for C/SUP 2/L devices requires 6 photomasks (one less than standard CMOS).     

A high-speed CMOS comparator with 8-b resolution

A comparator consisting of a differential input stage, two regenerative flip-flops, and an S-R latch is presented. No offset cancellation is exploited, which reduces the power consumption as well as the die area and increases the comparison speed. An experimental version of the comparator has been integrated in a standard double-poly double-metal 1.5-μm n-well process with a die area of only 140×100 μm². This circuit, operating under a +2.5/-2.5-V power supply, performs comparison to a precision of 8 b with a symmetrical input dynamic range of 2.5 V (therefore ±0.5 LSB resolution is equal to ±4.9 mV)     

A fast sample and hold charge-sensing circuit for photodiode arrays

An on-chip charge-sensing circuit with a feedback loop has been designed for improving the charge-transfer speed in photodiode arrays. Its large output voltage swing combined with improved speed performances, makes this circuit well-suited for OCR applications, especially low-cost data capture devices. Sample and hold operation can easily be performed without increasing the Si real estate, making parallel output feasible with frame rates of 3 kHz for arrays with 500 pixels. Experimental arrays were built in standard p-channel aluminum-gate technology.