Design of a capacitor cross-coupled dual-band LNA with switched current-reuse technique

This paper presents the design of a 2.5/3.5-GHz dual-band low-power and low-noise CMOS amplifier (LNA), which uses the capacitor cross-coupling technique and current-reuse method with four switches. The proposed LNA uses a single RF block and a broadband input stage, which is a key aspect for the easy reconfiguration of a dual-band LNA. Switching at the inter-stage and output allows for the selection of a different standard. The dual-band LNA attenuates the undesired interference of a broadband gain response circuit, which allows the linearity of the amplifier to be improved. The capacitor cross-coupled gm-boosting method improves the NF and reduces the current consumption. The proposed LNA employs a current-reused structure to decrease the total power consumption. The inter-stage and output switched resonators switch the LNA between the 2.5-GHz and 3.5-GHz bands. The proposed dual-band LNA optimises power consumption by the securing gain, noise figure and linearity. The simulated performance reveals gains of 16.7 dB and 19.6 dB, and noise figures of 3.04 dB and 2.63 dB at the two frequency bands, respectively. The linearity parameters of IIP3 are ?5.7 dBm at 2.5 GHz and ?9.7 dBm at 3.5 GHz. The proposed dual-band LNA consumes 5.6 mW from a 1.8 V power supply.     

Highly Rugged 30 GHz GaN Low-Noise Amplifiers

GaN low-noise amplifiers (LNAs) operating at 27-31 GHz are presented in this letter. The monolithically integrated LNAs were fabricated using the process line of the Ferdinand-Braun-Institut. Noise figures of 3.7 to 3.9 dB were measured. The ruggedness of the LNAs was verified by noise measurements after stressing the LNA for up to 2 h with up to 33 dBm of input power. These conditions are among the most severe stress tests reported in literature. To the best of the authors knowledge, this is the first demonstration of a GaN LNA in this frequency region.     

A modified architecture used for input matching in CMOS low-noise amplifiers

An architecture used for input matching in CMOS low-noise amplifiers (LNAs) is investigated in this paper. In the proposed architecture, gate and source inductors, which are essential in the traditional source inductive degeneration CMOS LNAs, are either reduced or removed. The architecture is finally verified by a narrow-band LNA and a wide-band LNA operating at 2.4-2.5 and 5.1-5.9 GHz, respectively. The narrow-band LNA has measured power gain of 24-dB, noise figure (NF) of 2.6-2.8 dB, and power consumption of 15 mW. The wide-band LNA provides 22.6-24.6-dB power gain and 2.85-3.5-dB NF while drawing 6 mA current from a 1.5-V voltage supply. Compared with their traditional counterparts, the proposed LNAs consume less chip area and present better gain performance.     

微波毫米波宽带单片低噪声放大器

推导了反馈电路理论,利用0.25μmGaAs PHEMT工艺,研制了两种并联反馈单片低噪声放大器。第一种放大器的工作频带为6～18GHz,测得增益G≥21dB,带内增益波动ΔG≤±1.0dB,噪声系数NF典型值为2.0dB,输入驻波VSWRin≤1.5,输出驻波VSWRout≤2.0,1分贝压缩点输出功率P1dB≥11dBm。第二种放大器的工作频带为26～40GHz,测得增益G≥17dB,噪声系数NF约为2.0dB,输入、输出驻波VSWR≤2.5,1分贝压缩点输出功率P1dB≥10dBm。两种电路的测试结果验证了设计的正确性。     

Two-port noise figure optimization of source-degenerated cascode CMOS LNAs

This paper presents a noise figure optimization technique for source-degenerated cascode CMOS LNAs with lossy gate inductors. The optimization technique, based on two-port theory, takes into account second order parasitic components. The effect of inductive source degeneration on LNA noise parameters is discussed. Measured noise figures agree well with the simulations confirming the accuracy of the noise model and allowing us to investigate the contributions of various components to the overall noise figure. A 0.18-μm CMOS LNA with an integrated inductor (Q = 7.5) achieves a noise figure of 1.16 dB and a return loss of 20 dB at 1.4 GHz, drawing 39 mA from a 1.8-V voltage supply, having gain (S ₂₁) of 14.5 dB, input P1dB of ?17.5 dBm, and input IP3 of ?13 dBm. LNAs with external inductors having quality factor of Q = 170 and Q = 40 achieve noise figures of 0.65 dB and 0.68 dB and a return loss of 20 dB at 1.4 GHz, drawing 37 mA from a 1.8-V voltage supply, having gain (S ₂₁) of 17 dB, input P1dB of ?22 dBm, and input IP3 of ?14 dBm. The large power consumption of the presented designs was intentionally selected in order to reduce the noise figure, an acceptable trade-off for LNA’s targeted for radio telescope applications, and to assess the impact of the large currents flowing through interconnect metals on the noise figure     

K-band low-noise amplifiers using 0.18 /spl mu/m CMOS technology

Two K-Band low-noise amplifiers (LNAs) are designed and implemented in a standard 0.18 /spl mu/m CMOS technology. The 24 GHz LNA has demonstrated a 12.86 dB gain and a 5.6 dB noise figure (NF) at 23.5 GHz. The 26 GHz LNA achieves an 8.9 dB gain at the peak gain frequency of 25.7 GHz and a 6.93 dB NF at 25 GHz. The input referred third-order intercept point (IIP3) is >+2 dBm for both LNAs with a current consumption of 30 mA from a 1.8 V power supply. To our knowledge, the LNAs show the highest operation frequencies ever reported for LNAs in a standard CMOS process.     

On-chip matched 5.2 and 5.8 GHz differential LNAs fabricated using0.35 μm CMOS technology

The authors have designed experimental 5.2 and 5.8 GHz low-noise amplifiers (LNAs) using 0.35 μm CMOS technology. The ICs feature on-chip matching to 50 Ω, differential operation, and open drain output buffers. A return loss of better than -15 dB was achieved for both amplifiers. LC parallel resonant loads were used to form the gain peak. The LNAs had a measured noise figure of 4 to 5 dB, at VSS=3.3 V     

Development of Integrated Broad-Band CMOS Low-Noise Amplifiers

This paper presents a systematic design methodology for broad-band CMOS low-noise amplifiers (LNAs). The feedback technique is proposed to attain a better design tradeoff between gain and noise. The network synthesis is adopted for the implementation of broad-band matching networks. The sloped interstage matching is used for gain compensation. A fully integrated ultra-wide-band 0.18-mum CMOS LNA is developed following the design methodology. The measured noise figure is lower than 3.8 dB from 3 to 7.5 GHz, resulting in the excellent average noise figure of 3.48 dB. Operated on a 1.8-V supply, the LNA delivers 19.1-dB power gain and dissipates 32 mW of power. The gain-bandwidth product of the UWB LNA reaches 358 GHz, the record number for the 0.18-m CMOS broad-band amplifiers. The total chip size of the CMOS UWB LNA is 1.37 times 1.19 mm².     

A Compact, ESD-Protected, SiGe BiCMOS LNA for Ultra-Wideband Applications

Two 3.65-mW, ESD-protected, BiCMOS ultra-wideband low-noise amplifiers (LNAs) for operation up to 10 GHz are presented. These common-base LNAs achieve significant savings in die area over more widely used cascoded common-emitter LNAs because they do not use an LC input matching network. A design with a shunt peaked load achieves a high S₂₁ (17-19 dB) and low noise figure (NF) (4-5 dB) across the band. A resistively loaded design exhibits a lower S₂₁ (15-16 dB) and higher NF (4.5-6 dB), but also utilizes 20% less silicon area. Both LNAs achieve a 1.5 kV ESD protection level and an acceptable S₁₁ (<-10 dB) across the band. Current source noise reduction is critical in common base topologies. Therefore, detailed noise analyses of MOS- and HBT-based current sources are provided     

Fully integrated concurrent dual-band low noise amplifier with suspended inductors in SiGe 0.35 μm BiCMOS technology

A fully integrated concurrent dual-band low noise amplifier with suspended inductors is reported. Wideband input impedance matching and wideband low noise characteristics are achieved by the proposed capacitive feedback technique simultaneously. Measurement results show input return losses of -12.8 and -11.5 dB, voltage gains of 14.4 and 14.3 dB, and noise figures of 2.5 and 3.0 measured at 2.3 and 4.5 GHz, respectively, with an image rejection ratio of 26.1 dB and power consumption of 11.9 mW.     

Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio

Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic design methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor f_T/f_MAX of 120 GHz/200 GHz. The PA, fabricated for the first time in CMOS at 60 GHz, operates from a 1.5-V supply with 5.2 dB power gain, a 3-dB bandwidth >13 GHz, a P _1dB of +6.4 dBm with 7% PAE and a saturated output power of +9.3 dBm at 60 GHz. The LNA represents the first 90-nm CMOS implementation at 60 GHz and demonstrates improvements in noise, gain and power dissipation compared to earlier 60-GHz LNAs in 160-GHz SiGe HBT and 0.13-mum CMOS technologies. It features 14.6 dB gain, an IIP ₃ of -6.8 dBm, and a noise figure lower than 5.5 dB, while drawing 16 mA from a 1.5-V supply. The use of spiral inductors for on-chip matching results in highly compact layouts, with the total PA and LNA die areas with pads measuring 0.35times0.43 mm² and 0.35times0.40 mm², respectively     

ESD-Protected Wideband CMOS LNAs Using Modified Resistive Feedback Techniques With Chip-on-Board Packaging

A novel modified resistive feedback structure for designing wideband low-noise amplifiers (LNAs) is proposed and demonstrated in this paper. Techniques including feedback through a source follower, an R–C feedback network, a gate peaking inductor inside the feedback loop, and neutralization capacitors are used. Bond-wire inductors and electrostatic devices (ESDs) are co-designed to improve the chip performance. Two LNAs, LNA1 and LNA2, were fabricated using a TSMC digital 90-nm CMOS technology. Both chips were tested on board using chip-on-board packages with ESD diodes added at the inputs and outputs. LNA1 achieves a 3-dB bandwidth of 9 GHz with 10 dB of power gain and a minimum noise figure (NF) of 4.2 dB. LNA2 achieves a 3-dB bandwidth of 3.2 GHz with 15.5 dB of power gain and a minimum NF of 1.76 dB. The two LNAs have third-order intermodulation intercept points of $-$8 and $-$9 dBm. Their power consumptions are 20 and 25 mW with a 1.2-V supply, respectively.      

Erratum to: Using Improved Product-Coded Modulation Codes to Reduce the Peak-to-Average Power Ratio in Single-Carrier Frequency Division Multiple Access Systems

A new ultra-wideband common gate low noise amplifier (LNA) for 3–6 GHz WLAN and WPAN applications is presented in which a current reused noise canceling structure utilized in the first stage not only provides a suitable noise performance, but also enhances the linearity characteristics of the LNA in a power efficient manner needed by WLAN/WPAN applications. The overall structure of the proposed LNA, consisting of three stages, namely input matching common gate stage with noise canceling, gain stage, and buffer one, is designed, laid out, and analyzed in 0.18 µm RF CMOS process. The LNA has a noise figure of 3.5–3.6 dB, a high and flat power gain of 20.27 ± 0.13 dB, and input and output losses of better than ?11 and ?14 dB, respectively, over the entire frequency band of 3–5 GHz, while these parameters are 3.5 dB, 20.75 ± 0.25 dB, ?15 and ?9 dB for the frequency band of 5–6 GHz, respectively. IIP2 and IIP3 of the proposed topology are equal to 25.9 and ?1.85 dBm, respectively, at 4 GHz frequency. The proposed LNA has 15.3 mW power dissipation from a 1.8 V supply.     

High-performance in W-band monolithic pseudomorphic InGaAsHEMT LNA's and design/analysis methodology

High-performance W-band monolithic one- and two-stage low noise amplifiers (LNAs) based on pseudomorphic InGaAs-GaAs HEMT devices have been developed. The one-stage amplifier has a measured noise figure of 5.1 dB with an associated gain of 7 dB from 92 to 95 GHz, and the two-stage amplifier has a measured small signal gain of 13.3 dB at 94 GHz and 17 dB at 89 GHz with a noise figure of 5.5 dB from 91 to 95 GHz. An eight-stage LNA built by cascading four of these monolithic two-stage LNA chips demonstrates 49 dB gain and 6.5 dB noise figure at 94 GHz. A rigorous analysis procedure was incorporated in the design, including accurate active device modeling and full-wave EM analysis of passive structures. The first pass success of these LNA chip designs indicates the importance of a rigorous design/analysis methodology in millimeter-wave monolithic IC development     

1MHz～40GHz超宽带分布式低噪声放大器设计

为满足宽带系统中低噪声放大器(LNA)宽带的要求,采用0.15μm GaAs赝配高电子迁移率晶体管(PHEMT)工艺,设计了两款1 MHz^40 GHz的超宽带LNA,分别采用均匀分布式放大器结构及渐变分布式放大器结构,电路面积分别为1.8 mm×0.85 mm和1.8 mm×0.8 mm。电磁场仿真结果表明,1 MHz^40 GHz频率范围内,均匀分布式LNA增益为15.3 dB,增益平坦度为2 dB,噪声系数小于5.1 dB;渐变分布式LNA增益为14.16 dB,增益平坦度为1.74 dB,噪声系数小于3.9 dB。渐变分布式LNA较均匀分布式LNA,显著地改善了增益平坦度、噪声性能和群延时特性。     

High-gain, V-band, low-noise MMIC amplifiers usingpseudomorphic MODFETs

State-of-the-art, 60-GHz, low-noise MMICs based on pseudomorphic modulation-doped FETs, with 0.25-μm×60-μm gates offset 0.3 μm from the source ohmic, are discussed. Single-state low-noise amplifiers (LNAs) exhibited minimum noise figures of 2.90 dB with 4.1 dB of associated gain at 59.25 GHz. Dual-state MMICs had minimum noise figures of 3.5 dB and 10.8 dB of associated gain at 58.50 GHz. Cascaded four-stage LNAs (two dual-stage MMICs) had minimum noise figures of 3.7 dB and over 20.7 dB of associated gain at 58.0 GHz. Finally, when biased for maximum gain, the four-stage amplifier exhibited over 30.4 dB of gain at 60.0 GHz     

110-120-GHz monolithic low-noise amplifiers

The authors discuss the development of 110-120-GHz monolithic low-noise amplifiers (LNAs) using 0.1-mm pseudomorphic AlGaAs/InGaAs/GaAs low-noise HEMT technology. Two 2-stage LNAs have been designed, fabricated, and tested. The first amplifier demonstrates a gain of 12 dB at 112 to 115 GHz with a noise figure of 6.3 dB when biased for high gain, and a noise figure of 5.5 dB is achieved with an associated gain of 10 dB at 113 GHz when biased for low-noise figure. The other amplifier has a measured small-signal gain of 19.6 dB at 110 GHz with a noise figure of 3.9 dB. A noise figure of 3.4 dB with 15.6-dB associated gain was obtained at 113 GHz. The authors state that the small-signal gain and noise figure performance for the second LNA are the best results ever achieved for a two-stage HEMT amplifier at this frequency band     

A Sub-2 dB NF Dual-Band CMOS LNA for CDMA/WCDMA Applications

This letter presents the design and experimental results of a 1.8/2.14 GHz dual-band CMOS low-noise amplifier (LNA), which is usable for code division multiple access and wideband code division multiple access applications. To achieve the narrow-band gain and impedance matching at both bands, an extra capacitor in parallel with the C_gs of the main transistor and a harmonic tuned load are switched. Except for the output blocking capacitor and series inductor, all components are integrated on a single-chip. The LNA is designed using a 0.13mum- CMOS process and employs a supply voltage of 1.5 V and dissipates a dc power of 7.5 mW. The measured performances are gains of 14.54 dB and 16.6 dB, and noise figures of 1.75 dB and 1.97 dB at the two frequency bands, respectively. The linearity parameters of and P1dB_in are -16dBm and -5.8 dBm at the 1.8 GHz, -14.8 dBm and -5.3 dBm at the 2.14 GHz, respectively.     

A 0.18μm CMOS low noise amplifier using a current reuse technique for 3.1-10.6 GHz UWB receivers

A new,low complexity,ultra-wideband 3.1-10.6 GHz low noise amplifier(LNA),designed in a chartered 0.18μm RFCMOS technology,is presented.The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected.The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure.A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide -3 dB bandwidth of the overall amplifier simultaneously.The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB,and a high reverse isolation of—45 dB,and good input/output return losses are better than -10 dB in the frequency range of 3.1-10.6 GHz.An excellent noise figure(NF) of 2.8-4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V.An input-referred third-order intercept point(IIP3) is -7.1 dBm at 6 GHz.The chip area,including testing pads,is only 0.8×0.9 mm2.     

带有ESD保护,900MHz/2.4 GHz Dual-BandCMOS LNA的设计

设计了一个可以同时工作在900 MHz和2.4 GHz的双频带(Dual-Band)低噪声放大器(LNA).相对于使用并行(parallel)结构LNA的双频带解决方案,同时工作(concurrent)结构的双频带LNA更能节省面积和减少功耗.此LNA在900MHz和2.4 GHz两频带同时提供窄带增益和良好匹配.该双频带LNA使用TSMC 0.25 μm 1P5M RF CMOS工艺.工作在900MHz时,电压增益、噪声系数(Noise Figure)分别是21 dB、2.9 dB;工作在2.4 GHz时,电压增益、噪声系数分别是25dB、2.8 dB,在电源电压为2.5 V时,该LNA的功耗为12.5mW,面积为1.1mm×0.9 mm.使用新颖的静电防护(ESD)结构使得在外围PAD上的保护二极管面积仅为8 μm×8 μm时,静电防护能力可达2 kV(人体模型)