有助于ADC测量其自身供电电压的重组基准

如果您用ADC来监视系统的电源电压．则您可能会遇到电源电压超过ADC基准电压的情况（图1）。但ADC输入电压不会超过其基准电压．因此您可以用一个外部电阻分压器来将电源电压变换到ADC输入范围内。但即使容差为0．1％的电阻器．也可能会引起令人讨厌的误差。您可以通过取消电阻分压器、将ADC基准输入连接至其电源上、     

A high precision programmable bandgap voltage reference design for high resolution ADC

temperature coefficient is close to 0.69 ppm/℃ over the whole temperature range.     

用于高分辨率ADC的高精度可编程带隙电压参考设计

A programmable high precision bandgap reference is presented, which can meet the accuracy requirements for all technology corners while a traditional bandgap reference cannot.This design uses SMIC 0.18 μm 1P4M CMOS technology.The theoretically achievable temperature coefficient is close to 0.69 ppm/°C over the whole temperature range.     

A CMOS threshold voltage reference source for very-low-voltage applications

This paper describes a CMOS voltage reference that makes use of weak inversion CMOS transistors and linear resistors, without the need for bipolar transistors. Its operation is analogous to the bandgap reference voltage, but the reference voltage is based on the threshold voltage of an nMOS transistor. The circuit implemented using 0.35 μm n-well CMOS TSMC process generates a reference of 741 mV under just 390 nW for a power supply of only 950 mV. The circuit presented a variation of 39 ppm/°C (after individual resistor trimming) for the −20 to +80 °C temperature range, and produced a line regulation of 25 mV/V for a power supply of up to 3 V.     

A programmable voltage reference optimized for power management applications

A 3-bits programmable, low drift, high PSRR and high precision voltage reference, optimized for Power Management (PM) applications, is presented. The topology is based on a high-performance bandgap voltage reference that presents a PSRR of up to 80 dB, which is required in PM applications, because they employ mixed-signal circuits, where high frequency switching noise is present. The proposed approach was successfully verified in a standard 0.35 μm CMOS process. The experimental results confirmed that, for power supply between 3.0 and 3.3 V, and temperatures in ?20°C to 80°C range, the programmable output voltage V _REF exhibits a worst case precision of ±3%.     

A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer

A 12-bit 30 MSPS pipeline analog-to-digital converter(ADC) implemented in 0.13-μm 1P8M CMOS technology is presented.Low power design with the front-end sample-and-hold amplifier removed is proposed.Except for the first stage,two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption.The ADC presents 65.3 dB SNR,75.8 dB SFDR and 64.6 dB SNDR at 5 MHz analog input with 30.7 MHz sampling rate.The chip dissipates 33.6 mW from 1.2 V power supply.FOM is 0.79 pJ/conv step.     

一个低功耗的带片上参考电压缓冲器的12位30兆采样率的CMOS流水线模数转换器

介绍了一个在0.13µm 1P8M CMOS工艺下实现的12位30兆采样率流水线模数转换器。提出了一种消除前端采样保持电路的低功耗设计方法。除了第一级之外,带双输入的两级cascode补偿的运算放大器在相邻级间共享以进一步地减小功耗。该模数转换器在5MHz的模拟输入和30.7MHz的采样速率下达到了65.3dB的SNR,75.8dB的SFDR和64.6dB的SNDR。该芯片在1.2V电源电压下消耗33.6mW。FOM达到了0.79pJ/conv step。     

应用于碲锌镉探测器逐次逼近模数转换器基准电压的研究

An on-chip reference voltage has been designed in capacitor-resister hybrid SAR ADC for CZT detector with the TSMC 0.35 μ m 2P4M CMOS process. The voltage reference has a dynamic load since using variable capacitors and resistances, which need a large driving ability to deal with the current related to the time and sampling rate. Most of the previous articles about the reference for ADC present only the bandgap part for a low temperature coefficient and high PSRR. However, it is not enough and overall, it needs to consider the output driving ability. The proposed voltage reference is realized by the band-gap reference, voltage generator and output buffer. Apart from a low temperature coefficient and high PSRR, it has the features of a large driving ability and low power consumption. What is more, for CZT detectors application in space, a radiation-hardened design has been considered. The measurement results show that the output reference voltage of the buffer is 4.096 V. When the temperature varied from 0 to 80℃, the temperature coefficient is 12.2 ppm/℃. The PSRR was-70 dB@100 kHz. The drive current of the reference can reach up to 10 mA. The area of the voltage reference in the SAR ADC chip is only 449×614 μm². The total power consumption is only 1.092 mW.     

Continuously operating reference station and surveying applications in KSA

Recently, there is an increased interest in surveying applications based on Continuously Operating Reference Station (CORS) technology in the Kingdom of Saudi Arabia (KSA). Jeddah Municipality has started operating the first CORS network in KSA since 2007. This work discusses the new technologies used in Jeddah CORS network, the obtained accuracy and addresses, the different applications covered by CORS network such as cadastral surveying, road surveying, Lidar, among others. Moreover, the work presents the determination of the different transformation parameters between ITRF/WGS84 coordinate system and the local coordinate systems used in KSA. The purpose is to improve the communication abilities in order to operate modern smart cities. With full coverage and high accuracy of locations, Geographic Information System (GIS) and 3D models will be created to operate all aspects of life starting from the inside (the houses) and ending with saving the environment and the energy. Copyright © 2015 John Wiley & Sons, Ltd.     

A power-efficient reference buffer with wide swing for switched-capacitor ADC

A level-shifter-aided CMOS reference voltage buffer with wide swing for high-speed high-resolution switched-capacitor ADC is proposed. It adopts a level shifter for wide swing and a NMOS-only branch circuit for low power. High PSRR (power supply rejection ratio) is guaranteed by the proposed architecture. The proposed reference buffer is integrated in a 14-bit 150 MSps low-power pipelined ADC with the amplification phase of only 2.5 ns. With the input of 2.4 MHz and 2 Vp-p, the measurement of the fabricated ADC shows that the SNDR is 71.3 dB and the SFDR is 93.6 dBc. And the power consumption of the reference buffer is 17 mW from a 1.3 V power supply.     

Low power time-domain rail-to-rail comparator with a new delay element for ADC applications

In this paper, a rail-to-rail time-domain comparator with low power supply voltage and low power consumption is introduced. The comparator can be employed in low-power converters and biomedical applications. In the proposed time-domain comparator, a rail-to-rail delay element has been employed to generate a significant voltage-to-time gain for the full range of input signals. This circuit is designed, laid out, and simulated in 0.18 μm TSMC technology and powered by 0.6 V and 1 V supply voltages. The simulation results show that the proposed comparator has a rail-to-rail dynamic range and the power consumption of the circuit is 0.6 μW and 19 μW at the clock frequency of 10 MHz and 100 MHz, respectively. The active area of 56 μm × 14 μm shows the compactness of the circuit comparing to the other similar works. The proposed comparator was used in an ADC to show its effectiveness to improve the performance of the ADC. An 8-bit 0.8 V 100 kS/s SAR-ADC is designed and simulated. It consumes 430 nW and the figure of merit is 19.3fJ/conversion-step.     

Design of a fA wide dynamic range ADC for current sensing

In this paper, optimal dynamic range scaling of ΔΣ ADC using bias current estimation method is proposed. Generally, a different dynamic range scaling gives different feedback factor and effective load capacitance to each integrator in the ΔΣ ADC. It means that power consumption of each integrator strongly depends on the coefficient of the integrator. Therefore, the proposed method estimates which dynamic range scaling consumes the least power to achieve a given settling error. To verify the effectiveness of the proposed method, the noise coupled third order ΔΣ ADC having different dynamic scaling with transistor level opamps was simulated to compare the ADC performance.     

Energy-efficient switching scheme for SAR ADC with only two reference voltages

An energy-efficient switching method for successive approximation register analog to digital converter is presented in this letter.The proposed two-step switching scheme using the goblet architecture achieves 99.52% less switching energy and 21.09% area reduction over the conventional switching scheme. Moreover, owing to the application of the goblet architecture, the proposed scheme employs only two reference voltages without any requirements for stability or accuracy of the third voltage level.     

Polycarbonate films metalized with a single component molecular conductor suited to strain and stress sensing applications

The paper reports all-organic strain and stress sensitive films that use electrical monitoring approach. The films were prepared by self-metallizing polycarbonate films with the single component molecular conductor [Au(α-tpdt)₂]⁰ (tpdt = 2,3-thiophenedithiolate). It was shown that [Au(α-tpdt)₂]⁰ by its nature is able to form metallic solid material with low crystallinity. Electromechanical tests demonstrated that the developed films are strain-resistive materials with advanced elastic properties: their electrical resistance varies linearly with uniaxial elongation up to relative strain being of 1.0% that is about five times larger than that for conventional metals. The gauge factor of the films is 4.4 and stress sensitivity is 30 Ω/bar. The processing characteristics of polycarbonate films, self-metalized with a metallic [Au(α-tpdt)₂]⁰-based layer, make them potentially useful for engineering flexible, lightweight, strain and pressure sensors. Due to electromechanical characteristics these films are suited to strain sensing applications requiring miniature strain control in a wide deformation range.     

A new transponder architecture with on-chip ADC for long-range telemetry applications

We present a new architecture for wireless power and data telemetry that recovers power and a system clock from a weak incident RF signal. A high-efficiency RF-DC converter generates a 3-VDC supply for the system from a -12.3-dBm incident RF signal, gathered by a commercial 50-/spl Omega/ antenna. A system clock is extracted from the same incident signal, by an injection-locked LC oscillator. Sub-harmonic injection-locking facilitates the separation of the incident and the transmit signal frequencies, without need for a PLL. The proposed architecture is used in a long-range telemetry device, incorporating an on-chip ADC, and employing active telemetry for data transmission. Data is transmitted through binary phase-shift-keying of a 900-MHz carrier. The prototype, implemented in 0.25-/spl mu/m CMOS, occupies less than 1 mm/sup 2/. A wireless operation range of more than 18 meters is indicated by anechoic chamber testing.     

一种分段曲率补偿带隙基准源设计

在传统带隙基准的基础上,设计了一种分段曲率补偿的低温漂带隙基准。利用NMOS管工作在亚阈值区域时漏电流和栅极电压的指数特性,在低温和高温段同时对基准电压进行曲率补偿,采用UMC 0.25μm BCD工艺进行仿真。仿真结果表明,电源电压5 V时,静态功耗电流为7.11μA;电源电压2.5~5.5 V,基准电压变化148μV;温度在–40~+145℃内,电路的温度系数为1.18×10–6/℃;低频时电源抑制比为–87 d B。     

Design of an ADC for subsampling video applications

This paper describes a 10 bit 30 Msample/s (MSPS) CMOS analog-to-digital converter (ADC) for high-speed signal processing, especially for subsampling applications, for example digital video broadcasting over cable (DVB-C), terrestrial (DVB-T) and handheld (DVB-H) systems. The proposed pipelined ADC shows a good figure-of-merit (FoM). It adopts a power efficient amplifier sharing technique, a symmetrical gate-bootstrapping technique with modified timing for the bottom-sampling switch of a wideband sample-and-hold (S/H) circuit, a proposed stable high-swing bias circuit for a wide-swing gain-boosting telescopic amplifier. The measured differential and integral nonlinearities of the prototype in a 0.25-μm CMOS technology show less than 0.4 least significant bit (LSB) and 0.85 LSB respectively at full sampling rate. The ADC exhibits higher than 9 effective number of bits (ENOB) for input frequencies up to about 60 MHz, which is the fourfold Nyquist rate (fs/2), at 30 MSPS. The ADC consumes 60 mW from a 3-V supply and occupies about 1.36 mm². Jian Li received the Bachelor of Engineering (B.E.) degree in electronic engineering from Xi’an Jiaotong University, Xi’an, China, in 2003. He is currently working toward the Ph.D. degree at Microelectronics department, Fudan University, Shanghai, China. His current research interest is high-speed high resolution A/D converter design. Xiaoyang Zeng was born in Hunan Province, P.R. China on April 17, 1972. He received the B.S. degree from Xiangtan University, China in 1992, and the Ph.D. degree from Changchun Institute of Optics and Fine Mechanics, Chinese Academy of Sciences in 2001. From 2001 to 2003, he worked as a post-doctor researcher at the State-Key Lab of ASIC & System, Fudan University, P.R. China. Then he joined the faculty of Department of Micro-electronics at Fudan University as an associate professor. His research interests include information security chip design, VLSI signal processing, and communication systems. Prof. Zeng is the Chair of Design-Contest of ASP-DAC 2004 and 2005, also the TPC member of several international conferences such as ASCON 2005 and A-SSCC 2006, etc. Jianyun Zhang received the B.S., M.S. and Ph.D degree in electrical engineering from Fudan University, Shanghai, China in 1997, 2000 and 2006 respectively. From 2000 to 2002, he was with Alcatel microelectronics, Belgium, where he was involved in circuit design for GSM and GPRS. In 2002, he joined Trident microsystem, where he concentrated on the design of Video AFE including data converters and mixed signal circuits. In 2005, he joined Shihong microelectronics Corp., where he is now a director of mixed signal IC for video high speed interface. His research interests include data conversion, HDMI SerDes, and analog circuit design. Lei Xie received the Bachelor of Science (B.S.) degree in microelectronics from Nankai University, Tianjin, China, in 2005. He is currently working toward the M.S. degree at Fudan University, Shanghai, China. His current research interest is high-speed high resolution A/D converter. Huan Deng received the B.S. degree in microelectronics from Fudan University, Shanghai, P.R. China, in 2003. He is currently working toward the M.S. degree in microelectronics at the State Key Lab of ASIC & System, Fudan University. He is currently involved in the design of low-power, high-speed PLL’s. Yawei Guo received the B.S. and M.S. degree in electrical engineering from Fudan University in 1999 and 2002 respectively. From 2002 to August 2003, he was with Philips Semiconductors in Shanghai. Since August 2003, he has been with Shanghai MicroScience Integrated Circuits Co., Ltd., based in Shanghai, P. R. China. He has been leading a group and developing analog and mixed signal circuits. His research interests include high-speed data communication, data converters, and phase locked loops.     

A capacitance-coupling memory cell operating with a single powersupply

A capacitance-coupling (CC) memory cell structure is proposed that operates with a single power supply and provides larger storage capacitance than the conventional CC cell. This structure uses triple polysilicon technology and a self-aligned positioning technique. To obtain single-power-supply operation, two word lines are used for reading and writing. The p-channel MOSFET and the junction FET, which are included in the memory cell and are merged in one device area, are extensively studied to estimate the capability of the cell. Experimental memory cells with 1-μm design rule were fabricated that showed complete memory operation and sufficient 0/1 readout-current ratio, and also confirmed the estimated capability results     

10 K NbN ADC for IR sensor applications

The authors report the design, fabrication and test results of a 12-bit NbN SFQ counting A/D converter operating at 9 to 10 K and its insertion into a test IR focal plane array sensor system. The NbN IC is based on a linearized SQUID front-end which generates SFQ pulses at a frequency proportional to the signal. A gated SFQ counter integrates the signal over the sample time and the data is driven off chip through a serializing latching voltage state logic (MVTL) output shift register. The TRW A/D converter chip has been packaged and inserted into an IR focal plane array sensor test facility, or test bed, at the NASA Jet Propulsion Laboratory. The entire system has been successfully demonstrated producing IR images at 100 frames/s with the NbN A/D converter operating at 9 K, dissipating 0.3 mW. Performance of the A/D converter chip, the package including magnetic shielding and medium/high speed signal I/O, and the integrated test bed system are discussed.