基于可重构S盒的常用分组密码算法的高速实现

DES、3DES和AES是应用最广泛的分组密码算法，其可重构性和高速实现对可重构密码芯片的设计具有重要影响。该文分析了这3种算法的高速硬件实现，利用流水线、并行处理和重构的相关技术，提出了一种可重构S盒（RC-S）的结构，并在此基础上高速实现了DES、3DES和AES。基于RC-S实现的DES、3DES和AES吞吐率分别可达到7Gbps、2．3Gbps和1．4Gbps，工作时钟为110MHz。与其它同类设计相比，该文的设计在处理速度上有明显优势。     

远程控制系统的自重构探讨

本文研究在远程控制环境下,利用自重构机器人的可重构控制系统的自重构设计。笔者分别从远程控制系统的自重构结构、可重构系统设计思路、可重构控制律、可重构控制系统的软硬件设计等方面探讨自重构设计。     

嵌入式单片自重构平台体系结构的实现

讨论了在Xilinx开发平台上利用FPGA动态重构技术实现自重构系统的方法以及流程。系统中包含静态和动态两种模块,采用Xilinx的基于模块的动态重构设计方法实现。静态模块和动态模块通过一个称为总线宏的结构通信,由嵌入式硬核处理器PPC405控制Xilinx的内部访问接口(ICAP)完成重构。实验表明采用自重构技术可以在单片FPGA上实现复杂的可重构系统。     

基于FPGA的可重构计算技术研究

本文介绍了可重构计算技术的提出和历程,结合器件发展、重构方式和结构模式分析了基于FPGA的可重构计算技术原理,从设计、配置角度探讨了实现技术,并阐述了在多个领域的应用。根据存在的问题,提出了可重构计算技术的发展研究方向。     

基于软件芯片的可重构远程故障诊断系统*

提出了一种具有充分柔性与可重构性的远程故障诊断系统的结构模型,利用软件芯片技术对系统中的各功能模块进行封装,并描述了系统的运行原理。根据应用设备的不同要求,通过系统数据组织、诊断芯片适配和运行结构设计,可以快速重构出不同的诊断系统。     

网络系统可重构性分析模型研究

当前信息网络正面临各种挑战,具有动态适应能力的可重构网络系统正成为人们关注的焦点.首先提出网络系统可重构性的概念,揭示了其鲁棒性、演化性和生存性的基本属性.通过建立系统状态的分层模型,在对系统鲁棒行为、演化行为和生存行为进行刻画的基础上,提出一种基于FSM的网络系统可重构性分析模型.为实现网络可重构性的量化分析,以网络拓扑可重构性度量为例进行研究,提出了量化的可重构性度量指标.可重构性的量化指标使得可重构性分析模型具有了量化分析的应用前景.     

基于函数级原型的流水线可重构结构的研究

针对目前动态可重构技术中重构时隙的问题,本文利用流水线技术和可熏构技术,提出并讨论一种流水线可重构体系结构的函数级原型设计方法,并采用AES算法对其进行了仿真验证.结果表明,流水线可熏构结构的函数级原型设计方法可有效的解决动态重构系统中的重构时隙问题.     

基于AES和DES算法的可重构S盒硬件实现

密码芯片的可重构性不仅可以提高安全性，而且可以提高芯片适应性．S盒是很多密码算法中的重要部件，其可重构性对密码芯片的可重构性有重大影响．文章在分析AES和DES算法中S盒硬件实现方法的基础上，利用硬件复用和重构的概念和相关技术，提出了一种可重构S盒（RC-S）结构及其实现方法．实验结果表明RC-S可用于AES算法和DES的硬件实现．基于RC-S的AES、DES密码模块规模分别是AES、DES模块的0．81／1．13，性能分别是DES／AES的0．79／0．94．     

自重构模块机器人研究

介绍国外自重构模块机器人的研究现状。分析多种典型自重构模块机器人系统的模块构成、连接机制和自重构规划方法。指出自重构模块机器人研究的关健技术和需解决的现实问题。     

动态可重构系统的通信结构研究

动态可重构技术能在一定控制逻辑的驱动下,对全部或部分逻辑资源实现在系统的动态功能变换和硬件的时分复用.本文介绍了可重构体系结构及典型动态可重构结构;详细分析、比较了动态可重构系统4种通信结构的主要性能,指出各自适用领域,并给出一个应用实例;最后探讨了动态可重构技术研究面临的相关问题和发展趋势.     

Experimenting with dynamic linking with ADA

An approach to achieving dynamic reconfiguration within the framework of Ada¹ is described. A technique for introducing a kernel facility for dynamic reconfiguration in Ada is illustrated, and its implementation using the Verdix VADS 5.5 Ada compiling system on a Sun3–120 running the 4.3 BSD Unix operating system is discussed. This experimental kernel allows an Ada program to change its own configuration dynamically, linking new pieces of code at run-time. It is shown how this dynamic facility can be integrated consistently at the Ada language level, without introducing severe inconsistencies with respect to the Standard semantics.     

Synchronization-oriented reconfiguration of FPAI under graduation intelligent manufacturing system in the COVID-19 pandemic and beyond

Companies with manufacturing systems that are more responsive and resilient will be able to survive or even gain market shares in the face of the unpredicted variable of an outbreak similar to the COVID-19 pandemic. Motivated by an industrial company restructuring its manufacturing system with the layout of fixed-position assembly islands (FPAI) during the COVID-19 pandemic, this paper introduces the synchronization-oriented reconfiguration of FPAI under Graduation Intelligent Manufacturing System (GiMS). Inspired by the graduation ceremony, a novel manufacturing mode-Graduation Manufacturing System (GMS) with ticket-based reconfigurable structures, is designed for organizing production operations with simplicity and resilience for the layout of FPAI. The IIoT and digital twin-enabled GiMS is developed for transforming real-time visibility in operations to support the reconfiguration of the manufacturing system. A synchronization-oriented reconfiguration mechanism is proposed to achieve the synchronous interaction among changing customer demand, island configuration, and production activities allocation rapidly and cost-effectively. Cloud services integrating the proposed reconfiguration mechanism are developed for managers and onsite operators for supporting the successful reconfiguration implementation with enhanced operational visibility. Through the case study of an industrial company, the effectiveness of the proposed concept and approach is verified.     

可重构密码处理结构中重构机制及对性能的影响

重构机制对可重构密码处理系统的性能有着重要的影响,该文从全局、局部、静态、动态几方面提出了流水化可重构密码处理结构中重构机制的分类,给出了各种机制的吞吐率和延迟公式,并分析了几种机制的性能和实现代价,最后给出了在采用局部动态重构机制的可重构密码处理结构中密码处理的性能。     

基于组件的分布式软件的动态配置和容错

论文提出一种结构化新方法,它能通过动态配置支持基于组件的分布式软件的容错。采用面向图形的编程模型,基于组件的分布式软件的软件体系结构可用一个逻辑图来表示,该逻辑图可以精化为一个明确的对象并分布到网络中,软件的动态配置通过执行定义在图上的一系列操作来实现,发生错误时通过动态重配置软件来支持容错。论文描述了该方法的基本模型、系统结构及其在CORBA上的实现原型。     

基于DSP总线的振动传感器信号采集系统设计

以TMS320F2808控制的CAN模块为核心,设计了CAN总线节点模块,以实现对ICP振动传感器的振动信号进行实时检测和处理[1]。通过描述系统的硬件设计原理和软件框架流程,介绍系统的设计和实现方法。该系统能够满足传感器系统对实时性的要求,方便、易携,并且具有可重构性,能够实现不同的算法。     

学习增强型PID控制系统的收敛性分析

针对具有可重复性的一般离散时间非线性系统, 在已存在的PID控制系统的基础上, 利用重复性的特点, 给出了一种学习增强型PID控制方法, 严格证明了收敛性, 并通过快速路交通系统的仿真验证了该方法的有效性和优越性. 该种方法的主要特点是, 不需要对已有的PID控制装置和系统做任何改动, 只需在PID控制器的外环加上迭代学习控制器即可, 是一种模块化的设计. 该方法实现了PID与迭代学习控制的优势互补.     

Reconfiguration and analysis of a fault-tolerant circular butterflyparallel system

The butterfly parallel system has a regular and simple interconnection pattern, making it suitable for VLSI or WSI implementation. The authors propose an effective fault-tolerant technique for the circular butterfly parallel system to ensure its rigid full butterfly structure even in the presence of failures, addressing reconfiguration in detail. The resulting butterfly system has L levels, involves (1/log₂ L)% spare processing elements (PEs), and approximately 50% additional links. The reconfiguration process of the design in response to any operational fault is easy and can be performed in a distributed manner. The reliability and layout of this proposed design are evaluated analytically. This design, due to its specific configuration, exhibits significant improvement in reliability while taking only moderately more layout area     

A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations

Signal processors exploiting ASIC acceleration suffer from sky-rocketing manufacturing costs and long design cycles. FPGA-based systems provide a programmable alternative for exploiting computation parallelism, but the flexibility they provide is not as high as in processor-oriented architectures: HDL or C-to-HDL flows still require specific expertise and a hardware knowledge background. On the other hand, the large size of the configuration bitstream and the inherent complexity of FPGA devices make their dynamic reconfiguration not a very viable approach. Coarse-grained reconfigurable architectures (CGRAs) are an appealing solution but they pose implementation problems and tend to be application specific. This paper presents a scalable CGRA which eases the implementation of algorithms on field programmable gate array (FPGA) platforms. This design option is based on two levels of programmability: it takes advantage of performance and reliability provided by state-of-the-art FPGA technology, and at the same time it provides the user with flexibility, performance and ease of reconfiguration typical of standard CGRAs. The basic cell template provides advanced features such as sub-word SIMD integer and floating-point computation capabilities, as well as saturating arithmetic. Multiple reconfiguration contexts and partial run-time reconfiguration capabilities are provided, tackling this way the problem of high reconfiguration overhead typical of FPGAs. Selected instances of the proposed architecture have been implemented on an Altera Stratix II EP2S180 FPGA. On this system, we mapped some common DSP, image processing, 3D graphics and audio compression algorithms in order to validate our approach and to demonstrate its effectiveness by benchmarking the benefits achieved.     

面向RSoC的过程级动态软硬件划分

软硬件划分作为可重构片上系统设计的重要技术手段,其结果直接影响到系统的性能。目前的软硬件划分大多只考虑从算法本身提高划分效果,忽略了划分结果的具体配置实现,导致划分效果很不理想。分析了预配置模型下的任务描述,给出了预配置调度优先级的计算方法,设计了一种预配置调度策略;针对软硬件划分与动态可重构的特点,提出并实现了一种结合预配置的软硬件划分算法,给出了一种评价软硬件划分方案优劣的方法。实验结果表明,该划分方法具有良好的划分效果。