Hydrogen passivation of PolySilicon MOSFET's from a plasma Nitride source

Improvements in polysilicon grain-boundary passivation techniques have made polysilicon MOSFET's increasingly attractive, as vertically stackable circuit components in applications, where high mobility is not a primary requirement. A simple method for the "last step" passivation of grain boundaries in polysilicon MOSFET's is presented. The method involves diffusion of atomic hydrogen at 450°C from a plasma-deposited compressive silicon nitride layer for reaction at silicon grain-boundary dangling bond sites. By use of this technique, ON/OFF current ratios of greater than 10⁶can be achieved with drive currents that are sufficient for many circuit applications.     

Novel self-aligned polysilicon-gate MOSFETs with polysilicon source and drain

A novel self-aligned technique is described for self-aligning a polysilicon gate in devices with polysilicon source and drain regions. The technique is demonstrated for two types of polysilicon source and drain devices. In one type of device, the polysilicon serves as the source of dopant for diffused source and drain junctions. In the second type, the polysilicon, together with an underlying interfacial oxide, forms a tunneling CIS (conductor-thin insulator-semiconductor) structure. The characteristics of devices of both types fabricated under almost identical conditions using the new self-alignment technique are compared.     

A self-aligned elevated source/drain MOSFET

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior     

A novel thin-film transistor with self-aligned field induced drain

In this letter, a novel thin-film transistor with a self-aligned field-induced-drain (SAFID) structure is reported for the first time. The new SAFID TFT features a self-aligned sidewall spacer located on top of the drain offset region to set its effective length, and a bottom gate (or field plate) situated under the drain offset region to electrically induce the field-induced-drain (FID). So, unlike the conventional off-set-gated TFTs with their effective FID length set by two separate photolithographic masking layers, the new SAFID is totally immune to photomasking misalignment errors, while enjoying the low off-state leakage as well as high turn-on characteristics inherent in the FID structure. Polycrystalline silicon TFTs with the new SAFID structure have been successfully fabricated with significant improvement in the on/off current ratio     

A new MOSFET structure with self-aligned polysilicon source and drain electrodes

A new MOSFET structure whose source and drain electrodes are self-aligned to the gate electrode is proposed. The new structure utilizes a second layer of polysilicon which is defined by a preferrential etching to form the source and drain regions. Due to the self-alignment property of the source and drain regions, the total device size is decreased by about 50 percent over the conventional MOS transistors when the same design rule is used. Experimental results of the new structure are presented.     

A vertical FET with self-aligned ion-implanted source and gate regions

A new self-aligned vertical channel JFET has been fabricated using ion-implantation and LOCOS techniques. This device required four photolithography processes. Fine patterning and accurate mask alignment are not required by this process. The electrical properties of this device are a voltage amplification factor of more than 5, a source-to-gate breakdown voltage of 50 V, and a drain-to-gate breakdown voltage of 140 V. It is possible to realize a larger voltage amplification factor, compared to the diffused vertical FET.     

Junction capacitance reduction due to self-aligned pocketimplantation in elevated source/drain NMOSFETs

A new advantage of an elevated source/drain (S/D) configuration to improve MOSFET characteristics is presented. By adopting pocket implantation into an elevated S/D structure which was formed by Si selective epitaxial growth and gate sidewall removal, we demonstrate that the parasitic junction capacitance as well as the junction leakage was significantly reduced for an NMOSFET while maintaining its good short channel characteristics. These successful results are attributed to the modification of the boron impurity profile in the deep S/D regions. The capacitance reduction rate, furthermore, was more remarkable as the pocket dose was further increased. This means that the present self-aligned pocket implantation is very promising for future MOSFETs with a very short gate length, where high pocket dosage will be required to suppress the short channel effect     

增强型自对准源漏区AlN/GaN/AlN 氮极化金属绝缘半导体场效应晶体管的静态特性与短沟道效应的研究

This paper aims to simulate the I–V static characteristic of the enhancement-mode(E-mode) Npolar Ga N metal–insulator–semiconductor field effect transistor(MISFET) with self-aligned source/drain regions.Firstly, with SILVACO TCAD device simulation, the drain–source current as a function of the gate–source voltage is calculated and the dependence of the drain–source current on the drain–source voltage in the case of different gate–source voltages for the device with a 0.62 m gate length is investigated. Secondly, a comparison is made with the experimental report. Lastly, the transfer characteristic with different gate lengths and different buffer layers has been performed. The results show that the simulation is in accord with the experiment at the gate length of 0.62 m and the short channel effect becomes pronounced as gate length decreases. The E-mode will not be held below a100 nm gate length unless both transversal scaling and vertical scaling are being carried out simultaneously.     

Direct-coupled GaAs ring oscillators with self-aligned gates

The performance of direct-coupled GaAs MESFET ring oscillators having a 1µm self-aligned recessed-gate structure defined by optical contact lithography on CVD epitaxial material is reported. Propagation delays as low as 20.9 and 16.1 ps/stage have been achieved at 300 and 77 K, respectively, representing the fastest results reported to date for GaAs ring oscillators having conventional 1-µm gate technology.     

Polysilicon thin-film transistors using self-aligned cobalt andnickel silicide source and drain contacts

Polysilicon thin-film transistors (TFTs) with island thickness of 20 and 70 nm were fabricated with self-aligned cobalt and nickel silicide contacts to the source and drain. The silicide contacts are shown to reduce the series resistance, which limits the on-current of the device, thus significantly increasing the effective mobility in the 20-nm island devices. The mobilities of 20-nm cobalt and nickel silicided devices are similar to those with 70-nm islands, 31 versus 33 cm²/V-s, whereas the nonsilicided 20-nm devices have a mobility of only 13 cm²/V-s. The island thickness is shown to influence other device parameters affecting active matrix display driver circuit design, such as threshold voltage, leakage current, and subthreshold swing; all these parameters are improved when the island thickness is decreased     

Effects of interfacial Oxide layer on short-channel polycrystalline source and drain MOSFET's

Using a novel self-alignment approach, the characteristics of polycrystalline source and drain MOSFET's with and without a deliberately grown oxide under the polycrystalline regions are compared. The interfacial oxide is shown to suppress short-channel effects in the shortest channel devices studied, but this improvement is at the expense of increased source-to-drain contact resistance in the present devices. The devices without the interfacial oxide are also expected to have superior hot-carrier performance.     

Novel fully self-aligned MESFET using source and drain regrown nonalloyed contacts by ALE

A new low temperature, nonalloyed, self-aligned FET process using regrowth technology on a patterned substrate has been demonstrated. A double 8-doped MESFET with regrown n⁺⁺ source and drain contact regions using atomic layer epitaxy (ALE) were fabricated and characterized. In this novel regrowth technique, a silicide gate was embedded by molybdenum and a side wall oxide to prevent any contamination or unwanted reaction during the ALE growth. Two main features associated with our process that makes it an attractive technology for more uniform device performance across a large area wafer are: a) the refractory gate/GaAs interface is not subjected to any high temperature process, and b) nonalloyed ohmic contacts are achieved without undesirable lateral diffusion of n⁺ regions caused by annealing of implanted source and drain. The preliminary unoptimized device results show a transconductance of 40 mS/mm for gate length of 0.65 μn.     

Implementation and characterization of self-aligned double-gate TFTwith thin channel and thick source/drain

In this paper, a self-aligned double-gate (SADG) TFT technology is proposed and experimentally demonstrated for the first time. The self-alignment between the top-gate and bottom-gate is achieved by a noncritical chemical-mechanical polishing (CMP) step. A thin channel and a thick source/drain region self-aligned to the two gates are realized in the proposed process. Simulation results indicate that the self-aligned thick source/drain region leads to a significant reduction in the lateral electric field arisen from the applied drain voltage. N-channel poly-Si TFTs are fabricated with a maximum processing temperature of 600°C. Metal-induced unilateral crystallization (MIUC) is used to enhance the grain size of the poly-Si film. The fabricated SADG TFT exhibits symmetrical bi-directional transfer characteristics when the polarity of source/drain is reversed. The on-current under double-gate operation is more than two times the sum of that under individual top-gate and bottom-gate control. High immunity to short channel effects and kink-free current-voltage (I-V) characteristics are also observed in the SADG TFTs     

High-performance p-channel Schottky-barrier SOI FinFET featuring self-aligned PtSi source/drain and electrical junctions

A simplified and improved Schottky-barrier metal-oxide-semiconductor device featuring a self-aligned offset channel length, PtSi Schottky junction, and reduced oxide thickness underneath the sub-gate was proposed and demonstrated. To alleviate the drawbacks related to the nonself-aligned offset channel length in the original version, a self-aligned offset channel length is achieved in the new device by forming the silicide source/drain junction self-aligning to the sidewall spacers abutting the gate. This results in not only one mask count saving but also better device performance, as facilitated by the reduced offset channel length of the self-aligned sidewall spacers. Moreover, the adoption of PtSi for the Schottky junction further improves the on-state current of p-channel operation, while a thinner oxide employed underneath the sub-gate effectively reduces the sub-gate bias needed to form the electrical junction to below 5 V. Significant improvement in on-current as well as leakage current reduction is achieved in the new improved device.     

Performance of Carbon monoxide-sensitive MOSFET's with metal-Oxide semiconductor gates

A multilayer PdO-Pd-gate metallization was investigated at a MOS-CO sensor. This type of metallization gives a high CO sensitivity and a good electrical control of the transistor. The performance of this sensor was investigated in comparison to a commercial SnO2resistor CO sensor.     

High holding voltage C-MOS technology with lightly doped source and drain regions

This work presents the results of measurements and simulations of n-well C-MOS structures fabricated to study the effect of reduced source-drain doping of p-channel MOSFET's on latchup triggering and holding characteristics. It is shown that lighter dopings, degrading the emitter efficiency of the parasitic p-n-p bipolar transistor, lead to improved latchup resistance that can be conveniently traded off versus the induced decrease of MOSFET transconductance.     

Source and drain resistance determination for MOSFET's

A new method has been developed for determining the source and drain resistances of MOSFET's from 2-D process and device modeling. The method connects the current predicted from a standard drain current formula to an approximate current computed from the output of a 2-D device simulator. This approximate current is compared with the exact current calculated from the 2-D device simulator to locate the effective edges of the inversion channel. The source/drain resistance for use in the standard formula is then computed from the quasi-Fermi levels at these effective channel edges. Good agreement is obtained with source/drain resistances extracted from experimental ID-VG data.     

Carrier mobility in MOSFETs fabricated with Hf-Si-O-N gate dielectric, polysilicon gate electrode, and self-aligned source and drain

A study of electron and hole mobilities for MOSFET devices fabricated with Hf-Si-O-N gate dielectric, polysilicon gate electrodes and self-aligned source and drain is presented. High effective electron and hole mobilities, 250 cm/sup 2//V/spl middot/s and 70 cm/sup 2//V/spl middot/s, respectively, were measured at high effective field (>0.5 MV/cm). The NMOSFETs have an equivalent oxide thickness (EOT) of 1.3 nm and the PMOSFETs have an EOT of 1.5 nm. The effect of interface engineering on the electron and hole mobilities is discussed.     

Fabrication of planar Gunn-effect logic device with self-aligned Schottky-barrier gates

A method of fabricating planar Gunn-effect devices with Schottky-barrier gates has been improved by using the self-alignment technique. Dual-gate devices fabricated by this method have fine geometries and exhibited sufficiently good performance.     

Inverted thin-film transistors with a simple self-aligned lightlydoped drain structure

The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length L_ch. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to L_ch, L_LDD, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of ~1.25 μA at 5 V and a leakage current of ~0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is ~7×10⁶