Improved high-voltage lateral RESURF MOSFETs in 4H-SiC

High-voltage lateral RESURF metal oxide semiconductor field effect transistors (MOSFETs) in 4H-SiC have been experimentally demonstrated, that block 900 V with a specific on-resistance of 0.5 Ω-cm² . The RESURF dose in 4H-SiC to maximize the avalanche breakdown voltage is almost an order of magnitude higher than that of silicon; however this high RESURF dose leads to oxide breakdown and reliability concerns in thin (100-200 nm) gate oxide devices due to high electric field (>3-4 MV/cm) in the oxide. Lighter RESURF doses and/or thicker gate oxides are required in SiC lateral MOSFETs to achieve highest breakdown voltage capability     

High performance of high-voltage 4H-SiC Schottky barrier diodes

High performance of high-voltage rectifiers could be realized utilizing 4H-SiC Schottky barrier diodes. A typical specific on-resistance (R_on) of these devices was 1.4×10³ Ω cm³ at 24°C (room temperature) with breakdown voltages as high as 800 V. These devices based on 4H-SiC had R _on's lower than 6H-SiC based high-power rectifiers with the same breakdown voltage. As for Schottky contact metals, Au, Ni, and Ti were employed in this study. The barrier heights of these metals for 4H-SiC were determined by the analysis of current-voltage characteristics, and the reduction of power loss could be achieved by controlling the barrier heights     

Inductive switching of 4H-SiC gate turn-off thyristors

The high-temperature operation of a silicon carbide gate turn-off thyristor is evaluated for use in inductively loaded switching circuits. Compared to purely resistive load elements, inductive loads subject the switching device to higher internal power dissipation. The ability of silicon carbide components to operate at elevated temperatures and high power dissipations are important factors for their use in future power conversion/control systems. In this work, a maximum current density of 540 A/cm² at 600 V was switched at a frequency of 2 kHz and at several case temperatures up to 150°C. The turn-off and turn-on characteristics of the thyristor are discussed     

P-type 4H and 6H-SiC high-voltage Schottky barrier diodes

High-voltage Schottky barrier diodes have been successfully fabricated for the first time on p-type 4H- and 6H-SiC using Ti as the barrier metal. Good rectification was confirmed at temperatures as high as 250°C. The barrier heights were estimated to be 1.8-2.0 eV for 6H-SiC and 1.1-1.5 eV for 4H-SiC at room temperature using both I-V and C-V measurements. The specific on resistance (R_on,sp) for 4H- and 6H-SiC were found to be 25 mΩ cm^-2 and 70 mΩ cm^-2 at room temperature. A monotonic decrease in resistance occurs with increasing temperature for both polytypes due to increased ionization of dopants. An analytical model is presented to explain the decrease of R_on,sp with temperature for both 4H and 6H-SiC which fits the experimental data. Critical electric field strength for breakdown was extracted for the first time in both p-type 4H and 6H-SiC using the breakdown voltage and was found to be 2.9×10⁶ V/cm and 3.3×10⁶ V/cm, respectively. The breakdown voltage remained fairly constant with temperature for 4H-SiC while it was found to decrease with temperature for 6H-SiC     

4H-SiC基超结器件各向异性的TCAD建模分析

基于文献报道的4H-SiC材料的各向异性物理特性,首次提出4H-SiC基超结器件的各向异性物理模型,并对不同晶向的碰撞电离分别进行考虑。基于该模型,我们对 和 两种晶向晶圆的4H-SiC超结器件的电学特性进行了研究。与 晶圆相比, 晶圆的碰撞电离系数较小,可以实现更高的击穿电压。由于碰撞电离各向异性,与传统4H-SiC基器件相比,超结器件的二维电场分布可以将 晶圆器件的击穿电压从 晶圆器件的60%提高到72%。     

A self-aligned process for high-voltage, short-channel vertical DMOSFETs in 4H-SiC

In this paper, we describe a self-aligned process to produce short-channel vertical power DMOSFETs in 4H-SiC. By reducing the channel length to /spl les/0.5 /spl mu/m, the specific on-resistance of the MOSFET channel is proportionally reduced, significantly enhancing performance.     

I-V characteristics of high-voltage 4H-SiC diodes with a 1.1-eV Schottky barrier

The I-V characteristics of high-voltage 4H-SiC diodes with a Schottky barrier ∼1.1 eV in height are measured and analyzed. The forward I-V characteristics proved to be close to “ideal” in the temperature range of 295–470 K. The reverse I-V characteristics are adequately described by the model of thermionic emission at the voltages to 2 kV in the temperature range of 361–470 K if, additionally, a barrier lowering with an increase in the band bending in the semiconductor is taken into account.     

Characterization of hard- and soft-switching performance of high-voltage Si and 4H-SiC PiN diodes

This paper presents a study of the performance of high-voltage Si and 4H-SiC diodes in a DC-DC buck converter. Device operation in both hard- and zero-voltage switching conditions is presented with the help of measurements and two-dimensional (2-D) mixed device-circuit simulations. Experimental results show that SiC PiN diodes have a strong potential for use in high-speed high-voltage power electronics applications operating at high temperature. A combination of low excess carrier concentration and low carrier lifetime results in superior switching performance of the 4H-SiC diode over ultrafast Si diodes. Soft switching is shown to minimize the switching loss and allow operation at higher switching frequencies using Si diodes. The power loss of 4H-SiC diodes is dominated by conduction loss. Consequently, soft-switching techniques result in a marginal reduction in power loss. However, the low overall power loss implies that SiC diodes can be used at very high switching frequencies even in hard-switching configurations.     

Low-loss, high-voltage 6H-SiC epitaxial p-i-n diode

The p-i-n diodes were fabricated using 31 /spl mu/m thick n/sup -/- and p-type 6H-SiC epilayers grown by horizontal cold-wall chemical vapor deposition (CVD) with nitrogen and aluminum doping, respectively. The diode exhibited a very high breakdown voltage of 4.2 kV with a low on-resistance of 4.6 m/spl Omega/cm/sup 2/. This on-resistance is lower (by a factor of five) than that of a Si p-i-n diode with a similar breakdown voltage. The leakage current density was substantially lower even at high temperatures. The fabricated SiC p-i-n diode showed fast switching with a turn-off time of 0.18 /spl mu/s at 300 K. The carrier lifetime was estimated to be 0.64 /spl mu/s at 300 K, and more than 5.20 /spl mu/s at 500 K. Various characteristics of SiC p-i-n diodes which have an advantage of lower power dissipation owing to conductivity modulation were investigated.     

A 475-V high-voltage 6H-SiC lateral MOSFET

High-voltage lateral MOSFET's on 6H- and 4H-SiC have been fabricated with 400-475 V breakdown voltage using the RESURF principle. An MOS electron inversion layer mobility of about 50 cm²/V-s is obtained on 6H-SiC wafers. This mobility is high enough such that the specific on-resistance of the 6H-SiC MOSFET's (~0.29-0.77 Ω-cm²) is limited by the resistance of the drift layer, as desired. However, the implanted drift layer resistance is about ten times higher than expected for the implant dose used. Design and process changes are described to decrease the on-resistance and increase the breakdown voltage. For 4H-SiC, extremely low mobility was obtained, which prevents satisfactory device operation     

4H-SiC power devices for use in power electronic motor control

Silicon carbide (SiC) is an emerging semiconductor material which has been widely predicted to be superior to both Si and GaAs in the area of power electronic switching devices. This paper presents an overview of SiC power devices and concludes that the MOS turn-off thyristor (MTO™), comprising of a hybrid connection of SiC gate turn-off thyristor (GTO) and MOSFET, is one of the most promising near term SiC switching device given its high power potential, ease of turn-off, 500°C operation and resulting reduction in cooling requirements. The use of a SiC and an anti-parallel diode are primary active components which can then be used to construct an inverter module for high-temperature, high-power direct current (d.c.) motor control.     

Trade-off relations for high-voltage switching transistors

This paper presents trade-off relations between device performance and parameters for high-voltage switching transistors. These curves are found to be in good agreement with experimental results and are not only useful for improving device performance but also may lead to higher yield.     

Second breakdown in high-voltage switching transistors

A 2-dimensional mathematical model which includes the avalanche multiplication and internal self-heating effects has been used to predict the internal behaviour of a typical high-voltage power-transistor design. Collector n?-n+ interface is the region of high electrical and thermal stresses which cause second-breakdown failure at high-current and high-voltage operating conditions.     

Active defects in MOS devices on 4H-SiC: A critical review

The state-of-the-art 4H-SiC MOSFETs still suffer from performance (low channel-carrier mobility and high threshold voltage) and reliability (threshold voltage instability) issues. These issues have been attributed to a large density of electrically active defects that exist in the SiO₂–SiC interfacial region. This paper reviews the earlier and the latest results about the responsible defects for the performance and reliability issues of SiC MOS devices, in the context of the evolution of physical understanding of these defects. The aim of this critical review is to clarify possible confusions due to inconsistencies between the earlier and the latest results. Specific clarifications relate to the physical position of the active defects (whether they are located at or near the SiO₂–SiC interface) and the energy position of their energy levels (above or below the bottom of conduction band).     

Investigation of the reliability of 4H-SiC MOS devices for high temperature applications

In this paper, the excellent reliability of 4H-SiC MOS devices during high temperature operation is demonstrated for a gate oxide processed in N₂O. A temperature dependent Fowler-Nordheim analysis is used to show that statistical energy spreading accounts for only part of the reported temperature induced barrier height degradation. Poole-Frenkel current caused by acceptor like traps in the oxide due to carbon interstitials is proposed to be responsible for the additional current observed. Temperature and electric field acceleration of the time to dielectric breakdown is investigated at elevated temperatures in order to predict the expected MOS lifetime during high temperature operation.     

Self-heating and destruction of high-voltage 4H-SiC rectifier diodes under a single short current surge pulse

Self-heating of high-voltage (6 kV class) 4H-SiC rectifier p⁺–n–n⁺ diodes under the action of a single 20 μs forward current surge pulse has been studied experimentally up to current densities j ≈ 100 kA/cm². The diode parameters are stable after a single surge pulse with current density j ≈ 60 kА/cm², although the estimated temperature of the diode at the end of this pulse is ～1650 K. After several pulses of this amplitude or after subjecting the diode to pulses with higher current density, the diode degrades. The degradation is manifested in an irreversible decrease of the differential resistance of the diode under a high forward bias. Even a single 20 μs pulse with peak current density j ≈ 100 kA/cm² leads to total destruction of the device.     

Optimization of junction termination extension for ultrahigh voltage 4H-SiC planar power devices

Numerical simulations on the optimization of junction termination extension (JTE) have been performed. Various termination techniques have been applied and simulated in this paper, such as single-zone JTE (S-JTE), multi-zone JTE (M-JTE), and space-modulated JTE (SM-JTE). A completely novel and efficient method is demonstrated in this paper to determine total length of SM-JTE, and it is verified through simulation results. The simulation results show that the SM-JTE could provide a protection efficiency (defined in Section 2) of 95.2%, which is much higher than that of M-JTE (82.4%) and S-JTE (64.7%). Based on the fabricated MOSFETs, the interface charge density is extracted and the approximate range of charge density has been determined. The influences of different interface charge densities have been investigated for the three termination techniques respectively. According to the previous reports, the JTE is quite sensitive to the implanted dose, so the blocking capability of each termination structure with different implanted doses is also simulated. The results show that when interface charge is considered, the SM-JTE always shows an enormous advantage over the other two junction termination structures, however the interface charge densities varied. The space-modulated JTE is also applicable to the power planar devices such as MOSFETs and IGBTs, which would provide a very promising lower fabrication cost.     

Avalanche breakdown in high-voltage D-MOS devices

A new type of voltage breakdown occurring in high-voltage D-MOS transistors is described. This effect severely reduces the high-voltage capability of these devices when the gate field plate is extended through the drift region toward overlapping the n⁺drain contact region. The breakdown is shown to be due to an avalanche phenomenon appearing close to the n⁺region, due to the very high field induced in this NIOS structure in nonequilibrium. A first-order theory is developed to confirm the conclusions of the experimental study.     

A 765 mW high-voltage switching ADSL line-driver

With the increasing popularity of ADSL-modems, there is a stringent need to develop highly efficient line-drivers. Currently most line-drivers use linear amplifiers, such as class AB. Due to the nature of the DMT-encoded signal, the efficiency of such amplifiers is limited. Another issue is the transformer turns ratio and the resulting supply voltage of the amplifier. In general, a high-voltage supply is needed. In this paper, a high-voltage switching differential amplifier using a 50 V supply is described. The maximum efficiency into a matched load yields over 40%, with an efficiency of 13.1% for a full downstream signal while maintaining a minimum MTPR of 40 dB. The circuit is processed in a 100 V, 0.7 μm technology.     

Bias temperature reliability of p-channel high-voltage devices

Important shifts in the threshold voltage of high voltage p-channel DMOS transistors have been observed. These shifts are strongly dependent on the stress conditions.An empirical degradation model is derived from measurement data. For a given allowed shift in threshold voltage, this model can determine the safe operating area of the device.The shift in threshold voltage in the p-channel DMOS transistors is explained by excitation and trapping of holes at the oxide-silicon interface at the drain side.