Evaluation of 850°C wet oxide as the gate dielectric in a0.8-μm CMOS process

The authors describe a detailed comparison of a 850°C wet oxide and a 900°C dry oxide as the MOS gate dielectric in a 0.8-μm CMOS process. The device fabrication involves a GE 0.8-μm CMOS process. Emphasis is given to poly-Si gate linewidth measurements which are crucial to the interpretation of the results. The comparison of thin oxide integrity, device characteristics, hot-electron reliability, and total-dose radiation hardness between the two oxides is discussed. Specifically, it is pointed out why the PMOS punchthrough voltage requirements mandate the use of a 850°C wet oxide for the gate dielectric     

0.1-μm p+-GaAs gate HJFET's fabricated using two-stepdry-etching and selective MOMBE growth techniques

This paper reports the first successful fabrication of high-performance, 0.1-μm p⁺-gate pseudomorphic heterojunction-FET's (HJFET's). By introducing the two-step dry-etching technique which compensates for the poor dry-etching resistance of PMMA, 0.1-μm or less gate-openings with a high aspect-ratio of 3.5 in SiO ₂ film are achieved. In addition, by using the gate electrode filling technique with selective MOMBE p⁺-GaAs growth, 0.1-μm voidless p⁺-GaAs gate electrodes with a high aspect-ratio are achieved for the first time. The fabrication technology leads to a reduction of external gate fringing capacitance (Ce^ext _f) in a T-shaped gate-structure and an improvement in gate turn-on voltage. The fabricated 0.1-μm, T-shaped, p⁺-gate n-Al_0.2Ga_0.8As/In_0.25Ga_0.75 As HJFET exhibits a high gate turn-on voltage (V_f) of about 0.9 V, and a good gm_max of 435 mS/mm. Also, an excellent microwave performance of f_T=121 GHz and f_max =144 GHz is achieved due to the C^ext_f reduction. The technology and device show great promise for future high-speed applications, such as in power devices, MMIC's, and digital IC's     

Disposable polysilicon LDD spacer technology

An advanced 0.5-μm CMOS disposable lightly doped drain (LDD) spacer technology has been developed. This 0.5-μm CMOS technology features surface-channel LDD NMOS and PMOS devices, n⁺/p⁺ poly gates, 125-A-thick gate oxide, and Ti-salicided source/drain/gate regions. Using only two masking steps, the NMOS and PMOS LDD spacers are defined separately to provide deep arsenic n⁺ regions for lower salicided junction leakage, while simultaneously providing shallow phosphorus n^- and boron p^- regions for improved device short-channel effects. Additionally, the process allows independent adjustment of the LDD and salicide spacers to optimize the LDD design while avoiding salicide bridging of source/drain to gate regions. The results indicate extrapolated DC hot-carrier lifetimes in excess of 10 years for a 0.3-μm electrical channel-length NMOS device operated at a power-supply voltage of 3.3 V     

An investigation of a molybdenum gate for submicrometer CMOS

Processing issues including Mo deposition, gate etching, ion implant channeling, and integration of a Mo gate with high-temperature processing are discussed. Methods for addressing these issues are described. A 0.8-μn Mo-gate CMOS process incorporating these methods has been developed. Submicrometer Mo-gate NMOS and PMOS devices and 0.8-μm CMOS ring oscillator results are presented. The high performance of these devices and circuits demonstrates the potential of a Mo gate     

Self-aligned bottom-gate submicrometer-channel-length a-Si-:Hthin-film transistors

Fully self-aligned bottom-gate thin-film transistors (TFTs) fabricated by using a back substrate exposure technique combined with a metal lift-off process are discussed. Ohmic contact to the sources and drains is accomplished by a 40-nm-thick layer of phosphorous-doped microcrystalline silicon. Devices with channel lengths ranging from 0.4 to 12 μm are processed with overlap dimensions between the gate and the source and the gate and the drain ranging from 0.0 to 1.0 μm. Analysis of the conductance data in the linear voltage regime reveals a parasitic drain-to-channel and source-to-channel resistance that is 14% of the channel resistance for a 10-μm device and 140% for a 1-μm device. Thus, increase in the device speed caused by reducing the channel length does not follow expected behavior. A similar situation exists in the nonlinear regime. The on-current of the devices starts to saturate below channel lengths of 2 μm. Current on/off ratios taken at V_d=5 V and V_G=15 V and 0 V, respectively, are approximately 1×10⁶ for the 1- and 12-μm-long devices. The on/off ratio is reduced to 1×10⁵ for the 0.4-μm device     

An 0.1-μm voidless double-deck-shaped (DDS) gate HJFET withreduced gate-fringing-capacitance

This paper describes a novel double-deck-shaped (DDS) gate technology for 0.1-μm heterojunction FETs (HJFETs) which have about half the external gate fringing capacitance (C_f^ext) of conventional T-shaped gate HJFET's. By introducing a T-shaped SiO₂-opening technique based on two-step dry-etching with W-film masks, we fabricated 0.1-μm gate-openings which were suitable for reducing the C_f^ext and filling gate-metals with voidless. The fine gate-openings are completely filled with refractory WSi/Ti/Pt/Au gate-metal by using WSi-collimated sputtering and electroless Au-plating, resulting in high performance 0.1-μm DDS gate HJFETs are fabricated. The 0.1-μm n-Al _0.2Ga_0.8As/i-In_0.15Ga_0.85As pseudomorphic DDS gate HJFETs exhibited an excellent V_th standard-deviation (σV_th) of 39 mV because dry-etching techniques were used in all etching-processes. Also, an HJFET covered with SiO₂ passivation film had very high performance with an f_T of 120 GHz and an f_max of 165 GHz, due to the low C_f^ext with the DDS gate structure. In addition, a high f_T of 151 GHz and an f_max of 186 GHz were obtained without a SiO₂ passivation film. This fabrication technology shows great promise for high-speed IC applications     

Low-resistance self-aligned Ti-silicide technology for sub-quartermicron CMOS devices

A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent pre-amorphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices. 0.15-μm CMOS devices with low-resistance and uniform TiSi₂ on gate and source/drain regions were fabricated using the SEDAM process. Non-doped silicon films were selectively deposited on gate and source/drain regions to reduce suppression of silicidation due to heavily-doped As in the silicon. Silicidation was also enhanced by pre-amorphization, using ion-implantation, on the narrow gate and source/drain regions. Low-resistance and uniform TiSi₂ films were achieved on all narrow, long n⁺ and p⁺ poly-Si and diffusion layers of 0.15-μm CMOS devices. TiSi₂ films with a sheet resistance of 5 to 7 Ω/sq were stably and uniformly formed on 0.15-μm-wide n⁺ and p⁺ poly-Si. No degradation in leakage characteristics was observed in pn-junctions with TiSi₂ films. It was confirmed that, using SEDAM, excellent device characteristics were achieved for 0.15-μm NMOSFET's and PMOSFET's with self-aligned TiSi₂ films     

High-performance GaAs MESFETs with advanced LDD structure fordigital, analog, and microwave applications

GaAs MESFETs with advanced LDD structure have been developed by using a single resist-layered dummy gate (SRD) process. The advanced LDD structure suppresses the short channel effects, and reduces source resistance, while maintaining a moderate breakdown voltage. The 0.3-μm enhancement-mode devices exhibit a transconductance of 420 mS/mm, while the breakdown voltage of the depletion-mode device (V_th=-500 mV) is larger than 6 V. The standard deviation of the threshold voltage for 0.3-μm devices is less than 30 mV across a 3-in wafer. The 0.3-μm devices exhibit an average cutoff frequency of 47.2 GHz with a standard deviation of 1.3 GHz across a 3-in wafer. The cutoff frequency of a 0.15-μm device is as high as 72 GHz. D-type flip-flop circuits for digital IC applications and preamplifier for analog IC applications fabricated with 0.3-μm gate length devices operate above 10 Gb/s. In addition, the 0.3-μm devices also show good noise performance with a noise figure of 1.1 dB with associated gain of 6.5 dB at 18 GHz. These results demonstrate that GaAs MESFETs with an advanced LDD structure are quite suitable for digital, analog, microwave, and hybrid IC applications     

Optimization of a self-aligned titanium silicide process forsubmicron technology

The optimization of a manufacturable self-aligned titanium silicide process is described. In particular, the integrity of the TiSi ₂ layer has been studied versus the BPSG reflow conditions. Excellent contact resistance and very low leakage currents have been obtained. The good device parameters obtained with an n⁺ or n ⁺/p⁺ gate have demonstrated that the self-aligned process can be integrated in a 0.8-μm double-metal CMOS process     

0.2-μm fully-self-aligned Y-shaped gate HJFET's with reducedgate-fringing capacitance fabricated using collimated sputtering andelectroless Au-plating

This paper reports on new fully-self-aligned gate technology for 0.2-μm, high-aspect-ratio, Y-shaped-gate heterojunction-FET's (HJFET's) with about half the external gate-fringing capacitance (C_f^rext) of conventional Y-shaped gate HJFET's. The 0.2-μm Y-shaped gate openings are realized by anisotropic dry-etching with stepper lithography and SiO₂ sidewall techniques instead of electron beam lithography. By introducing WSi-collimated sputtering and electroless gold-plating techniques for the first time, we have developed a high-aspect-ratio, voidless and refractory Y-shaped gate-electrode without the need for mask alignments. A fabricated 0.2-μm gate n-Al_0.2Ga_0.8As/In_0.2Ga_0.8As HJFET shows very small current saturation voltage of 0.25 V, marked gm _max of 631 mS/mm with 6-V gate-reverse breakdown voltage, and excellent threshold voltage uniformity of 9 mV. Also, the improved rf-performance such as f_T=71 GHz and f_max=120 GHz is realized even with the passivation for the high-aspect-ratio gate-structure with reduced C_f^rext. The developed technology based upon a fully-self-aligned and an all-dry-etching process provides higher performance and uniformity, thus it is very promising for high-speed and low-power-consumption digital and/or analog IC's/LSI's     

A high gain n-well/gate tied PMOSFET image sensor fabricated from astandard CMOS process

The performance of a high gain photodetector fabricated using a standard 0.8-μm, triple metal, n-well CMOS process is reported, The photodetector is formed by connecting the gate of the PMOSFET and n-well together while keeping both floating. The depletion region induced by the floating gate and the well-to-substrate p-n junction separate the optically generated electron-hole pairs in the direction perpendicular to the current flow. The n-well potential modulated by illumination is fed back to the gate through the well-to-gate connection, which results in an extra current amplification beyond that of a normal PMOSFET biased in the lateral bipolar mode. A high responsivity of 2.5×10³ A/W has been measured with an operating voltage as low as 0.3 V for a W/L of 8.2 μm/0.8 μm. The impact of technology scaling on the performance of the photodetector are also studied. A simple 32×32-pixel image sensor array was fabricated to demonstrate the feasibility of integrating the new device in actual circuit applications     

Manufacturing study of yield and performance dependence on gatelength of submicron AlInAs-GaInAs HEMTs

The fabrication, characterization, and statistical analysis of the performance and yield of AlInAs-GaInAs on InP low-noise high electron mobility transistors (HEMTs) with subquarter-micron T-gates fabricated with electron beam lithography are reported. This was undertaken to establish the manufacturability of submicron AlInAs-GaInAs HEMT technology for various low-noise microwave receiver applications. Excellent DC device yield (up to 90%) was obtained from devices to gate widths 300 μm and 1000 μm. A range of minimum noise figures between 0.026 to 0.5 dB at 2 GHz and 0.39 to 0.8 dB at 12 GHz were obtained for 0.15-μm and 0.20-μm gate length devices. The results establish the correlation between the noise figure and yield for this new class of microwave devices     

Influence of quantum-well width on device performance ofAl0.30Ga0.70As/In0.25Ga0.75As (on GaAs) MODFETs

An experimental study in which the quantum well width (W) is varied from 45 to 200 Å is discussed. Optimum device performance was observed at a well width of 120 Å. The 0.2-μm×130-μm devices with 120-Å quantum-well width typically exhibit a maximum channel current density of 550 mA/mm, peak transconductance of 550 mS/mm, and peak current gain cutoff frequency ( f_T) of 122 GHz. These results have been further improved in subsequent fabrications employing a trilevel-resist mushroom-gate process. The 0.2-μm×50-μm devices with mushroom gate exhibit a peak transconductance of 640 mS/mm, peak f _T of 100 GHz, and best power gains cutoff frequency in excess of 200 GHz. These results are among the best ever reported for GaAs-based FETs and are attributed to the high two-dimensional electron gas (2DEG) sheet density, good low-field mobility, low ohmic contact, and the optimized mushroom gate process     

A 40-ps high electron mobility transistor 4.1 K gate array

A high-electron mobility transistor (HEMT) 4.1 K-gate array has been developed, using a selective dry etching process and a MBE (molecular-beam epitaxy) growth technology. The circuit design uses direct-coupled FET logic (DCFL). The chip contains 4096 NOR gates, each with a 0.8-μm gate length, and measures 6.3 mm×4.8 mm. A basic gate delay of 40 ps has been achieved. A 16×16-bit parallel multiplier, used to test this array, has a multiplication time of 4.1 ns at 300 K, where the power dissipation is 6.2 W     

A 100-MHz 64-tap FIR digital filter in 0.8-μm BiCMOS gate array

A 64-tap FIR (finite impulse response) digital filter that has been designed using a newly developed filter compiler and fabricated in a 0.8-μm triple-level interconnect BiCMOS gate array technology is presented. The filter has been tested and is fully functional at a 100-MHz clock rate. These results are obtained by combining an optimized architecture and gate array floorplan with submicrometer BiCMOS technology. The filter occupies 49 mm², which is approximately two-thirds of the 100 K gate array core. The design uses an equivalent of 55 K gates (two-input NAND gates). The device input/output are 100 K emitter-coupled-logic (ECL) compatible     

Demonstration of submicron depletion-mode GaAs MOSFETs withnegligible drain current drift and hysteresis

We successfully fabricated submicron depletion-mode GaAs MOSFETs with negligible hysteresis and drift in drain current using Ga₂ O₃(Gd₂O₃) as the gate oxide. The 0.8-μm gate-length device shows a maximum drain current density of 450 mA/mm and a peak extrinsic transconductance of 130 mS/mm. A short-circuit current gain cutoff frequency (f_T) of 17 GHz and a maximum oscillation frequency (f_max) of 60 GHz were obtained from the 0.8 μm×60 μm device. The absence of drain current drift and hysteresis along with excellent characteristics in the submicron devices is a significant advance toward the manufacture of commercially useful GaAs MOSFETs     

Quantum-well p-channel AlGaAs/InGaAs/GaAs heterostructureinsulated-gate field-effect transistors with very high transconductance

Quantum-well p-channel pseudomorphic AlGaAs/InGaAs/GaAs heterostructure insulated-gate field-effect transistors with enhanced hole mobility are described. The devices exhibit room-temperature transconductance, transconductance parameter, and maximum drain current as high as 113 mS/mm, 305 mS/V/mm, and 94 mA/mm, respectively, in 0.8-μm-gate devices. Transconductance, transconductance parameter, and maximum drain current as high as 175 mS/mm, 800 mS/V/mm, and 180 mA/mm, respectively were obtained in 1-μm p-channel devices at 77 K. From the device data hole field-effect mobilities of 860 cm²/V-s at 300 K and 2815 cm²/V-s at 77 K have been deduced. The gate current causes the transconductance to drop (and even to change sign) at large voltage swings. Further improvement of the device characteristics may be obtained by minimizing the gate current. To this end, a type of device structure called the dipole heterostructure insulated-gate field-effect transistor is proposed     

Gate length scaling for Al0.2Ga0.8N/GaNHJFETs: two-dimensional full band Monte Carlo simulation includingpolarization effect

Two-dimensional self-consistent full band Monte Carlo (FBMC) simulator was developed for electron transport in wurtzite phase AlGaN/GaN heterojunction (HJ) FET. Recessed gate Al_0.2Ga_0.8N/GaN HJFET structures with an undoped cap layer were simulated, where the spontaneous and piezoelectric polarization effects were taken into account. The polarization effect was shown to not only increase the current density, but also improve the carrier confinement, and hence improve the transconductance. An off-state drain breakdown voltage (BV_ds) of 300 V and a maximum linear output power (P_max) of 46 W/mm were predicted for a 0.9-μm gate device. For a 0.1-μm gate device, 60 V BV_ds , 20 W/mm P_max, and 160 GHz current-gain cutoff frequency were predicted. Although there is considerable uncertainty due to lack of information on the band structure, scattering rates, and surface conditions, the present results indicate a wide margin for improvements over current performance of AlGaN/GaN HJFETs in the future. To our knowledge, this is the first report on the FBMC simulation for AlGaN/GaN HJFETs     

Time resolution of NMOS sampling switches used on low-swing signals

A number of recently reported CMOS line receivers and downconversion mixers are based on sampling. A key component in these designs is the NMOS sampling switch. It can sample a very high bandwidth signal, several GHz for a 0.8-μm transistor. We present an expression for the aperture time for an NMOS switch when the input has low swing. The switch can, under this condition, be modeled as a device that determines a weighted average over time of the input signal. The weight function is derived. The aperture time function shows that the maximum theoretical time resolution for a switch in 0.8-μm standard CMOS is 21 ps (~48 Gb/s). SPICE simulations agree with the theory. Transient two-dimensional (2-D) device simulations do not contradict the predicted results. Experiments on a switch made in a 0.8-μm standard CMOS process show successful sampling of every thirty second bit of a 5-Gb/s data stream