一种高性能CMOS采样/保持电路

介绍了一种高性能CMOS采样/保持电路.该电路在3 V电源电压下,60 MHz采样频率时,输入直到奈奎斯特频率仍能够达到90 dB的最大信号谐波比(SFDR)和80 dB的信噪比(SNR).电路采用全差分结构、底板采样、开关栅电压自举(bootstrap)和高性能的增益自举运算放大器.采用0.18 μm CMOS工艺库,对电路进行了Hspice仿真验证.结果表明,整个电路消耗静态电流5.8 mA.     

一种欠采样应用的高精度低功耗采样/保持电路

设计了一种可用于欠采样情况的高精度、低功耗采样/保持电路。在40 MHz时钟频率下,采样90 MHz输入信号时可达11位以上精度。采用电容翻转结构的采样/保持电路,以消除电容失配的影响;使用栅压自举开关,以提高线性度,实现欠采样输入;并设计了一种高增益、大带宽、低功耗的增益自举套筒式共源共栅(telescopic cascode)运算放大器。电路采用SMIC 0.35μmCMOS工艺实现,电源电压为3.3 V,功耗仅为7.6 mW。     

一个用于14位采样保持电路的全差分增益增强放大器的分析和设计

介绍了一种全差分增益增强CMOS运算放大器的设计和实现。该放大器用于14位20 MHz采样频率的流水线模/数转换器(A/D)的采样保持电路。为了实现大的输入共模范围,采用折叠式共源共栅放大器。主放大器采用开关电容共模反馈电路在获得大输出摆幅的同时降低了功耗。辅助放大器则采用简单的连续时间共模反馈电路。该放大器采用UMC Logic 0.25μm工艺,电源电压为2.5 V。Hspice仿真结果显示,在负载为15 pF的情况下,其增益为104 dB,单位增益带宽为166 MHz。     

一种100 MHz采样频率CMOS采样/保持电路

设计了一种高速采样保持电路。该电路采用套筒级联增益自举运算放大器,可在达到高增益高带宽的同时最大程度地减小功耗;优化了采样开关,获得了良好的线性度,减少了输出误差;电路的采样频率达到100 MHz。采用Charter半导体公司的0.35μm标准CMOS工艺库,对整体电路和分块电路进行了性能分析和仿真。     

一种14位125MHz采样/保持电路的设计

设计了一种高性能采样/保持(S/H)电路,采用全差分电容翻转型的主体结构,有效减小了噪声和功耗.在电路设计中,采用栅压自举开关,极大地减小了非线性失真,同时,有效地抑制了输入信号的直流偏移.采样/保持放大器电路采用折叠共源共栅结构,由于深亚微米工艺中器件本征增益减小,S/H电路为达到更高增益,采用增益提升技术.设计的采样/保持电路采用0.18μm1P5M工艺实现,在1.8V电源电压、125 MHz采样速率下,输出差动摆幅达到2 V(VP-P),输入信号到奈奎斯特频率时仍能达到98 dB以上的无杂散动态范围(SFDR),其性能满足14位精度、125MHz转换速率的流水线ADC要求.     

用于10位100 MS/s流水线A/D转换器的采样保持电路

设计了一个用于10位100 MHz采样频率的流水线A/D转换器的采样保持电路。选取了电容翻转结构;设计了全差分套筒式增益自举放大器,可以在不到5 ns内稳定在最终值的0.01%内;改进了栅压自举开关,减少了与输入信号相关的非线性失真,提高了线性度。采用TSMC 0.25μm CMOS工艺,2.5 V电源电压,对电路进行了仿真和性能验证,并给出仿真结果。所设计的采样保持电路满足100 MHz采样频率10位A/D转换器的性能要求。     

采样保持电路中全差分增益提高放大器设计

介绍了一种全差分增益增强CMOS运算放大器的设计和实现。该放大器用于12位20 MHz采样频率的流水线模/数转换器(A/D)的采样保持电路。为了实现大的输入共模范围,采用折叠式共源共栅放大器。主放大器采用开关电容共模反馈电路,辅助放大器则采用简单的连续时间共模反馈电路。该放大器采用CMOS 0.5μm工艺,电源电压为3.3 V。Cadence Spectre仿真结果显示,在负载为6 p F的情况下,其增益为99 d B,单位增益带宽为318 MHz,相位裕度为53°。     

两倍增益10位100 MSPS CMOS采样/保持电路

提出了一种两倍增益高线性、高速、高精度采样/保持电路。该采样/保持电路通过对输入信号实现两倍放大,改善了高频非线性失真;一种新型的消除衬底偏置效应的采样开关,有效地提高了采样的线性度;高增益和宽带宽的折叠共源共栅运算放大器保证了采样/保持电路的精度和速度。整个电路以0.35μm AMS Si CMOS模型库验证。模拟结果显示,在输入信号为49.21875MHz正弦波,采样频率为100 MHz时,增益误差为70.9μV,SFDR可达到84.5 dB。     

Flip-around结构高速采样保持电路的设计

分析了Flip-around结构采样保持电路产生失真的原因。采用增加哑开关管的自举开关,消除与输入有关的电荷注入和时钟馈通;采用增益增强技术,提高运算放大器的直流增益,并通过调整辅助运放的负载电容大小,实现主运放建立时间特性的优化。设计了一个Flip-around结构的高速采样保持电路;对电路各模块进行了功能仿真,给出了整个采样保持电路的仿真结果。     

一种高线性度超宽带采样/保持电路

设计了一种桥式并-串联级联结构的高线性度、超宽带采样/保持电路。该采样/保持电路包括输入缓冲器、辅助开关和SEF开关三个单元。采用桥式并-串联级联结构改进的辅助开关模块单元,大幅提高了电路的线性度和带宽。该采样保持电路基于0.13 μm SiGe双极型工艺进行设计,-4.75 V和2 V双电源电压供电。仿真结果表明,在100 fF采样电容、6.25 GHz采样频率、10.28 GHz输入频率的条件下,SFDR为69.60 dB,THD为-65.25 dB,-3 dB带宽达 35.43 GHz。     

Circuit Techniques for CMOS Divide-By-Four Frequency Divider

This letter describes circuit techniques for obtaining divide-by-four (divide4) frequency dividers (FDs) from CMOS ring-oscillator based injection locked frequency dividers (ILFDs). The circuit is made of a two-stage differential CMOS ring oscillator and is based on MOS switches directly coupled to the differential outputs of the ring oscillator. At the supply voltage of 1.8V and at the incident power of 0dBm, for a dual-band ILFD, the divide4 ILFD can provide a locking range of 6.3% from 5.39 to 6.12GHz at low band and 5.9% from 8.84 to 9.38GHz at high band when the dc bias of MOS switches V_inj changes from 0.7 to 1.1V     

Two 1-V Fully Differential CMOS Switched-Capacitor Amplifiers

Two 1-V fully differential CMOS switched-capacitor amplifiers in a standard CMOS 0.35-μm technology are presented. The improved bootstrapped switches are used to allow rail-to-rail signal swing. The circuit design of the major building blocks is described. The performance of these two circuits is demonstrated by experimental results.     

A Wide Band Injection Locked Frequency Divider With Variable Inductor Load

This letter proposes a new wide band CMOS injection locked frequency divider (ILFD). The circuit is made of a two-stage differential CMOS ring oscillator and is based on MOS switches directly coupled to the differential outputs of the ring oscillator. A tuning circuit composed of inductors in series with a metal oxide semiconductor field effect transistor is used to extend the locking range. The divide-by-two ILFD can provide wide locking range and the measured results show that at the supply voltage of 1.8 V, the free-running frequency of the ILFD is operating from 0.92 to 3.6 GHz while the Vtune is tuned from 0 to 1.8 V. At the incident power of 0 dBm, this ILFD has a wide locking range from 1.15 to 7.4 GHz     

一种12位80 MS/s CMOS流水线ADC设计

介绍了一种12 bit 80 MS/s流水线ADC的设计,用于基带信号处理,其中第一级采用了2.5 bit级电路,采样保持级采用了自举开关提高线性,后级电路采用了缩减技术,节省了芯片面积.采用了折叠增益自举运放,优化了运放的建立速度,节省了功耗.芯片采用HJTC0.18μm标准CMOS工艺,1.8 V电压供电,版图面积2.3 mm × 1.4 mm.版图后仿真表明,ADC在8 MHz正弦信号1 V峰值输入下,可以达到11.10 bit有效精度,SFDR达到80.16 dB,整个芯片的功耗为155 mW.     

一种单片集成相敏解调器

本文给出了一种由CMOS工艺制成的单片全波相敏解调集成电路,由一个差分放大器,一个精密比较器和模拟开关组成。详细介绍了该电路的工作原理,呈现设计结果。     

A 14-bit high-temperature /spl Sigma//spl Delta/ modulator in standard CMOS

Experimental verification is given for the use of /spl Sigma//spl Delta/ modulation for high-temperature applications (/spl ges/approximately 150/spl deg/C) in a standard CMOS process. Switched-capacitor circuits are used to implement a second-order single-stage and a third-order 2-1 MASH /spl Sigma//spl Delta/ modulator with single-bit quantization. The two modulators have an oversampling ratio of 256 with an input signal bandwidth of 500 Hz. The modulators were fabricated in a 1.5-/spl mu/m standard CMOS technology. A fully differential signal path and near minimum sized switches are used to mitigate the effect of large junction-to-substrate leakage current present at high temperatures. Experimental results show both modulators are capable of over 14 bits of resolution at 225/spl deg/C and over 13 bits of resolution at 255/spl deg/C. Results show that the single-stage modulator is more resistant to high-temperature circuit impairment than is the MASH cascaded structure.     

900MHz CMOS锁相环/频率综合器

给出了一个900MHz CMOS锁相环/频率综合器的设计,设计中采用了电流可变电荷泵及具有初始化电路的环路滤波器.电荷泵电流对温度与电源电压变化的影响不敏感,同时电流的大小可通过外部控制信号进行切换控制而改变.因此,锁相环的特性,诸如环路带宽等,也可通过电流的改变而改变.采用具有初始化电路的环路滤波器可提高锁相环的启动速度.另外采用了多模频率除法器以实现频率合成的功能.该电路采用0.18μm、1.8V、1P6M标准数字CMOS工艺实现.     

A sample-and-hold current measurement integrated circuit for neural recording

This paper describes a new differential sample-and-hold technique of current measurement for neural probing. The design utilizes bottom plate sampling (BPS) and T-transmission switches to mitigate signal coupling and a differential sample-and-hold technique to reduce charge injection and clock feed through. The circuit was fabricated in a 0.35?µm CMOS process and tested using different input loads to model the electrochemical properties of the microelectrode. Test results matched closely with the simulation results, proving that the concept of the sample-and-hold current measurement circuit is valid for neural probing.     

10 /spl Omega/ 370 V high voltage switches for line circuit application

The authors describe the integration of 8 high-voltage switches together with their low-voltage polygate CMOS control logic in an 18-pin package, the HVX chip. This custom IC is intended to be used as a switching cross-point between the subscriber line and circuit equipment in digital telephony. The high-voltage DMOS is processed in a dielectrically isolated substrate, and allows the switches to have both terminals floating with respect to the low-voltage circuitry. A novel control circuit guarantees that the switch status will be defined under all circumstances.     

A 1.5-V 50-MHz pseudodifferential CMOS sample-and-hold circuit with low hold pedestal

This paper describes the design strategy and implementation of a low-voltage pseudodifferential double-sampled timing-skew-insensitive sample-and-hold (S/H) circuit with low hold pedestal based on the Miller-effect scheme. The S/H circuit employs bootstrapped switches in order to facilitate low voltage operation. The design considerations for each building block are described in detail. The S/H circuit has been designed using a 0.35-/spl mu/m 2P4M CMOS technology and experimental results are presented. The 1.5-V S/H circuit operates up to a sampling frequency of 50 MHz with less than -54.6 dB of total harmonic distortion for an input sinusoidal amplitude of 0.8 V/sub pp/. In these conditions, a differential hold pedestal of less than 0.8 mV, 1.6 ns acquisition time at 0.8-V step input, and 0.8 V/sub pp/ full-scale differential input range are achieved.