Noise associated with interdigitated gate structures in RFsubmicron MOSFETs

CMOS technologies have gained considerable attention and have raised expectations for employment in RF transceivers. The shrinkage of the MOSFET device dimensions along with the relatively wide gate electrode devices needed to accommodate RF applications lead to reconsideration of the noise properties of submicron MOSFETs. In this paper, we present the noise properties associated with interconnect resistors of an interdigitated structure and the resulting noise source (strong function of the number of fingers) is evaluated against the other noise sources present in the device such as channel thermal noise, induced gate noise, and resistive gate voltage noise. Short channel effects have been taken into account for the evaluation of these noise sources and two-port analysis performed in order to calculate minimum noise figure and optimum input resistance for noise matching     

Effects of gate structures on the RF performance in PD SOI MOSFETs

The radio-frequency (RF) performance of PD silicon-on-insulator metal oxide semiconductor field effect transistors with T-gate and H-gate structures has been investigated. Our measurement shows that H-gate devices have larger cutoff frequency and smaller minimum noise figure than T-gate devices. This improved RF performance in H-gate devices can be explained mainly by the enhancement of transconductance resulting from the gate extension induced inversion charges and the low gate resistance. We conclude that the H-gate structure is superior to the T-gate structure for the design of the low-noise amplifier (LNA).     

Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness

In this paper, we use statistical three-dimensional (3-D) simulations to study the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs. The line edge roughness is introduced using a Fourier synthesis technique based on the power spectrum of a Gaussian autocorrelation function. In carefully designed simulation experiments, we investigate the impact of the rms amplitude /spl Delta/ and the correlation length /spl Lambda/ on the intrinsic parameter fluctuations in well scaled, but simple devices with fixed geometry as well as the channel length and width dependence of the fluctuations at fixed LER parameters. For the first time, we superimpose in the simulations LER and random discrete dopants and investigate their relative contribution to the intrinsic parameter fluctuations in the investigated devices. For particular MOSFET geometries, we were able to identify the regions where each of these two sources of intrinsic parameter fluctuations dominates.     

Metal gate work function engineering on gate leakage of MOSFETs

We present a systematic study of tunneling leakage current in metal gate MOSFETs and how it is affected by the work function of the metal gate electrodes. Physical models used for simulations were corroborated by experimental results from SiO/sub 2/ and HfO/sub 2/ gate dielectrics with TaN electrodes. In bulk CMOS results show that, at the same capacitance equivalent oxide thickness (CET) at inversion, replacing a poly-Si gate by metal reduces the gate leakage appreciably by one to two orders of magnitude due to the elimination of polysilicon gate depletion. It is also found that the work function /spl Phi//sub B/ of a metal gate affects tunneling characteristics in MOSFETs. It is particularly significant when the transistor is biased at accumulation. Specifically, the increase of /spl Phi//sub B/ reduces the gate-to-channel tunneling in off-biased n-FET and the use of a metal gate with midgap /spl Phi//sub B/ results in a significant reduction of gate to source/drain extension (SDE) tunneling in both n- and p-FETs. Compared to bulk FET, double gate (DG) FET has much lower off-state leakage due to the smaller gate to SDE tunneling. This reduction in off-state leakage can be as much as three orders of magnitude when high-/spl kappa/ gate dielectric is used. Finally, the benefits of employing metal gate DG structure in future CMOS scaling are discussed.     

Comparison of threshold modulation in narrow MOSFETs with different isolation structures

The threshold shifts of narrow MOSFETs with different oxide structures are calculated explicitly using numerical means. It is found that the semirecessed device with vertical-field oxide step and vertical side wall appears to be a more suitable candidate for very-large-scale integration (VLSI) if the characteristic of threshold change vs gate width is taken into consideration.     

Inverse-narrow-width effect of deep sub-micrometer MOSFETs with LOCOS isolation

The effect of scaling down the channel width on the threshold voltage of deep submicron MOSFETs with LOCOS isolation has been investigated. Previous results, obtained from 1 μm technology and above, show an increase in threshold voltage as the width is reduced. However, in deep submicron technology, oxide thickness is scaled-down and channel doping is increased to avoid punchthrough and maintain a sufficiently high threshold voltage. This results in a threshold voltage reduction as channel width is scaled-down—the so called Inverse-Narrow-Width-Effect (INWE). The trend is explained through dopant redistribution and is verified by both experiment and process simulation. Lastly, a new narrow width threshold voltage model is proposed to account for the dopant redistribution effect.     

Photovoltaic gate biasing edge effect in GaAs MESFETs

A new effect in planar GaAs MESFETs, whereby a sharp increase in optical gain at the transistor edges occurs, is reported for the first time. This gain effect only appears when a large resistor is inserted in series with the gate, to produce the conditions for photovoltaic gate biasing. The mechanism for increased gain at the edges is suggested to be due to carrier photogeneration in the substrate that is subsequently collected by the gate. Application in the area of X-Y addressable transistor array imagers is proposed.<>     

Gate length effect on the RTS noise amplitude in SOI MOSFETs

The Random Telegraph Signal (RTS) noise amplitude in Silicon-on-Insulator MOSFETs is studied as a function of the gate length, by adding a second transistor in series. Different types of behavior can be distinguished, pointing toward a different origin of the related trapping centers. It is shown that in linear operation, the RTS amplitude and the corresponding low-frequency noise peak magnitude normally scales with 1/L. However, an increase with device length can also be found when the noise peaks of two RTSs add up. For RTSs occurring in the saturation regime, a complete elimination is observed for larger Ls, in support of the supposed film-related origin     

Characterization and modeling of edge direct tunneling (EDT)leakage in ultrathin gate oxide MOSFETs

This paper examines the edge direct tunneling (EDT) of electron from n⁺ polysilicon to underlying n-type drain extension in off-state n-channel MOSFETs having ultrathin gate oxide thicknesses (1.4-2.4 nm). It is found that for thinner oxide thicknesses, electron EDT is more pronounced over the conventional gate-induced-drain-leakage (GIDL), bulk band-to-band tunneling (BTBT) and gate-to-substrate tunneling, and as a result, the induced gate and drain leakage is better measured per unit gate width. A physical model is for the first time derived for the oxide field E_OX at the gate edge by accounting for electron subband in the quantized accumulation polysilicon surface. This model relates E_OX to the gate-to-drain voltage, oxide thickness, and doping concentration of drain extension. Once fox is known, an existing DT model readily reproduces EDT I-V consistently and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well     

Analysis of gate shot noise in MOSFETs with ultrathin gate oxides

The impact of gate shot noise associated with gate leakage current in MOSFETs is studied by means of analytical models and numerical device simulation. The effects of shot noise on the main two-port noise parameters (minimum noise figure, equivalent noise resistance, and optimum source admittance) and their dependence on oxide thickness and on the level of tunneling leakage current are analyzed.     

Dependence of hot-carrier immunity on channel length and channelwidth in MOSFETs with N2O-grown gate oxides

The authors report on the channel length (0.5-5 μm) and width (0.6-10 μm) dependence of hot-carrier immunity in n-MOSFETs with N ₂O-grown gate oxides (~85 Å). While channel hot-carrier-induced degradation has a strong dependence on channel geometry in control devices, the degradation and its channel geometric dependences are greatly suppressed in devices with N₂O-gate oxides. Under Fowler-Nordheim injection stress, the control device shows an enhanced degradation with decreasing channel length and increasing channel width, whereas N₂O device exhibits a less dependence on channel geometry     

Comprehensive separate extraction of parasitic resistances in MOSFETs considering the gate bias-dependence and the asymmetric overlap length

Parasitic resistances cause degradation of transconductance (g_m), cutoff frequency (f_T), current driving capability, and long term reliability of MOSFETs. We report a comprehensive extraction of parasitic resistance components in MOSFETs for the contact, the spreading current path, and the lightly doped drain region caused by the process, structure, and degradation. We considered the gate bias (V_GS)-dependence and the asymmetric overlap length (L_ov,SD) in the source and drain. We report systematically integrated extraction technique combined with the channel resistance method, the transfer length method, the dual-sweep combinational transconductance technique, the open drain method, and the parasitic junction current method. V_GS-independent resistances were separated to be R_Se = 6.8–6.9 Ω, R_De = 7.4–7.5 Ω, R_SUB = 7.4–7.6 Ω, R_So = 1.8–2.1 Ω, and R_Do = 3.2–3.5 Ω for MOSFETs with and at W/L = 50 μm/0.27 μm. V_GS-dependent intrinsic resistances are obtained to be R_Si = 1.9–4.4 Ω, R_Di = 1.4–3.2 Ω for the same devices. The V_GS-dependent intrinsic channel resistance (R_CH) is extracted with different channel lengths for MOSFETs with L = 0.18 μm/0.27 μm/0.36 μm.     

Improvement of performance deviation and productivity of MOSFETs with gate length below 30 nm by flash lamp annealing

The impact of new flash lamp annealing (FLA) technology, which both minimizes diffusion to yield a shallow junction and realizes low sheet resistivity, is investigated based on MOSFET fabrication and computer simulations. Productivity can be improved since FLA makes it possible to employ higher acceleration energy ion implantation and higher throughput. The MOSFET performance can be improved and its deviation suppressed by using FLA. In analyzing MOSFETs with gate length (L) of 20 nm by computer simulations, it was clarified that in contrast to spike annealing, the shallow junction realized by applying FLA to pMOSFET fabrication enabled the suppression of |I/sub off/| with a low channel surface dopant concentration. This provided a higher mobility value and a higher drive current. FLA is promising for improving the performance and productivity of sub-30-nm gate-length MOSFETs.     

Modeling for reduced gate capacitance of nanoscale MOSFETs

As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate capacitance, due to the increasing importance of the carrier distributions in the polysilicon electrodes. For the first time, based on least-squares curve fit, we quantitatively explore the impact of quantum mechanics effects in polysilicon gate region on gate capacitance. Comparing the theoretical curves with an extensive set of simulation ones has validated this model.     

Effect of gate impurity concentration on inversion-layer mobility in MOSFETs with ultrathin gate oxide layer

In this paper, the influence of poly-Si-gate impurity concentration, N/sub poly/, on inversion-layer electron mobility is experimentally investigated in MOSFETs with ultrathin gate oxide layer. The split capacitance-voltage C-V method is modified to directly measure an effective mobility, paying attention to both 1) accurate current-voltage I-V and capacitance-voltage (C-V) measurements with high gate leakage current and 2) correct surface carrier density, N/sub s/, estimation at a finite drain bias. It is demonstrated that the mobility in ultrathin gate oxides becomes low significantly for highly doped gate, strongly suggesting the contribution of remote Coulomb scattering due to the gate impurities, which is quantitatively discriminated from that of Coulomb scattering due to substrate impurities and interface states. It is also found that the mobility lowering becomes significant rapidly at T/sub ox/ of 1.5 nm or less. The mobility-lowering component is weakly dependent on N/sub s/, irrespective of N/sub poly/, which cannot be fully explained by the existing theoretical models of remote impurity scattering.     

Submicrometre gate length scaling of inversion channelheterojunction field effect transistor

The scaling to 0.5 μm of the inversion channel HFET with a single strained InGaAs quantum well is described. A unity current gain frequency of 40 GHz, g_m=205 mS/mm and V_TH=-0.34 V have been obtained for 0.5×100 μm² devices. For shorter gate lengths, threshold shifts are sizeable so that in order to scale further, modifications to the growth and processing are required     

The effect of MOS Channel length on the performance of insulated gate transistors

The effect of MOS channel length on n-channel 600-V insulated gate transistors (IGT's) is evaluated. When the channel length was decreased from 1.9 to 0.8 µm, a doubling of the forward conduction current was measured at a forward drop of 2 V for IGT's with a turn-off time of 2 µs. Also, a better forward drop versus turnoff time tradeoff were observed. However, a 25-50-percent decrease in latching current was measured for the short-channel devices under dynamic switching conditions at 150°C.     

Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance

Using a novel process flow, we managed to cointegrate several devices on the same wafer; single gate (SG), ground plane (GP), perfectly aligned double gate (DG), misaligned DG and oversized back-gate DG. This paper reports the experimental evaluation of the gate architectures influence on the performance of silicon-on-insulator MOSFETs. DG MOSFETs, with gate lengths down to 40 nm, are experimentally compared to SG and GP MOSFETs. Short-channel effect (SCE) control, static performance and mobility are quantified for each architecture. When compared to SG and GP transistors, the DG transistor shows the best SCE control and performance as predicted by simulations. Gate coupling is demonstrated to be a sensitive and a nondestructive method to evaluate the real on-wafer alignment. Using this method, we report an experimental analysis of gate misalignment influence on DG MOSFETs' performance and SCE. It is found that misalignment primarily affects the subthreshold parameters due to an electrostatic control loss. The DG MOSFET with a slightly oversized back gate (10 nm on each side of the top gate) is a promising solution, if a 10% loss in dynamic performance can be tolerated.     

A comparative study on electrothermal characteristics of nanoscale multiple gate MOSFETs

Multiple-gate (MG) MOSFETs are promising candidates for next-generation integrated circuits technology. This paper presents the electrothermal characterization of three-type nanoscale MG MOSFETs, i.e., Π-gate, quadruple-gate (QG), and Ω-gate MOSFETs. Meanwhile, the temperature distribution of a real Ω-gate MOSFET with gradual channel width is also studied. Finite difference method (FDM) is adopted to solve the 3-D time-dependent heat conduction equations. The simulation results of the steady-state temperature distribution are validated against the commercial software COMSOL. Moreover, the transient temperature response of MG MOSFETs to different waveforms are also captured and compared.     

Measuring the effective channel length of MOSFETs

Eleven measurement methods are outlined, and their assumptions are examined. The methods are analyzed, critiqued, and compared. Recommendations are made as to which methods are best under various conditions