Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget

We report on a top-down complementary metal oxide semiconductor (CMOS) compatible fabrication method of ultra-high density Si nanowire (SiNW) arrays using a time multiplexed alternating process (TMAP) with low temperature budget. The flexibility of the fabrication methodology is demonstrated for curved and straight SiNW arrays with different shapes and levels. Ultra-high density SiNW arrays with round or rhombic cross-sections diameters as low as 10 nm are demonstrated for vertical and horizontal spacing of 60 nm. The uniqueness of the technique, which achieves several advantages such as bulk-Si processing, low-thermal budget, and wide process window makes this fabrication method suitable for a very broad range of applications such as nano-electro-mechanical systems (NEMS), nano-electronics and bio-sensing.     

Characterization of ultra-thin SiO2 by capacitance-voltage and charge pumping measurements

In this paper, we present results on electrical measurements of ultra thin SiO₂ layers (from 3.5 nm down to 1.7 nm), used as gate dielectric in metal-oxide-semiconductors (MOS) devices. Capacitance-voltage (C-V) measurements and simulations on MOS capacitors have been used for extracting the electrical oxide thickness. The SiO₂/Si interface and oxide quality have been analyzed by charge pumping (CP) measurements. The mean interface traps density is measured by 2-level CP, and the energy distribution within the semiconductor bandgap of these traps are investigated by 3-level charge pumping measurements. A comparison of the energy distribution of the SiO₂/Si interface traps is made using classical and quantum simulations to extract the surface potential as a function of the gate signal. When the gate oxide thickness <3.5 nm, we prove that it is mandatory to take into account the quantum effects to obtain a more accurate energy distribution of the SiO₂/Si interface traps. We also explain the increase of the apparent interface traps density measured by 2-levels CP with the increase of the oxide thickness, for transistors made from the same technological process.     

Electrical transport properties in electroless-etched Si nanowire field-effect transistors

We report the electrical transport of the Si nanowires in a field-effect transistor (FET) configuration, which were synthesized from B-doped p-type Si(1 1 1) wafer by an aqueous electroless etching method based on the galvanic displacement of Si by the reduction of Ag⁺ ions on the wafer surface. The FET performance of the as-synthesized Si nanowires was investigated and compared with Ag-nanoparticles-removed Si nanowires. In addition, high-k HfO₂ gate dielectric was applied to the Si nanowires FETs, leading to the enhanced performance such as higher drain current and lower subthreshold swing.     

Enhanced electrical properties of nominally undoped Si/SiGe heterostructure nanowires grown by molecular beam epitaxy

Electrical properties of epitaxial single-crystalline Si/SiGe axial heterostructure nanowires (NWs) on Si〈1 1 1〉 substrate were measured by contacting individual NWs with a micro-manipulator inside an scanning electron microscope. The NWs were grown by incorporating compositionally graded Si_1−xGe_x segments of a few nm thicknesses in the Si NWs by molecular beam epitaxy. The I-V characteristics of the Si/SiGe heterostructure NWs showed Ohmic behavior. However, the resistivity of a typical heterostructure NW was found to be significantly low for the carrier concentration extracted from the simulated band diagram. Similarly grown pure Si and Ge NWs showed the same behavior as well, although the I-V curve of a typical Si NW was rectifying in nature instead of Ohmic. It was argued that this enhanced electrical conductivities of the NWs come from the current conduction through their surface states and the Ge or Si/SiGe NWs are more strongly influenced by the surface than the Si ones.     

Integration of SiC-1D nanostructures into nano-field effect transistors

We report on the integration and the electrical transport properties of silicon carbide-based one-dimensional nanostructures into field effect transistors. Different kinds of SiC-based 1D nanostructures have been used: 3C– and 4H–SiC nanowires obtained by a plasma etching process, Si–SiC core–shell nanowires and SiC nanotubes both obtained by a carburization route of silicon nanowires.     

Optimization of sub-0.1-μm offset Γ-shaped gate MHEMTs for millimeter-wave applications

We examine the effects of device scaling in both vertical and lateral dimensions for the metamorphic high electron mobility transistors (MHEMTs) on the DC and millimeter-wave electrical performances by using a hydrodynamic transport model. The well-calibrated hydrodynamic simulation for the sub-0.1-μm offset Γ-gate In_0.53Ga_0.47As/In_0.52Al_0.48As MHEMTs shows a reasonable agreement with the electrical characteristics measured from the fabricated 0.1 μm devices. We have calibrated all the parameters using the measurement data with various physical considerations to take into account the sophisticated carrier transport physics in sub-0.1-μm devices. Being simulated with these calibrated parameters, the optimum device performance is obtained at a source-drain spacing of 2 μm, a gate length of 0.05 μm, a barrier thickness of 10 nm and a channel thickness of 12 nm.     

Growth of Nb-catalysed GaN nanowires

GaN nanowires have been successfully synthesized on Si(1 1 1) substrate by ammoniating Ga₂O₃ films at 950 °C. The structure and morphology of GaN nanowires are characterized by X-ray diffraction, scanning electron microscopy, field-emission transmission electron microscope and X-ray photoelectron spectroscopy. The results show that the synthesized nanowires are single-crystal hexagonal wurtzite GaN with diameters ranging from 50 to 100 nm and lengths up to several microns. Finally, the growth mechanism of GaN nanowires is explored.     

MOCVD fluorine free WSix metal gate electrode on high-k dielectric for NMOS technology

We report material and electrical properties of tungsten silicide metal gate deposited on 12 in. wafers by chemical vapor deposition (CVD) using a fluorine free organo-metallic (MO) precursor. We show that this MOCVD WSi_x thin film deposited on a high-k dielectric (HfSiO:N) shows a N+ like behavior (i.e. metal workfunction progressing toward silicon conduction band). We obtained a high-k/WSi_x/polysilicon “gate first” stack (i.e. high thermal budget) providing stable equivalent oxide thickness (EOT) of ∼1.2 nm, and a reduction of two decades in leakage current as compared to SiO₂/polysilicon standard stack. Additionally, we obtained a metal gate with an equivalent workfunction (EWF) value of ∼4.4 eV which matches with the +0.2 eV above Si midgap criterion for NMOS in ultra-thin body devices.     

Investigation of luminescence properties of ZnO nanowires at room temperature

The controllable growth processes of ZnO nanowires by evaporation of metal zinc with high purity and its luminescence properties have been investigated in detail. Firstly, the power of ZnO nanowires with high yield and homogeneous dimension was synthesized using the special quartz boat at 600 °C. Then, the oriented ZnO nanowires with about 20 nm diameter were synthesized by using a 90 nm-thick layer of ZnO nanocrystals on the Si substrate as the seed layer. Both fabrication processes are repeatable and no catalysts are necessary. Finally, photoluminescence (PL) spectroscopy for ZnO nanowires using an He-Cd laser line of 325 nm as the excitation source were measured at room temperature and both samples showed a sharp strong ultraviolet (UV) near-band edge emission. However, different UV peak positions (385 nm for ZnO nanowire powder, 377 nm for ZnO nanowire array) can be observed. The size confinement effect for excitons and carriers is proposed to explain the blue shift of the near-band edge emission with decreasing size and the native defects are responsible for the green emission.     

Electrical property dependence on thickness and morphology of nanocrystalline diamond thin films

In this study, we investigate the influence of nanocrystalline diamond (NCD) thin film morphology and thickness on their electrical properties. NCD films are grown on p-type Si substrates with varied thicknesses from 250 to 788 nm. Electrical contacts are formed from combination of Ti/Au metal layers (100 nm thick each). The I-V and breakdown field measurements are used to analyze the electrical properties of metal/NCD/Si sandwich structure. In addition, NCD films are analyzed by scanning electron microscopy and Raman spectroscopy for better interpretation of the I-V measurements.     

Electrical properties of Pt interconnects for passive crossbar memory arrays

We report on the fabrication and the electrical characterization of platinum interconnects for novel non-volatile memory technologies. These nanowires present an important and essential contribution to the deep nanometer scaling of alternative architectures beyond CMOS, e.g. nanocrossbar arrays with resistance switching junctions. The nanowires, which have a thickness of 25 nm and a width ranging from 200 nm down to 40 nm, were patterned using electron beam direct writing. They were deposited by UHV electron beam evaporation in combination with a lift-off process.The electrical characteristic is increasingly affected by the contribution of surface effects like scattering at grain boundaries and scattering at the surfaces as the wire dimensions become smaller. With decreasing width of the platinum wire an increasing resistivity was observed, which is consistent with the theories of Fuchs-Sondheimer and Mayadas-Shatzkes. Our studies have shown that the investigated structures possess a high stability concerning the operational current densities up to 4 × 10⁷ A/cm², and an additional annealing step results in an improvement of the electrical wire properties, which is explained by a higher quality of the grain boundaries and side walls.     

Titanium-aluminum oxynitride (TAON) as high-k gate dielectric for sub-32 nm CMOS technology

High-k insulators for the next generation (sub-32 nm CMOS (complementary metal-oxide-semiconductor) technology), such as titanium-aluminum oxynitride (TAON) and titanium-aluminum oxide (TAO), have been obtained by Ti/Al e-beam evaporation, with additional electron cyclotron resonance (ECR) plasma oxynitridation and oxidation on Si substrates, respectively. Physical thickness values between 5.7 and 6.3 nm were determined by ellipsometry. These films were used as gate insulators in MOS capacitors fabricated with Al electrodes, and they were used to obtain capacitance-voltage (C-V) measurements. A relative dielectric constant of 3.9 was adopted to extract the equivalent oxide thickness (EOT) of films from C-V curves under strong accumulation condition, resulting in values between 1.5 and 1.1 nm, and effective charge densities of about 10¹¹ cm⁻². Because of these results, nMOSFETs with Al gate electrode and TAON gate dielectric were fabricated and characterized by current-voltage (I-V) curves. From these nMOSFETs electrical characteristics, a sub-threshold slope of 80 mV/dec and an EOT of 0.87 nm were obtained. These results indicate that the obtained TAON film is a suitable gate insulator for the next generation (MOS) devices.     

Molecular beam deposition of LaAlO3 on silicon for sub-22 nm CMOS technological nodes: Towards a perfect control of the oxide/silicon heterointerface

This work reports on the development of thin amorphous LaAlO₃ (LAO) layers on Si(0 0 1) for their integration as gate oxide in sub-22 nm CMOS technologies. The crucial influence of the Si surface preparation is highlighted and an optimized surface preparation procedure is proposed. An unexpected interface reaction during Rapid Thermal Annealing is also evidenced, and an explanation attempt of the origin of this reaction, involving surface contaminants, is proposed.     

Interfacial transition regions at germanium/Hf oxide based dielectric interfaces: Qualitative differences between non-crystalline Hf Si oxynitride and nanocrystalline HfO2 gate stacks

The contribution from a relatively low-K SiON (K ∼ 6) interfacial transition region (ITR) between Si and transition metal high-K gate dielectrics such as nanocrystalline HfO₂ (K ∼ 20), and non-crystalline Hf Si oxynitride (K ∼ 10-12) places a significant limitation on equivalent oxide thickness (EOT) scaling. This limitation is equally significant for metal-oxide-semiconductor capacitors and field effect transistors, MOSCAPs and MOSFETs, respectively, fabricated on Ge substrates. This article uses a novel remote plasma processing approach to remove native Ge ITRs and bond transition metal gate dielectrics directly onto crystalline Ge substrates. Proceeding in this way we identify (i) the source of significant electron trapping at interfaces between Ge and Ge native oxide, nitride and oxynitride ITRs, and (ii) a methodology for eliminating native oxide, or nitride IRTs on Ge, and achieving direct contact between nanocrystalline HfO₂ and non-crystalline high Si₃N₄ content Hf Si oxynitride alloys, and crystalline Ge substrates. We then combine spectroscopic studies, theory and modeling with electrical measurements to demonstrate the relative performance of qualitatively different nanocrystalline and non-crystalline gate dielectrics for MOS Ge test devices.     

Cathodoluminescence characterization of β-SiC nanowires and surface-related silicon dioxide

The main goal of our study is to prepare and to understand the properties of cubic SiC nanowires (NWs) and to characterize its native silicon dioxide. The wires, with diameters ranging from 10 nm to 2 μm, have been prepared by a CVD process on Si (0 0 1) substrates, using CO as the carbon source and Ni as the catalyst. A structural and optical analysis, by means of TEM, micro-Raman and cathodoluminescence (CL) spectroscopy, has been performed. Two sets of samples have been studied, labelled A and B, which differ for growth process conditions. Set A showed two broad CL peaks. Set B showed a much weaker CL emission. This difference has been explained by means of TEM investigation and micro-Raman spectra: set A shows a thick amorphous silicon dioxide layer on the wire surface, whereas set B shows a thin or absent oxide layer. Consequently, the nature of the CL emission has to be ascribed mainly to oxide-related recombination.     

Drain current saturation at high drain voltage due to pinch off instead of velocity saturation in sub-100 nm metal-oxide-semiconductor transistors

Older MOS transistor theory pointed out that drain current saturation is due to pinch off for MOS transistors with large gate length and due to velocity saturation for MOS transistors with sub-micron gate length. Newer quasi-ballistic transport theory pointed out that there is no velocity saturation. In this letter, we report our experimental observation that for sub-100 nm MOS transistors, there is no strong velocity saturation in the traditional sense and current saturation is mainly due to pinch off.     

Study of CVD nanowire high-k metal interface quality for interconnect level MOS devices

We report a study of low temperature gate stack on silicon nanowires compatible with Back-End-Of-Line (BEOL) integration. The same gate stack is deposited at low temperature on Si nanowires obtained thanks to either Chemical Vapor Deposition (CVD) or Selective Epitaxial Growth (SEG) in patterns. Gate stack characterization on CVD nanowires (NWs) shows low leakages and good agreement with simulated curves without interface states. A dramatic decrease of the capacitance in accumulation region and faster electron generation are observed and attributed to NW defects. In contrast, SEG devices reveals lower capacitance decrease with frequency but higher interface state density of about 10¹³ cm⁻².     

Ultrathin CdSe nanowire field-effect transistors

We report the fabrication, and electrical and optical characterization, of solution-liquid-solid (SLS) grown CdSe nanowire field-effect transistors. Ultrathin nanowires (7–12 nm diameters) with lengths between 1 μm and 10 μm were grown by the SLS technique. Al-CdSe-Al junctions are then defined over oxidized Si substrate using photolithography. The nanowires, which were very resistive in the dark, showed pronounced photoconductivity even with a visible light source with resistance decreasing by a factor of 2–100 for different devices. Field-effect devices fabricated by a global backgating technique showed threshold voltages between −7.5 V and −2.5 V and on-to-off channel current ratios between 10³ and 10⁶ at room temperature. Channel current modulation with gate voltage is observed with the current turning off for negative gate bias, suggesting unintentional n-type doping. Further, optical illumination resulted in the loss of gate control over the channel current of the field-effect transistor.     

Self-aligned n-channel GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using HfO2 and silicon interface passivation layer: Post-metal annealing optimization

In this work, using Si interface passivation layer (IPL), we demonstrate n-MOSFET on p-type GaAs by varying physical-vapor-deposition (PVD) Si IPL thickness, S/D ion implantation condition, and different substrate doping concentration and post-metal annealing (PMA) condition. Using the optimized process, TaN/HfO₂/GaAs n-MOSFETs made on p-GaAs substrates exhibit good electrical characteristics, equivalent oxide thickness (EOT) (∼3.7 nm), frequency dispersion (∼8%) and high maximum mobility (420 cm²/V s) with high temperature PMA (950 °C, 1 min) and good inversion.     

Thermal annealing effect on electrical properties of metal nitride gate electrodes with hafnium oxide gate dielectrics in nano-metric MOS devices

Electrical properties of hafnium oxide (HfO₂) gate dielectric with various metal nitride gate electrodes, i.e., tantalum nitride (TaN), molybdenum nitride (MoN), and tungsten nitride (WN), were studied over a range of HfO₂ thicknesses, e.g., 2.5-10 nm, and post-metal annealing (PMA) temperatures, e.g., 600 °C to 800 °C. The work function of the nitride gate electrode was dependent on the material and the post-metal annealing (PMA) temperature. The scanning transmission electron microscopy technique is used to observe the effect of PMA on the interfacial gate dielectric thickness. After high-temperature annealing, the metal nitride gates were suitable for NMOS. At the same PMA temperature, the oxide-trapped charges increased and the interface state densities decreased with the increase of the HfO₂ thickness for TaN and WN gate electrodes. However, for MoN gate electrode the interface state density is almost independent of film thickness. Therefore, dielectric properties of the HfO₂ high-k film depend not only on the metal nitride gate electrode material but also the post-metal annealing condition as well as the film thickness. During constant voltage stress of the MOS capacitors, an increase in the time-dependent gate leakage current is also observed.