Strain Engineering in Highly Mismatched SiGe/Si Heterostructures

In this work we present an innovative approach to realise coherent, highly-mismatched 3-dimensional heterostructures on substrates patterned at the micrometre-scale. The approach is based on the out-of-equilibrium deposition of SiGe alloys graded at an exceptionally shallow grading rate (GR) of 1.5% µm⁻¹ by low energy plasma enhanced chemical vapour deposition (LEPECVD). Fully coherent SiGe/Si crystals up to 6 µm in width were achieved as confirmed by defect etching and transmission electron microscopy (TEM) analyses. The experimental results are supported by calculations of the energy for dislocation formation which indicate that elastic relaxation is energetically favoured over plastic relaxation in the narrower heterostructures. X-ray diffraction measurements show that the SiGe crystals are strain-free irrespective of the stress relieving mechanism which changes from elastic to plastic by increasing their width. The impact of dislocations on the SiGe crystal quality is analysed by comparing the width of X-ray diffraction peaks as a function of the heterostructure size.     

SiGe技术、器件及其应用

SiGe技术和SOI技术将是21世纪硅集成的重要技术,它们相互补充,改善晶体管的速度 和性能。本文介绍了SiGe技术、器件和应用。     

Laser annealing of SiGe and Ge based devices

The integration of laser annealing in SiGe and Ge based MOS devices is investigated by means of numerical simulations. Our simulation code is based on two modules: the former simulates the interaction between the laser light and the transistor structure to estimate the heating, the latter simulates heat diffusion, phase changes and material redistribution under irradiation. The model is calibrated in the case of different atomic species (namely Si, Ge and common dopant impurities), considering the thermal properties of the materials and the impurity depending diffusivity in the solid, liquid and interfacial region. We present several simulation results obtained by varying materials, implanted impurity profiles and geometry of the CMOS-like structures. With the support of the simulation results we discuss the possible perspectives of the excimer laser annealing application to the fabrication of post-Si CMOS devices. In particular, we show that by using Ge and SiGe materials the process window for a melting process is larger with respect to the case of traditional Si based devices.     

SiGe PMOSFET性能模拟

由于受热力学基本定律的限制 ,Si集成电路技术的发展已经日益接近极限 ,而 Si Ge材料的引入使得占据小于 1GHz频段的 Si产品可以进一步覆盖 2～ 30 GHz的 RF和无线通信市场。根据前人的材料研究工作 ,在普通 Si器件性能模拟的基础上 ,进一步研究长沟应变 Si Ge器件的模拟 ,引入了插值所得的近似因子以修正 silvaco中隐含的 Si Ge能带模型和迁移率参数。然后依据修正后的模型对 Si Ge PMOS进行更为精确的二维模拟     

B在SiGe中的应变补偿作用

用超高真空化学气相淀积方法生长出不同硼(B)掺杂浓度的应变SiGe合金材料，研究了B对SiGe合金的应变补偿作用. 结果表明，B的掺入使SiGe的应变减小，B对Ge的应变补偿率为7.3，即平均掺入1个B原子可以补偿7.3个Ge原子引起的应变. 同时获得B的晶格收缩系数为6.23e-24cm3/atom.     

SiGe:C HBT transit time analysis based on hydrodynamic modeling using doping, composition and strained dependent SiGe:C carriers mobility and relaxation time

A global additional uniaxial stress ranging from −1 GPa to 1 GPa along different directions has been applied to SiGe HBTs in order to improve the high-frequency performance of these devices. Two transistors have been investigated: a slow one (peak f_T = 110 GHz) and a fast one (peak f_T = 750 GHz). The results from full-band Monte Carlo simulations show that the cutoff frequency of both devices can be improved by more than 30 percent under suitable stress conditions. A spherical-harmonics-expansion simulator is also used to investigate the spatial origin of this improvement, where it is found that the transit times are reduced in all regions (base, collector, emitter).     

长波长锗硅光电探测器的材料生长研究

介绍了应变SiGe层的特性,包括SiGe应变层临界厚度与Ge组分的关系,能带变窄,折射率增加以及应变SiGe层的亚稳态特性.然后从材料生长方面入手,提出了4种改善长波长锗硅光电探测器性能的方案,包括采用生长缓冲层来减小位错的方法、生长高组分表面起伏多量子阱的方法和生长Ge岛超晶格的方法,随之给出了相关的实验结果,并对这4种方案进行了分析.最后对上述内容进行小结,并对Ge量子点共振腔增强型光电探测器的应用前景进行了探讨与展望.     

Ge组分对SiGe HBT主要电学特性的影响

采用SiGe异质结结构提高晶体管的性能,分析了Ge对器件电流增益和频率特性提高的物理机制.综合考虑了Si1-xGex薄膜的稳定性、工艺特点和器件结构对Ge含量以及分布的要求和Ge组分的设计及其对器件电学特性的影响.从理论上推算了SiGe HBT的β和fT等主要特性参数,Ge的引入以及Ge的分布情况对提高这些参数有着显著的影响.Ge的引入对晶体管主要特性参数的提高使得SiGe HBT技术在微波射频等高频电子领域可以有更重要的应用前景.     

一种适合制作CMOS的SiGePMOSFET

在通常适合于制作埋沟 Si Ge NMOSFET的 Si/弛豫 Si Ge/应变 Si/弛豫 Si Ge缓冲层 /渐变 Ge组分层的结构上 ,制作成功了 Si Ge PMOSFET.这种 Si Ge PMOSFET将更容易与 Si Ge NMOSFET集成 ,用于实现 Si Ge CMOS.实验测得这种结构的 Si Ge PMOSFET在栅压为 3.5 V时最大饱和跨导比用作对照的 Si PMOS提高约 2倍 ,而与常规的应变 Si Ge沟道的器件相当     

改善SiGe HBTs热稳定性的Ge组分分布优化与设计

The impact of the three state-of-the-art germanium(Ge) profiles(box,trapezoid and triangular) across the base of SiGe heterojunction bipolar transistors(HBTs) under the condition of the same total amount of Ge on the temperature dependence of current gainβand cut-off frequency f_T,as well as the temperature profile,are investigated.It can be found that although theβof HBT with a box Ge profile is larger than that of the others,it decreases the fastest as the temperature increases,while theβof HBT with a triangular Ge profile is smaller than that of the others,but decreases the slowest as the temperature increases.On the other hand,the f_T of HBT with a trapezoid Ge profile is larger than that of the others,but decreases the fastest as the temperature increases,and the f_T of HBT with a box Ge profile is smaller than that of the others,but decreases the slowest as temperature increases.Furthermore,the peak and surface temperature difference between the emitter fingers of the HBT with a triangular Ge profile is higher than that of the others.Based on these results,a novel segmented step box Ge profile is proposed,which has modestβand f_T,and trades off the temperature sensitivity of current gain and cut-off frequency,and the temperature profile of the device.     

采用薄SiGe虚拟衬底制备应变Ge材料

This paper describes a method using both reduced pressure chemical vapor deposition （RPCVD） and ultrahigh vacuum chemical vapor deposition （UHVCVD） to grow a thin compressively strained Ge film. As the first step, low temperature RPCVD was used to grow a fully relaxed SiGe virtual substrate layer at 500 ℃ with a thickness of 135 nm, surface roughness of 0.3 nm, and Ge content of 77%. Then, low temperature UHVCVD was used to grow a high quality strained pure Ge film on the SiGe virtual substrate at 300 ℃ with a thickness of 9 nm, surface roughness of 0.4 nm, and threading dislocation density of - 10^5 cm^-2. Finally, a very thin strained Si layer of 1.5-2 nm thickness was grown on the Ge layer at 550 ℃ for the purpose of passivation and protection. The whole epitaxial layer thickness is less than 150 nm. Due to the low growth temperature, the two-dimensional layer-by-layer growth mode dominates during the epitaxial process, which is a key factor for the growth of high quality strained Ge films.     

Ge组分对SiGe HBT直流特性的影响

制作了基区Ge组分分别为0.20和0.23的多发射极指数双台面结构SiGe异质结双极型晶体管(HBT)。实验结果表明,基区Ge组分的微小增加,引起了较大的基极复合电流,但减小了总的基极电流,提高了发射结的注入效率,电流增益成倍地提高。Ge组分从0.20增加到0.23,HBT的最大直流电流增益从60增加到158,提高了约2.6倍。     

SiGe HBT器件的可靠性技术

介绍了SiGe异质结双极晶体管的特点,对SiGe异质结双极晶体管的物理机理进行了讨论,进而分析了影响其可靠性的各种可能因素,总结了目前SiGe HBT可靠性加速寿命试验方法,并进行了比较。     

微区中MBE共度生长SiGe/Si异质结构的应变和退火效应

报道了在Si衬底上微米尺寸的介质膜窗口中,采用分子束外延技术共度生长的Si0.8Ge0.2薄膜的应变及其退火特性. 实验表明,微区生长材料的这些特性,与同一衬底上无边界约束条件下生长的材料相比,有明显的不同.微米尺寸窗口中生长的SiGe/Si材料的应变与窗口尺寸有关,也和窗口的掩膜中的内应力有关.实验还表明,边缘效应对于微区中共度生长的SiGe/Si材料的热稳定性也有显著的影响.在3μm×3μm窗口中共度生长的Si0.8Ge0.2/Si异质结构材料,在950℃高温退火30min后,它的应变弛豫不大于4%.远小于同一衬底上非微区生长材料的应变弛豫.文章还对微区生长材料的这些特性成因进行了探讨.     

微区中MBE共度生长SiGe/Si异质结构的应变和退火效应

报道了在Si衬底上微米尺寸的介质膜窗口中,采用分子束外延技术共度生长的Si0.8Ge0.2薄膜的应变及其退火特性. 实验表明,微区生长材料的这些特性,与同一衬底上无边界约束条件下生长的材料相比,有明显的不同.微米尺寸窗口中生长的SiGe/Si材料的应变与窗口尺寸有关,也和窗口的掩膜中的内应力有关.实验还表明,边缘效应对于微区中共度生长的SiGe/Si材料的热稳定性也有显著的影响.在3μm×3μm窗口中共度生长的Si0.8Ge0.2/Si异质结构材料,在950℃高温退火30min后,它的应变弛豫不大于4%.远小于同一衬底上非微区生长材料的应变弛豫.文章还对微区生长材料的这些特性成因进行了探讨.     

调制掺杂层在SiGe PMOSFET中的应用

在普通Si器件性能模拟的基础上，详细研完了长沟应变SiGe器件的模拟，并进一步探讨了调制掺杂层的引入对器件性能(主要是跨导)的影响。在器件模拟过程中，采用隐含的SiGe材料和Si材料模型会得到与实际情况差别较大的结果。根据前人的材料研完工作，引入了插值所得的近似因子，以修正Silvaco中隐含的SiGe能带模型和迁移率参数。然后，依据修正后的模型对SiGe PMOS进行了更为精确的二维模拟，并验证了调制掺杂层的作用。     

Si间隔层对利用低温Si缓冲层生长高弛豫SiGe层的影响

利用低温生长Si缓冲层与Si间隔层相结合的方法生长高弛豫SiGe层,研究了Si间隔层在其中的作用. 利用化学腐蚀和光学显微镜，观察了不同外延层厚度处位错的腐蚀图样. 研究了不同温度下生长的Si间隔层对SiGe外延层中位错形成、传播及其对应变弛豫的影响. 结果表明Si间隔层的引入，显著改变了外延层中位错的形成和传播，进而使得样品表面形貌也呈现出较大的差异.     

Low-frequency noise analysis of Si/SiGe channel pMOSFETs

Low-frequency noise characteristics of 0.1 μm Si_1−xGe_x channel pMOSFETs were studied by numerical simulations in the framework of the carrier number fluctuation model as well as the correlated fluctuation in the mobility model. Simulation results predict that Si_1−xGe_x channel pMOSFETs could offer improved low-frequency noise performance as compared to the conventional bulk Si devices. This improvement in Si_1−xGe_x channel pMOSFETs could be attributed to less effective oxide trap density for noise generation due to the increasing separation of quasi-Fermi level and valence band edge at Si–SiO₂ interface by Ge-induced band offset.     

Applications and processing of SiGe and SiGe:C for high-speed HBT devices

The continued growth of high-speed-digital data transmission and wireless communications technology has motivated increased integration levels for ICs serving these markets. Further, the increasing use of portable wireless communications tools requiring long battery lifetimes necessitates low power consumption by the semiconductor devices within these tools. The SiGe and SiGe:C materials systems provide solutions to both of these market needs in that they are fully monolithically integratible with Si BiCMOS technology. Also, the use of SiGe or SiGe:C HBTs for the high-frequency bipolar elements in the BiCMOS circuits results in greatly decreased power consumption when compared to Si BJT devices.Either a DFT (graded Ge content across the base) or a true HBT (constant Ge content across the base) bipolar transistor can be fabricated using SiGe or SiGe:C. Historically, the graded profile has been favored in the industry since the average Ge content in the pseudomorphic base is less than that of a true HBT and, therefore, the DFT is tolerant of higher thermal budget processing after deposition of the base. The inclusion of small amounts of C (e.g. <0.5%) in SiGe is effective in suppressing the diffusion of B such that very narrow extremely heavily doped base regions can be built. Thus the f_T and f_max of a SiGe:C HBT/DFT are capable of being much higher than that of a SiGe HBT/DFT.The growth of the base region can be accomplished by either nonselective mixed deposition or by selective epitaxy. The nonselective process has the advantage of reduced complexity, higher deposition rate and, therefore, higher productivity than the selective epitaxy process. The selective epi process, however, requires fewer changes to an existing fabrication sequence in order to accommodate SiGe or SiGe:C HBT/DFT devices into the BiCMOS circuit.     

超高真空CVD对锗硅外延材料中锗分布的优化

对自行研制的超高真空化学气相外延设备(RHT/UHV/CVD SGE500)的气路系统进行了改进,使之能够生长出较好的Ge分布图形。利用X射线双晶衍射(DCXRD)和二次离子质谱(SIMS)测试技术,研究并优化了外延生长参量,最终得到了具有优化Ge分布的SiGe材料。