Investigation of voltage-swing effect and trap generation in high-k gate dielectric of MOS devices by charge-pumping measurement

Charge-pumping (CP) techniques with various rise and fall times and with various voltage swings are used to investigate the energy distribution of interface-trap density and the bulk traps. The charge pumped per cycle (Q_cp) as a function of frequency was applied to detect the spatial profile of border traps near the high-k gate dielectric/Si interface and to observe the phenomena of trap migration in the high-k dielectric bulk during constant voltage stress (CVS) sequence. Combining these two techniques, a novel CP technique, which takes into consideration the carrier tunneling, is developed to measure the energy and depth profiles of the border trap in the high-k bulk of MOS devices.     

On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors

According to the recent prediction made by the Semiconductor Industry Association (SIA) in International Technology Roadmap for Semiconductors (ITRS), the silicon technology will continue its historical rate of advancement with the Moore’s law for at least a couple of decades. With this trend, the silicon gate oxide will be scaled down to its physical limit in order to maintain proper control of the nanosize MOS transistors. This work reviews several critical issues of MOS gate dielectrics in the nanometer range.Although it was suggested that the conventional oxide can be scaled down, in principle, to two atomic layers of about 7 Å, this is not practically feasible because of the non-scalabilities of interface, trap capture cross-section, leakage current, and the statistical parameters of fabrication processes. Introducing a high-κ material can help solving most of the problems by using physically thicker high-κ gate dielectric films but several other reliability problems of the MOS devices rises. Being used in the extreme fine structure, the requirements for the material properties of the new high-κ are very stringent. Unfortunately, most of the high-κ materials are ionic metal oxides. This fundamental physics results in several undesirable instability issues when interfacing with silicon and with the CMOS processes. Bulk type thin oxynitride/high-κ stack could be a good solution for the coming technology nodes.     

Hot carrier effects in n-MOSFETs with SiO2/HfO2/HfSiO gate stack and TaN metal gate

Charge trapping and trap generation in field-effect transistors with SiO₂/HfO₂/HfSiO gate stack and TaN metal gate electrode are investigated under uniform and non-uniform charge injection along the channel. Compared to constant voltage stress (CVS), hot carrier stress (HCS) exhibits more severe degradation in transconductance and subthreshold swing. By applying a detrapping bias, it is demonstrated that charge trapping induced degradation is reversible during CVS, while the damage is permanent for hot carrier injection case.     

Effect of thin Si insertion at metal gate/high-k interface on electrical characteristics of MOS device with La2O3

The effect of a thin Si layer insertion at W/La₂O₃ interface on the electrical characteristics of MOS capacitors and transistors is investigated. A suppression in the EOT increase can be obtained with Si insertion, indicating the inhibition of diffusion of oxygen atoms into La₂O₃ layer by forming an amorphous La-silicate layer at the W/La₂O₃ interface. In addition, positive shifts in V_fb and V_th caused by Si insertion implies the formation of amorphous La-silicate layer at the top of La₂O₃ dielectrics reduces the positive fixed charges induced by the metal electrode. Consequently, a large improvement in mobility has been confirmed for both at peak value and at high E_eff of 1 MV/cm with Si inserted nFETs. Although a degradation trend on EOT scaling has been observed, the insertion of thin Si layer is effective in pushing the scaling limit.     

CHC degradation of strained devices based on SiON and high-k gate dielectric materials

A comparison between the Channel Hot-Carrier (CHC) degradation on strained pMOSFETs with SiGe source/drain (S/D) based on different gate dielectric materials, as SiON or HfSiON, has been done. The influence of the device channel orientation, channel length and temperature on the CHC damage has been studied.     

Comparison of interfacial and electrical properties between Al2O3 and ZnO as interface passivation layer of GaAs MOS device with HfTiO gate dielectric

GaAs metal–oxide–semiconductor(MOS) capacitors with HfTiO as the gate dielectric and Al2O3 or ZnO as the interface passivation layer(IPL) are fabricated. X-ray photoelectron spectroscopy reveals that the Al2O3 IPL is more effective in suppressing the formation of native oxides and As diffusion than the ZnO IPL. Consequently, experimental results show that the device with Al2O3 IPL exhibits better interfacial and electrical properties than the device with ZnO IPL: lower interface-state density(7.21012 eV1cm2/, lower leakage current density(3.60107A/cm2 at Vg D1 V) and good C–V behavior.     

Resistive switching effects of HfO2 high-k dielectric

Resistive switching behavior of HfO₂ high-k dielectric has been studied as a promising candidate for emerging non-volatile memory technology. The low resistance ON state and high resistance OFF state can be reversibly altered under a low SET/RESET voltage of ±3 V. The memory device shows stable retention behavior with the resistance ratio between both states maintained greater than 103. The bipolar nature of the voltage-induced hysteretic switching properties suggests changes in film conductivity related to the formation and removal of electronically conducting paths due to the presence of oxygen vacancies induced by the applied electric field. The effect of annealing on the switching behavior was related to changes in compositional and structural properties of the film. A transition from bipolar to unipolar switching behavior was observed upon O₂ annealing which could be related to different natures of defect introduced in the film which changes the film switching parameters. The HfO₂ resistive switching device offers a promising potential for high density and low power memory application with the ease of processing integration.     

Effect of biasing at elevated temperature on the electronic structure of Pt/HfO2/Si stacks

The spatial distribution of charges in a Pt/HfO₂/Si stack has been manipulated by applying a cyclic bias voltage ±2.5 V in combination with moderate (T ∼ 630 K) heating. The modifications were monitored in situ by room temperature capacitance-voltage (C-V) and current-voltage (I-V) measurements and analyzed ex situ by hard X-ray photoelectron spectroscopy which additionally provides information on possible chemical changes at the interfaces. The experimental data on the charge/potential distributions resulting from the different steps of bias-temperature stress (BTS) are consistent with the model that additional oxygen vacancies, which are generated in HfO₂ and positively charged by charge transfer across the interface with a high work function metal (Pt), are driven across the HfO₂ layer. These vacancies ultimately control the observed growth/dissolution of SiO_x at the bottom interface upon negative/positive BTS, respectively.     

A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

Annealing effects on electrical characteristics and reliability of MOS device with HfO₂ or Ti/HfO₂ high-k dielectric are studied in this work. For the sample with Ti/HfO₂ higher-k dielectric after a post-metallization annealing (PMA) at 600 °C, its equivalent oxide thickness value is 7.6 Å and the leakage density is about 4.5 × 10⁻² A/cm². As the PMA is above 700 °C, the electrical characteristics of MOS device would be severely degraded.     

Characterization of the annealing impact on La2O3/HfO2 and HfO2/La2O3 stacks for MOS applications

The impact of various rapid thermal annealing used during the integration on the La₂O₃/HfO₂ and HfO₂/La₂O₃ stacks deposited by Atomic Layer deposition was analyzed. The consequences of lanthanum localization in such stacks on the evolution of the films during the rapid thermal annealing are investigated in term of morphology, crystalline structure, silicate formation and film homogeneity as a function of the depth. It appeared that the La₂O₃ location has an impact on the temperature of the quadratic phase formation which could be linked to the formation of SiOHfLa silicate and the resistance of the films to dissolution in HF 0.05 wt%.     

SiON and SiO2/HfSiON gate oxides time dependent dielectric breakdown measurements at nanoscale in ultra high vacuum

Time dependent dielectric breakdown (TDDB) measurements on a nano-scale using an AFM tip under ultra high vacuum as upper electrode are systematically compared to device measurements in this paper. Both studies were performed on the same SiON or SiO₂/HfSiON gate oxides. The shape factor of the TDDB distribution and the acceleration factor are compared at both scales.     

Density functional theory study of first-layer adsorption of ZrO2 and HfO2 on Ge(1 0 0)

Density functional theory was used to performed a survey of transition metal oxide (MO₂ = ZrO₂, HfO₂) ordered molecular adsorbate bonding configurations on the Ge(1 0 0)-4 × 2 surface. Surface binding geometries of metal-down (O-M-Ge) and oxygen-down (M-O-Ge) were considered, including both adsorbate and displacement geometries of M-O-Ge. Calculated enthalpies of adsorption show that bonding geometries with metal-Ge bonds (O-M-Ge) are essentially degenerate with oxygen-Ge bonding (M-O-Ge). Calculated electronic structures indicate that adsorbate surface bonding geometries of the form O-M-Ge tend to create a metallic interfaces, while M-O-Ge geometries produce, in general, much more favorable electronic structures. Hydrogen passivation of both oxygen and metal dangling bonds was found to improve the electronic structure of both types of MO₂ adsorbate systems, and induced the opening of true semiconducting band gaps for the adsorbate-type M-O-Ge geometries. Shifts observed in the DOS minima for both O-M-Ge and M-O-Ge adsorbate geometries are consistent with surface band bending induced by the adsorbate films, where such band bending extends much further into the Ge substrate than can be modeled by the Ge slabs used in this work.     

Towards metal electrode interface scavenging of rare-earth scandates: A Sc2O3 and Gd2O3 study

Amorphous Gd₂O₃ and Sc₂O₃ thin films were deposited on Si by high-pressure sputtering (HPS). In order to reduce the uncontrolled interfacial SiO_x growth, firstly a metallic film of Gd or Sc was sputtered in pure Ar plasma. Subsequently, they were in situ plasma oxidized in an Ar/O₂ atmosphere. For post-processing interfacial SiO_x thickness reduction, three different top metal electrodes were studied: platinum, aluminum and titanium. For both dielectrics, it was found that Pt did not react with the films, while Al reacted with them forming an aluminate-like interface and, finally, Ti was effective in scavenging the SiO₂ interface thickness without severely compromising gate dielectric leakage.     

Integration of HfxTayN metal gate with SiO2 and HfOxNy gate dielectrics for MOS device applications

Interaction of Hf_xTa_yN metal gate with SiO₂ and HfO_xN_y gate dielectrics has been extensively studied. Metal-oxide-semiconductor (MOS) device formed with SiO₂ gate dielectric and Hf_xTa_yN metal gate shows satisfactory thermal stability. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) analysis results show that the diffusion depths of Hf and Ta are less significant in SiO₂ gate dielectric than that in HfO_xN_y. Compared to HfO_xN_y gate dielectric, SiO₂ shows better electrical properties, such as leakage current, hysteresis, interface trap density and stress-induced flat-band voltage shift. With an increase in post metallization annealing (PMA) temperature, the electrical characteristics of the MOS device with SiO₂ gate dielectric remain almost unchanged, indicating its superior thermal and electrical stability.     

Characterization of transient currents in HfO2 capacitors in the short timescale

We present a detailed experimental investigation of transient currents in HfO₂ capacitors in the short timescale. We show that the transient currents flowing through the capacitor plates when the gate voltage is reset to zero after a low voltage stress period follow a power-law time dependence t^−α (with α ? 1) over more than eight decades of time and down to the μs timescale. As transient currents in HfO₂ are largely increased with respect to the SiO₂ case, these results confirm that transient effects can be a severe issue for the successful integration of high-k dielectrics.     

Hf-O-N and HfO2 barrier layers for Hf-Ti-O gate dielectric thin films

Hf-O-N and HfO₂ thin films were evaluated as barrier layers for Hf-Ti-O metal oxide semiconductor capacitor structures. The films were processed by sequential pulsed laser deposition at 300 °C and ultra-violet ozone oxidation process at 500 °C. The as-deposited Hf-Ti-O films were polycrystalline in nature after oxidation at 500 °C and a fully crystallized (o)-HfTiO₄ phase was formed upon high temperature annealing at 900 °C. The Hf-Ti-O films deposited on Hf-O-N barrier layer exhibited a higher dielectric constant than the films deposited on the HfO₂ barrier layer. Leakage current densities lower than 5 × 10 A/cm² were achieved with both barrier layers at a sub 20 Å equivalent oxide thickness.     

Effects of nitrogen incorporation by plasma immersion ion implantation on electrical characteristics of high-k gated MOS devices

Nitridation treatments are generally used to enhance the thermal stability and reliability of high-k dielectric. It is observed in this work that, the electrical characteristics of high-k gated MOS devices can be significantly improved by a nitridation treatment using plasma immersion ion implantation (PIII). Equivalent oxide thickness, (EOT) and interface trap density of MOS devices are reduced by a proper PIII treatment. At an identical EOT, the leakage current of devices with PIII nitridation can be reduced by about three orders of magnitude. The optimal process conditions for PIII treatment include nitrogen incorporation through metal gate, ion energy of 2.5 keV, and implantation time of 15 min.     

MOS devices with tetragonal ZrO2 as gate dielectric formed by annealing ZrO2/Ge/ZrO2 laminate

A Ge-stabilized tetragonal ZrO₂ (t-ZrO₂) film with permittivity (κ) of 36.2 was formed by depositing a ZrO₂/Ge/ZrO₂ laminate and a subsequent annealing at 600 °C, which is a more reliable approach to control the incorporated amount of Ge in ZrO₂. On Si substrates, with thin SiON as an interfacial layer, the SiON/t-ZrO₂ gate stack with equivalent oxide thickness (EOT) of 1.75 nm shows tiny amount of hysteresis and negligible frequency dispersion in capacitance-voltage (C-V) characteristics. By passivating leaky channels derived from grain boundaries with NH₃ plasma, good leakage current of 4.8 × 10⁻⁸ A/cm² at V_g = V_fb − 1 V is achieved and desirable reliability confirmed by positive bias temperature instability (PBTI) test is also obtained.     

A nanoanalytical investigation of elemental distributions in high-k dielectric gate stacks on silicon

Two high-k gate stacks with the structure Si/SiO₂/HfO₂/TiN/poly-Si are characterised using nanoanalytical electron microscopy. The effect of two key changes to the processing steps during the fabrication of the stacks is investigated. Electron energy-loss spectroscopy is used to show that the TiN layer has a very similar composition whether it is deposited by PVD or ALD. Spectrum imaging in the electron microscope was used to profile the distribution of elements across the layers in the stack. It was found that when the anneal after HfO₂ deposition is carried out in a NH₃ atmosphere instead of an O₂ atmosphere, there is diffusion of N into the SiO₂ and HfO₂ layers. There is also significant intermixing of the layers at the interfaces for both wafers.     

Pre- and post-BD electrical conduction of stressed HfO2/SiO2 MOS gate stacks observed at the nanoscale

In this work, the electrical properties of fresh and stressed HfO₂/SiO₂ gate stacks have been studied using a prototype of Conductive Atomic Force Microscope with enhanced electrical performance (ECAFM). The nanometer resolution of the technique and the extended current dynamic range of the ECAFM has allowed to separately investigate the effect of the electrical stress on the SiO₂ and the HfO₂ layer of the high-k gate stack. In particular, we have investigated this effect on both layers when the structures where subjected to low and high field stresses.