A DRAM compatible Cu contact using self-aligned Ta-silicide and Ta-barrier

As an alternative to W contacts currently used in MOSFETs for DRAM, Cu contacts using self-aligned Ta-silicide and Ta-based barrier were studied experimentally. The silicidation of PVD Ta layers was studied first on 300 mm blanket Si wafers. The developed method was applied to patterned wafers in the contacts, that land on poly gate and active areas of NMOS, with a sequence including the PVD of Ta, a silicidation annealing, a Ta-based Cu diffusion barrier and a Cu seed for plating the Cu plug. X-ray diffraction (XRD), X-ray reflection (XRR) and sheet resistance tests of the blanket wafers show that a Ta layer of about 10 nm reacts with Si substrate and forms TaSi₂ at 650 °C in a reducing ambient. Cross-sectional SEM observation reveals that the selected processing flow fills the 90 nm contacts. Top-view SEM observation on the samples after 420 °C sintering demonstrates that the Cu diffusion barrier is effective. I_on-I_off curves of the devices show a performance for NMOS comparable to the reference samples which use Ni(Pt)Si and the same barrier and Cu contacts, indicating that the stack of the barrier/TaSi₂/p-type Si has a contact resistance comparable to the barrier/Ni(Pt)Si/p-type Si.     

Electrical performance, reliability and microstructure of sub-45 nm copper damascene lines fabricated with TEOS backfill

The fabrication of narrow Cu trenches using a conformal TEOS backfill approach is shown. Cu trenches with widths down to 30-40 nm were achieved. With an adequate Ta-based PVD barrier and Cu seed layer scheme, narrow Cu lines with high yield were obtained. An increase of the electrical resistivity in the narrowest dimensions was observed as a result of the size effect. Electromigration assessment demonstrated that a bilayer TaN/Ta barrier outperforms the monolayer Ta barrier. Electron backscattering diffraction (EBSD) analysis was carried out to determine grain orientation and texture in narrow copper trenches. For the first time, EBSD data reveal that Cu trenches down to 30-40 nm wide have mostly a random texture. The narrower the Cu lines get, the weaker the (1 1 1) texture with both monolayer and bilayer Ta-based barriers.     

ALD-grown seed layers for electrochemical copper deposition integrated with different diffusion barrier systems

The deposition of Cu seed layers for electrochemical Cu deposition (ECD) via atomic layer deposition (ALD) of copper oxide and subsequent thermal reduction at temperatures between 110 and 120 °C was studied on different diffusion barrier systems. While optimization of the process is required on TaN with respect to reduction and plating, promising results were obtained on blanket PVD Ru. The plating results on layers of ALD Cu with underlying Ru even outperformed the ones achieved on PVD Cu seed layers with respect to morphology and resistivity. Applying the processes to via and line patterns gave similar results, suggesting that a combination of ALD Cu with PVD or ALD-grown Ru could significantly improve the ECD Cu growth.     

Impact of “terminal effect” on Cu electrochemical deposition: Filling capability for different metallization options

The 300 mm wafer copper electrochemical deposition (ECD) process for dual damascene metallization of semiconductor advanced interconnects is critically reviewed and the breakthroughs that enable further scaling of this process are examined. Special emphasis is placed on analyzing the critical issues, such as barrier/seed options, terminal effect and future plating prospects for this technology. The smallest plateable feature size values are estimated for different metallization integration schemes, such as conventional Physical Vapor Deposited (PVD) TaN/Ta/Cu, hybrid RuTa/Cu, CuMn (8%) self-forming barrier/seed, and Plasma-Enhanced Atomic Layer Deposition (PEALD) Ru, limiting the allowed maximum sheet resistance to 14 Ohms/sq for the Cu-based seeds and the effective maximum filling aspect ratio to 5-6.     

Enhancing the reliability of n-p junction diodes using plasma treated tantalum barrier film

The properties of Ta barrier films treated with various plasma nitridations have been investigated by Cu/barrier/Si. An amorphous layer is formed on Ta barrier film after plasma treatments. The thickness of the amorphous layer is about 3 nm. Plasma treated Ta films possess better barrier performance than sputtered Ta and TaN films. It is attributed to the formation of a new amorphous layer on Ta surface after the plasma treatment. Cu/Ta(N,H)/Ta (10 nm)/Si remained stable after annealing at 750 °C. Ta(N,H)/Ta possesses the best thermal stability and excellent electrical properties. Cu/Ta/n⁺-p and Cu/Ta(N,O)/Ta/n⁺-p diodes resulted in large reverse-bias junction leakage current after annealing at 500 °C and 600 °C, respectively. On the other hand, Ta(N,H)/Ta and Ta(N)/Ta diffusion barriers improve the thermal stability of junction diodes to 650 °C. Ta(N,H)/Ta barrier film possesses lowest resistivity among Ta, Ta(N,O)/Ta, and Ta(N)/Ta films. Hydrogen plays an important role in enhancement of barrier properties. It is believed that hydrogen not only induces amorphization on Ta, but also eliminates the oxygen in the film. It is believed that the enhancement of ability against the copper diffusion is due to the combined effects of the hydrogen reaction and nitridation.     

Comparison of PVD, PECVD & PEALD Ru(-C) films as Cu diffusion barriers by means of bias temperature stress measurements

The diffusion barrier properties of PVD Ru and PECVD / PEALD Ru-C films, deposited by RuEtcp₂ precursor and N₂/H₂ plasma, were compared on the basis of bias temperature stress measurements. An MIS test structure was used to distinguish between thermal diffusion induced by annealing and a Cu field drift due to applied electric fields. BTS-CV, TZDB and TDDB measurements revealed that the barrier performance is significantly better for PEALD and PECVD Ru-C films. This improvement is associated with carbon impurities in the Ru films with a concentration in the order of several percent according to ToF-SIMS and ERDA. The TDDB mean time to failure at 250 °C, +5 MV/cm was 7 s for PVD Ru samples, ≈500 s for PECVD Ru-C, ≈800 s for PEALD Ru-C and >3600 s for PVD TaN. Triangular voltage sweep measurements at 300 °C, 0.1 V/s confirmed the presence of Cu ions inside the SiO₂ for degraded dots, in contrast to the Al reference sample and to PVD TaN, which performed best among all the Cu barriers under test. XRD data suggests that PEALD and PECVD Ru-C films are only weakly crystalline.     

Failure mechanisms of PVD Ta and ALD TaN barrier layers for Cu contact applications

PVD Ta-based and ALD TaN layers were studied as Cu diffusion barriers on poly-silicon, NiSi and CoSi₂ for Cu contact applications. The effectiveness of nanometer-thick layers, deposited in manufacturing compatible chambers on 200 and 300 mm wafers, is evaluated by detection of Cu-silicidation temperature using high temperature in situ XRD. It is found that Si diffuses into the α-Ta lattice for PVD barriers between 300 and 500 °C, and induces Ta silicidation at 600 °C. The agglomeration of TaSi₂ seems to be responsible for the damage of barrier continuity and cause subsequent Cu-silicidation. The growth of ALD TaN on different surfaces of NiSi was studied by XRF, RBS and XRR. The growth curves show excellent linearity as a function of thickness. TOF-SIMS shows closed layers after 60 ALD cycles. In situ XRD reveals that the failure temperature of 4 nm thick ALD layers is higher than 500 °C. It is found that the failure of 3 and 4 nm ALD TaN layers in Cu/barrier/NiSi stacks is a diffusion controlled process, with an activation energy Q of ∼2.2 eV and a pre-exponential factor D₀ of ∼3.8 × 10⁻³ cm²/s.     

Reliability of multistacked tantalum-based structure as the barrier film in ultralarge-scale integrated metallization

Diffusion barrier properties of Ta films with and without plasma treatments have been investigated in the study. The nitrogen-incorporated Ta films were prepared by NH₃ plasma treatment or reactive sputtering. Barrier properties were evaluated by sheet resistance, X-ray diffraction, transmission electron microscopy, X-ray photoelectron spectroscopy and reverse-biased junction leakage current. An amorphous-like TaN_x layer was formed on Ta barrier film after plasma treatments. The thickness of the amorphous TaN_x layer is about 3 nm and NH₃ plasma-treated Ta films (TaN_x/Ta) possess lower resistivity and smaller grain sizes. The Cu/TaN_x/Ta(10 nm)/Si remained stable after annealing at 750 °C for 1 h. NH₃ plasma-treated Ta films (TaN_x/Ta) possess better thermal stability than Ta and TaN films. It is attributed to the formation of a new amorphous layer on the surface of Ta film after the plasma treatments. For thermal stability of Cu/Ta(-N)/n⁺-p diodes, Cu/Ta/n⁺-p and Cu/TaN/n⁺-p junction diodes resulted in large reverse-bias junction leakage current after annealing at 500 and 525 °C, respectively. On the other hand, TaN_x/Ta diffusion barriers will improve the integrity of Cu/Ta(-N)/n⁺-p junction diodes to 650 °C.     

Thermal and Electrical Properties of PVD Ru(P) Film as Cu Diffusion Barrier

Thermal and electrical properties of physical vapor deposition (PVD) Ru(P) film deposited on porous ultra low-k (p-ULK) material as Cu diffusion barrier were studied. The phosphorous concentration can be tuned by adjusting Ar to PH₃ ratio of the sputtering gases. The leakage current depends on phosphorous concentration. Higher phosphorous content in Ru film has lower leakage current. No obvious phosphorous content dependence was observed when the amorphous Ru(P) film crystallized. The X-ray diffraction (XRD) graphs and energy dispersive spectrometer’s (EDS) atomic depth profiles show that the Ru(P) film deposited on p-ULK can effectively block Cu diffusion when the sample is subjected to 800 °C 5 min annealing. The phosphorous doped Ru film improves diffusion barrier properties and leakage current performance. The improved Ru(P) barrier capable of direct Cu plating could be a potential candidate for advanced metallization.     

Cu contact on NiSi/Si with thin Ru/TaN barrier

Thin Ru(5 nm)/TaN(15 nm) bi-layer was sputtered on the NiSi/Si substrate as a diffusion barrier in the copper contact structure. The barrier properties were investigated through X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM), energy dispersive X-ray (EDX) and electrical measurement. The whole Cu/Ru/TaN/NiSi/Si structure has a good thermal stability until after annealing at 450 °C. The Schottky barrier measurement shows that the leakage current increases after 450 °C annealing and after 500 °C annealing the barrier fails. Failure mechanism of the barrier stack is discussed.     

Texture of atomic layer deposited ruthenium

Ruthenium films were grown by plasma enhanced atomic layer deposition (ALD) on Si(1 0 0) and ALD TiN. X-ray diffraction (XRD) showed that the as-deposited films on Si(1 0 0) were polycrystalline, on TiN they were (0 0 2) oriented. After annealing at 800 °C for 60 s, all Ru films were strongly (0 0 2) textured and very smooth. Electron backscatter diffraction (EBSD) and transmission electron microscopy (TEM) demonstrated that the lateral grain size of the annealed films was several 100 nm, which was large compared to the 10 nm thickness of the films. No ruthenium silicide was formed by annealing the ALD Ru films on Si(1 0 0). Comparison with sputter deposited films learned that this occurred because the ammonia plasma created a SiO_xN_y reaction barrier layer prior to film growth.     

Hf-O-N and HfO2 barrier layers for Hf-Ti-O gate dielectric thin films

Hf-O-N and HfO₂ thin films were evaluated as barrier layers for Hf-Ti-O metal oxide semiconductor capacitor structures. The films were processed by sequential pulsed laser deposition at 300 °C and ultra-violet ozone oxidation process at 500 °C. The as-deposited Hf-Ti-O films were polycrystalline in nature after oxidation at 500 °C and a fully crystallized (o)-HfTiO₄ phase was formed upon high temperature annealing at 900 °C. The Hf-Ti-O films deposited on Hf-O-N barrier layer exhibited a higher dielectric constant than the films deposited on the HfO₂ barrier layer. Leakage current densities lower than 5 × 10 A/cm² were achieved with both barrier layers at a sub 20 Å equivalent oxide thickness.     

Fabrication of Cu(Ti) Alloy Interconnects with Self-Formation of Thin Barrier Metal Layers Using a High-Pressure Annealing Process

Copper interconnects with self-formed thin TiSi _x O _y barrier layers were successfully fabricated by sequentially depositing Cu(7 at.%Ti) alloys and pure Cu films on SiO₂-based substrates with 0.1-μm-wide trenches, and embedding the samples using a high-pressure annealing technique at 550°C and 195 MPa. Microstructural analyses revealed that the self-formed Ti-rich layers with thicknesses of about 5 nm were uniformly formed on the trench bottom and sidewall. In addition, these layers were thermally stable against Cu diffusion into the SiO₂-based interlayers. The present study suggests that the Cu-Ti alloy is one of the best candidates among possible interconnect and/or seed layer materials.     

Enhancement of adhesion strength of Cu layer with low dielectric constant SiC:H liners in Cu interconnects

One of the primary candidates for the liner/etch stop layer in damascene process is silicon nitride (Si₃N₄). However, silicon nitride has a high dielectric constant of 7.0. To reduce the effective dielectric constant in Copper (Cu) damascene structure, dielectric SiC:H (prepared by plasma enhanced chemical vapor deposition (PECVD) using trimethylsilane source) as the Cu diffusion barrier was studied. The dielectric constant of SiC:H used is 4.2. A systematic study was made on the properties of liner material and electro-chemically plated (ECP) Cu to enhance the adhesion strength in Cu/low-dielectric constant (k) multilevel interconnects. Though the effects of as Si₃N₄ the liner have been much studied in the past, less is known about the relation between adhesion strength of ECP Cu layer and physical vapor deposited (PVD) Cu seeds, with seed thickness below 1000 Å. The annealing of Cu seed layer was carried out at 200 °C in N₂ ambient for 30 min was carried out to study the impact on adhesion strength and the microstructure evolution on the adhesion between ECP Cu and its barrier layer. In the study, our claim that SiC:H barrier/etch stop layer is essential for replacing conventional Si₃N₄ layer in enhancing adhesion strength and interfacial bonding between Cu/dielectric interconnects.     

Effect of Si/Ta and nitrogen ratios on the thermal stability of Ta-Si-N thin films

Ta-Si-N thin films were fabricated by using reactive magnetron cosputtering at different Si/Ta power ratios and nitrogen (N₂) to total gas (Ar + N₂) flow ratios (FN₂% = FN₂/(FAr + FN₂) × 100%). Both levels of high-vacuum furnace annealing (FA) and low vacuum rapid thermal annealing (RTA) were performed to investigate the thermal stability of films. The microstructure, morphology and electrical property of the Ta-Si-N thin films were characterized by grazing incidence X-ray diffraction, scanning electron microscope and four-point probe method, respectively. Ta-Si-N thin films at low FN₂% could endure temperature up to 900 °C for 1 h under high-vacuum FA at 6.5 × 10⁻³ Pa while their phase and morphology had changed under RTA at 750-900 °C for 1 min at 2.6 Pa. The resistivity increased with increasing both FN₂% and Si/Ta power ratios. However, the variation percentage of resistivity of Ta-Si-N films at high-temperature annealing decreased with increasing Si/Ta power ratio and inversely increased with increasing FN₂%. In brief, the thermal stability of Ta-Si-N films increased with increasing level of vacuum and Si/Ta power ratio. Increasing FN₂% and Si/Ta power ratio could enhance the thermal stability of films at RTA but also increased the resisitivity of films. Therefore, Ta-Si-N films prepared at 2 FN₂% and Si/Ta power ratio of 2/1 can be a good candidate for the application of diffusion barrier with low resistivity, low variation percentage and high stability of microstructure.     

Sputtered Ru-Ti, Ru-N and Ru-Ti-N films as Cu diffusion barrier

Ultrathin Ru-Ti alloy, Ru-N and Ru-Ti-N films were fabricated as diffusion barriers to Cu metallization. The thermal stability, phase formation, surface morphology and atomic depth profile of the Cu/Ru-Ti(10 nm)/Si, Cu/Ru-N(10 nm)/Si and Cu/Ru-Ti-N(10 nm)/Si structures after annealing at different temperatures were investigated. Comparing to the single Ru layer, both N doping and Ti alloying improve the thermal stability and diffusion barrier properties to Cu. The Cu on the Ru-Ti layer has better morphology than Cu on the Ru-N layer, while the Ru-Ti-N layer has the best thermal stability and has great potential to be applied as a single layer diffusion barrier.     

Development of different copper seed layers with respect to the copper electroplating process

Two types of copper seed layers deposited by MOCVD and long throw sputtering (LTS) onto a tantalum barrier layer were used for electroplating (EP) of copper in the forward pulsed mode. MOCVD and PVD copper seed layers were compared with respect to step coverage, electrical resistivity, texture and adhesion behaviour. The different properties induce different electroplating fill attributes, including grain size and adhesion behaviour. MOCVD Cu seed layers show high step coverage, but do not adhere to the Ta barrier after the Cu EP. LTS Cu reveal strong (111) texture and excellent adhesion before and after Cu EP. Therefore, a CMP process could only be performed on patterned wafers with PVD/EP copper to obtain electrical data. The fabricated Cu lines show a high yield with respect to opens and shorts and standard deviations of the line resistance across the wafer.     

Atomic layer deposition of tantalum oxide thin films for their use as diffusion barriers in microelectronic devices

Atomic Layer Deposition (ALD) was used for the deposition of tantalum oxide thin films in order to be integrated in microelectronic devices as barrier to copper diffusion. The influence of deposition temperature, number of cycles and precursor pulse time on the film growth was discussed. The conformity of thinnest deposited films was shown. Copper diffusion through ALD Ta₂O₅ thin films, 20 nm in thickness, was investigated, for three temperatures from 600 to 800 °C, using X-ray Photoelectron Spectroscopy. The failure of such films was detected after a thermal treatment at 700 °C.     

Impact of barrier deposition process on electrical and reliability performance of Cu/CVD low k SiOCH metallization

Integration of Cu with low k dielectrics provided solution to reduce both resistance-capacitance time delay and parasitic capacitance of BEOL interconnections for 130 nm and beyond technology node. The motivation of this work is to study and improve electrical and reliability performance of two-level Cu/CVD low k SiOCH metallization from the results of diffusion barrier deposition schemes. Barrier deposition schemes are (a) high-density-plasma 250 Å Ta; (b) surface treatment of forming gas followed by high-density-plasma 250 Å Ta and (c) bi-layer of 100 Å Ta(N)/150 Å Ta. In this work, we demonstrated the superior and competency of high-density-plasma Ta deposition for Cu/CVD low k metallization and achieved excellent electrical and reliability results. Wafers fabricated with high-density-plasma Ta barrier scheme resulted in the best electrical yields, >90% for testing vehicles of dense via chains (via size=200 nm) and interspersed comb structures (width/space=200 nm/200 nm). Dielectric breakdown strength of the interspersed comb structures obtained at electric field of 0.3 MV/cm was ∼4 MV/cm.     

High aspect ratio via metallization for 3D integration using CVD TiN barrier and electrografted Cu seed

3D integration is of high interest to overcome the future challenges that are to be met both by device interconnections and packaging. In between the challenges that are to be met to achieve this process is the via fill when making high aspect ratio vias and barrier and seed deposition layers deposition.In this paper, we showed that we were able to achieve a good continuity with a good conformality for barrier and seed layers in Aspect Ratio 10 vias, using respectively CVD TiN and eG ViaCoat^™ Cu seed. The studied vias are 5 μm wide and 50 μm deep.We first demonstrated the continuity of the barrier by performing a HF-dip test on trenches structures and, after having run a DOE to optimize seed layer deposition recipe, we did some early test of via fill to assess the continuity of the barrier/seed stack.