A highly miniaturized LTCC dual-band UWB filter using independent transmission zeros and lowpass filters

In this paper, a compact dual-band ultra-wideband (UWB) filter has been newly designed and fabricated for 3.1–4.75 GHz and 6.0–8.5 GHz UWB system applications by embedding all passive lumped elements into low temperature co-fired ceramic (LTCC) substrate. In order to reduce its size/volume and prevent parasitic electromagnetic (EM) coupling between the embedded passive elements, it was newly designed by using a modified 3rd order Chebyshev filter topology and J-inverter transformation technology. Moreover, in order to completely reject the wireless local area network (WLAN) bands of 2.4 GHz and 5.15 GHz, an independent transmission zeros technology was applied. For forming the higher passband, lowpass filters were also applied with two LC resonant circuits by using roll-off characteristics by independent transmission zeros. The measured insertion losses in the lower and upper passbands were better than 2.5 and 2.3 dB, respectively. Return loss and group delay were better than 8 dB and 0.61 ns, respectively in all the passbands. Independent transmission zeros that occurred at 5.17 and 5.42 GHz provided suppression of 22 dB at the WLAN band. The size/volume of the fabricated LTCC dual-band UWB filter was 3.65×2.35×0.65 (H) mm³.     

Wireless smart sensor with small spiral antenna on Si-substrate

This paper presents a wireless smart sensor (WSS) with a thermoelectric sensor, a wireless transmitter and a small spiral antenna on a single package. To transmit a sensor signal, the wireless transmitter was designed to consist of an amplifier, a modulator, an oscillator, a buffer stage and an antenna. The wireless transmitter used dual pulse position modulation for low-power transmission. The fabricated transmitter has a sampling frequency of 2.6 kHz and an output carrier wave frequency of 300 MHz band due to the higher far field radiation of the transmitted signals from inside the body. The small size spiral antenna on the chip was fabricated for the transmission of carrier waves. The antenna has a bandwidth of 270-360 MHz for VSWR<2 and a gain of −40 dBi. The fabricated sensor, transmitter and spiral antenna were packaged with bond-wire on a single package. The WSS consumed a power of about 16.9 mW at the supply power of 5 V. The electric field strength of the WSS was measured to be 64.6 dB μV/m at a distance of 3 m. The wireless operation of the fabricated WSS was confirmed by demonstrating that the sensor signal was modulated by the transmitter and that the modulated sensor data was transmitted through the small size spiral antenna.     

Energy efficiency of error control coding in intra-chip RF/wireless interconnect systems

Continuous scaling of conventional hard-wired metal interconnects into deep sub-micrometer region (DSM) has resulted in significant performance degradation in terms of delay, crosstalk noise, higher power dissipation, and decreased tolerance to noise. Besides, communication-centric nature of system-on-chip (SOC) networks requires efficient intra- and inter-chip interconnect technologies. Radio-frequency (RF)/wireless interconnects promise to be the best alternative to metal interconnects as they are compatible with current CMOS-technology, and they also provide higher data rate and bi-directional multi I/O transmissions. This paper evaluates the system bit-error-rate (BER) performance with the application of fault-tolerance capability using linear error-control codes (ECCs) within chip (intra-chip) RF/wireless interconnect systems. It also evaluates the utility of ECCs by considering energy consumed in ECC encoding-decoding vis-à-vis the energy saved due to coding gain by calculating the critical distance (d_cr). The results indicate that for a certain range of received signal-to-noise ratio (SNR), application of ECC improves the BER performance of the RF/wireless interconnect system. It is also shown that d_cr drops to 0.7 mm at 18 GHz.     

Fabrication of low-loss thin film microstrip line on low-resistivity silicon for RF applications

A detail fabricating process and characterization of thin film microstrip line (TFML) on low K polyimide, used for interconnects in radio frequency integrated circuits (RFICs) technology, is reported in this study. By incorporating a spin-on dielectric polyimide and sputtering of aluminum, the TFML is fabricated on low-cost low-resistivity silicon (LRS) substrate (ρ?10 Ω cm). The TFML with a thickness of 20 μm polyimide dielectric layer presents attenuation losses of 0.385 dB/mm at 25 GHz and 0.438 dB/mm at 50 GHz. Effective dielectric constant and attenuation of TFML on polyimide are carefully investigated and discussed.     

Linearization technique using bipolar transistor at 5 GHz low noise amplifier

A CMOS low noise amplifier (LNA) used in wireless communication systems, such as WLAN and CDMA, must have low noise figure, high linearity, and sufficient gain. Several techniques have been proposed to improve the linearity of CMOS LNA circuits. The proposed low noise amplifier achieves high third-order input intercept point (IIP3) using multi-gated configuration technique, by using two transistors, the first is the main CMOS transistor, and the second is bipolar transistor in TSMC 0.18 m technology. Bipolar transistor is used to cancel the third-order component from MOS transistor to fulfill high linearity operation. This work is designed and fabricated in TSMC 0.18 m CMOS process. At 5 GHz, the proposed LNA achieves a measurement results as 16 dBm of IIP3, 10.5 dB of gain, 2.1 dB of noise figure, and 8 mW of power consumption.     

Ultra low power phase detector and phase-locked loop designs and their application as a receiver

In this paper, we present a new low power down-conversion mixer design with single RF and LO input topology which consumes 48 μW power. Detailed analysis of the mixer has been provided. Using the presented mixer as a phase-detector, a low power phase-locked loop (PLL) has been designed and fabricated. A PLL based receiver architecture has been developed and analyzed. The circuit has been fabricated through 0.13 μm CMOS technology. Dissipating 0.26 mW from a 1.2 V supply, the fabricated PLL can track signals between 1.62 and 2.49 GHz. For receiver applications, the energy per bit of the receiver is only 0.26 nJ making it attractive for low power applications including wireless sensor networks.     

Burst-mode optical transmitter with DC-coupled burst-enable signal for 2.5-Gb/s GPON system

In this paper, first burst-mode transmitter for 2.5-Gb/s gigabit-capable passive optical networks (GPON) system is evaluated. Small form factor (SFF) type optical network unit (ONU) generates 2.5-Gb/s optical eyes with commercial distributed feedback-laser diode (DFB-LD). For the fast burst signal access, burst enable (BEN) connection on the evaluation board utilizes DC-coupling configuration. Resultant optical output waveform shows 16.30 dB extinction ratio with wide eye opening for GPON mask test. No significant eye degradation is detected in high temperature operation and after 10 km distance transmission. Proposed GPON ONU successfully shows fast timing characteristics of 2.17 nsec for Tx enable stage and 1.17 ns for Tx disable stage.     

Grain morphology of Cu damascene lines

The evolution of the grain structure through annealing of narrow damascene Cu interconnects is important for any further design of highly integrated circuits. Here we present a comprehensive transmission electron microscopy study of damascene lines between 80 nm and 3000 nm wide. Experimental results clearly indicate that morphology evolutions through annealing are strongly influenced by the line width. If the lines are wider than 250 nm a strong connection between the grain structure within the lines and the overburden copper is present at least after sufficient annealing. Once the lines are as small as 80 nm the grain structure within the lines are only weakly connected to the overburden copper grown above.     

Thermally-aware modeling and performance evaluation for single-walled carbon nanotube-based interconnects for future high performance integrated circuits

Given the performance and reliability limits of conventional copper interconnects in the tens of nanometer regime, carbon-nanotube (CNT) based interconnects emerge as a potential reliable alternative for future high performance VLSI industry. In this paper, we present an accurate thermally-aware model for single-walled carbon-nanotube (SWCNT) based interconnects. Our thermally-aware model is an integration of temperature-dependent electrical parasitics model and thermal equivalent circuit that captures both self-heating and heat conduction phenomena. We verify the accuracy of our electro-thermal model against recently reported experimental measurements. By leveraging the presented electro-thermal model, we present a simulation platform to estimate the performance of SWCNT-based interconnects under different temperature conditions. Our thermally-aware model achieves improvement in the delay estimation accuracy of about 51.3% on average. Based on our simulation results, SWCNT-based interconnects offer more than 5×reduction in delay at dimensions of about 10-20 nm for 27- 127 °C temperature range.     

New ISFET interface circuit design with temperature compensation

An integrated and new interface circuit with temperature compensation has been developed to enhance the ISFET readout circuit stability. The bridge-type floating source circuit suitable for sensor array processing has been proposed to maintain reliable constant drain-source voltage and constant drain current (CVCC) conditions for measuring the threshold voltage variation of ISFET due to the corresponding hydrogen ion concentration in the buffer solution. The proposed circuitry applied to Si₃N₄ and Al₂O₃-gate ISFETs demonstrate a variation of the drain current less than 0.1 μA and drain-source voltage less than 1 mV for the buffer solutions with the pH value changed from 2 to 12. In addition, the scaling circuitry with the V_T temperature correction unit (extractor) and LABVIEW software are used to compensate the ISFET thermal characteristics. Experimental results show that the temperature dependence of the Si₃N₄-gate ISFET sensor improved from 8 mV/°C to less than 0.8 mV/°C.     

Optimal design of a microthermoelectric cooler for microelectronics

In this paper, performance analysis using finite element methods (FEM) was carried out to develop a microthermoelectric cooler (μ-TEC) for maintaining the chip temperatures under the operating limitation. The performance evaluation process using the Ansys FEM software is described. The effects of the geometries of the thermoelectric columns and the thicknesses of connecting electrodes were investigated. The governing equations for the μ-TEC element were developed and the analytical solutions of the heat absorbed at the cold side of a single μ-TEC element were obtained using the derived equations. The FEM calculation results agreed well with the analytic solutions. Based on these results, the geometries and dimensions of the μ-TEC element were optimized using Taguchi Methods for maximizing the heat absorbed at the cold side of the μ-TEC. The experimental plan using an Orthogonal Array L₉ (3⁴) is described in detail. Nine different μ-TEC models were simulated using FEM and the design parameters were optimized. The optimal width to depth ratio (width/depth) was found to be 3.6 (600 μm/167 μm) and the optimized thicknesses of the thermoelectric column and the gold electrode were 25 and 2 μm, respectively. The obtained optimal distance between the P-type and the N-type columns was found to be 35 μm. Finally, the absorbed heat of the optimized μ-TEC was calculated. The obtained value was 72.1 mW, which agreed well with the predicted value of 75.7 mW. At the end, the electrical contact resistance was considered and the calculated performance was 72.2 mW, which is a little smaller result than the analytic solution of 72.5 mW without the contact resistance.     

The use of metal filled via holes for improving isolation in LTCCRF and wireless multichip packages

LTCC MCM's for RF and wireless systems often use metal filled via holes to improve isolation between the stripline and microstrip interconnects. In this paper, results from a 3D-FEM electromagnetic characterization of microstrip and stripline interconnects with metal filled via fences for isolation are presented. It is shown that placement of a via hole fence closer than three times the substrate height to the transmission lines increases radiation and coupling. Radiation loss and reflections are increased when a short via fence is used in areas suspected of having high radiation. Also, via posts should not be separated by more than three times the substrate height for low radiation loss, coupling, and suppression of higher order modes in a package     

Bottom-contact small-molecule n-type organic field effect transistors achieved via simultaneous modification of electrode and dielectric surfaces

Low-voltage, n-type organic field effect transistors (OFETs) with simultaneously modified bottom-contact (BC) electrodes and dielectric were compared to their top-contact (TC) counterparts. The devices modified with 6-phenoxyhexylphosphonic acid (Ph6PA) self-assembled monolayer (SAM) showed similar performance, morphology, and contact resistance. Electron mobility of C₆₀ devices were 0.212 and 0.320 cm² V⁻¹ s⁻¹ and [6,6]-phenyl-C₆₁-butyric acid methyl ester (PCBM) devices were 0.04 and 0.06 cm² V⁻¹ s⁻¹ for TC and BC devices, respectively. Low contact resistance between 11 and 45 kΩ cm was found regardless of device architecture or n-type semiconductor used. This work shows it is possible to fabricate solution processable low-voltage bottom-contact devices with performance that is similar or better than their top-contact counterparts without the addition of complex and time-consuming processing steps.     

Internally compensated LDO regulator based on the cascoded FVF

In this paper, an internally compensated low dropout (LDO) voltage regulator based on the Flipped Voltage Follower (FVF) is proposed. By means of capacitive coupling and dynamic biasing, the transient response to both load and line variations is enhanced. The proposed circuit has been designed and fabricated in a standard 0.5 µm CMOS technology. Experimental results show that the proposed circuit features a line and a load regulation of 132.04 µV/V and 153.53 µV/mA, respectively. Moreover, the output voltage spikes are kept under 150 mV for a 2 V-to-5 V supply variation and for 1 mA-to-100 mA load variation, both in 1 µs.     

Performance of terahertz channel with multiple input multiple output techniques

Terahertz (THz) communication is being considered as a potential solution to mitigate the demand for high bandwidth. The characteristic of THz band is relatively different from present wireless channel and imposes technical challenges in the design and development of communication systems. Due to the high path loss in THz band, wireless THz communication can be used for relatively short distances. Even, for a distance of few meters (>5m), the absorption coefficient is very high and hence the performance of the system is poor. The use of multiple antennas for wireless communication systems has gained overwhelming interest during the last two decades. Multiple Input Multiple Output (MIMO) Spatial diversity technique has been exploited in this paper to improve the performance in terahertz band. The results show that the Bit Error Rate (BER) is considerably improved for short distance (<5m) with MIMO. However, as the distance increases, the improvement in the error performance is not significant even with increase in the order of diversity. This is because, as distance increases, in some frequency bands the signal gets absorbed by water vapor and results in poor transmission. Adaptive modulation scheme is implemented to avoid these error prone frequencies. Adaptive modulation with receiver diversity is proposed in this work and has improved the BER performance of the channel for distance greater than 5m.     

Fabrication of 3D MEMS toroidal microinductor for high temperature application

Based on Microelectromechanical systems (MEMS) technique and thick photoresist lithography technology, a new toroidal-type inductor for high temperature application has been successfully developed. In the fabrication process, heat-resistant materials are used, alumina as insulator and supporting materials instead of polyimide, heat resistant glass for underlay instead of normal glass, and copper for coil. The maximum inductance is 87 nH at 0.826 GHz and maximum of quality factor (Q-factor) is 4.63 at 0.786 GHz, at room temperature. With simulation of thermal deformation, it shows that the developed toroidal inductor can be suitable for high temperature application, from 300 to 700 °C.     

Spin cast self-assembled monolayer field effect transistors

Top-contact self-assembled monolayer field-effect transistors (SAMFETs) were fabricated through both spin-coating and solution assembly of a semiconducting phosphonic acid-based molecule (11-(5?-butyl-[2,2′;5′,2″;5″,2?;5?,2?]quinquethiophen-5-yl)undecylphosphonic acid) (BQT-PA). The field-effect mobilities of both spin-cast and solution assembled SAMFETs were 1.1-8.0 × 10⁻⁶ cm² V⁻¹ s⁻¹ for a wide range of channel lengths (between 12 and 80 μm). The molecular monolayers were characterized by atomic force microscopy (AFM), attenuated total reflectance-Fourier transform infrared spectroscopy (ATR-FTIR), and near edge X-ray absorption fine structure (NEXAFS) spectroscopy. It was found that the BQT-PA monolayer films exhibit dense surface coverage, bidentate binding, and tilt angles of ∼32° and ∼44° for the thiophene rings and alkyl chain, respectively. These results indicate that rapid throughput of fabricating SAMFETs is possible even by spin-coating.     

A novel compact circuit for 4-PAM energy-efficient high speed interconnect data transmission and reception

Transmission of signals, whether on-chip or off-chip, places severe constraints on timing and extracts a large price in energy. New silicon device technologies, such as back-plane CMOS, provide a programmable and adaptable threshold voltage as an additional tool that can be used for low power design. We show that one particularly desirable use of this freedom is energy-efficient high-speed transmission across long interconnects using multi-valued encoding. Our multi-valued CMOS circuits take advantage of the threshold voltage control of the transistors, by using the signal-voltage-to-threshold-voltage span, in order to make area-efficient implementations of 4-PAM (pulse amplitude modulation) transceivers operating at high speed. In a comparison of a variety of published technologies, for signal transmission with interconnects of 10-15 mm length, we show up to 50% improvement in energy for on-chip signal transmission over binary encoding together with higher limits for operating speeds without a penalty in circuit noise margin.     

A micromachining technology for integrating low-loss GHz RF passives on non-high-resistivity low-cost silicon MCM substrate

A micromachining technology for integrating high-performance radio-frequency (RF) passives on CMOS-grade low-cost silicon substrates is developed. The technology can form a thick solid-state dielectric isolation layer on silicon substrate through high-aspect-ratio trench etch and refill. On the non-high-resistivity but low-loss substrate, two metal layers with an inter-metal dielectric layer are formed for integrating embedded RF components and passive circuits. Using the technology, two types of integrated RF filters are fabricated that are band-pass filter and image-reject filter. The band-pass filter shows measured minimum insertion loss of 3.8 dB and return loss better than 15 dB, while the image-reject filter exhibits steeper band selection and achieves better than −30 dB image rejection. A 50 Ω co-planar waveguide (CPW) on the substrate is also demonstrated, showing low loss and low dispersion over the measured frequency range up to 40 GHz. The developed technology proves a viable solution to implementing silicon-based multi-chip modules (MCM) substrates for RF system-in-package (RF-SiP).     

基于ZigBee的搜救人员特征信息无线传输系统设计与应用

为了保证灾难现场搜救人员的自身安全,提出一种基于单片机和ZigBee技术的搜救人员特征信息无线传输新技术。着重了介绍了无线传输单元的设计原理、硬件组成以及实现方法。同时,提出了改善ZigBee传输距离的方法,使得传输距离大于100 m,速率达到50 kbit/s,可以较好地满足现场应用要求。