Surface effects on the Frenkel pair defects stability in the vicinity of the Si(001) surface

A systematic first-principles pseudo-potential study of the stability of tetrahedral Frenkel pairs generated in the vicinity of the silicon Si(001)-(2×1) surface is reported. The defect formation energies and associated structures are discussed. We demonstrate that vacancies that are generated close to the surface are subject to annihilation processes either through recombination of the Frenkel pairs or through surface amorphization. On the other hand, interstitials that are positioned on the subsurface exhibit specific behaviors compared to those located deeper inside the bulk Si. Calculations indicate that the tetrahedral interstitial is unstable when located close to the surface and it relaxes to form a split-110 (dumbbell) configuration. In deeper layers, the tetrahedral interstitial remains rarely stable; it relaxes to hexagonal or to fourfold-coordinated configurations. The defect formation energies are given as a function of surface–vacancy and interstitial–vacancy distances. Results indicate that the formation energy is considerably reduced as the interstitial approaches the surface.     

Growth and fabrication of AlGaN/GaN HEMT based on Si(1 1 1) substrates by MOCVD

AlGaN/GaN high electron mobility transistor (HEMT) hetero-structures were grown on the 2-in Si (1 1 1) substrate using metal-organic chemical vapor deposition (MOCVD). Low-temperature (LT) AlN layers were inserted to relieve the tension stress during the growth of GaN epilayers. The grown AlGaN/GaN HEMT samples exhibited a maximum crack-free area of 8 mm×5 mm, XRD GaN (0 0 0 2) full-width at half-maximum (FWHM) of 661 arcsec and surface roughness of 0.377 nm. The device with a gate length of 1.4 μm and a gate width of 60 μm demonstrated maximum drain current density of 304 mA/mm, transconductance of 124 mS/mm and reverse gate leakage current of 0.76 μA/mm at the gate voltage of −10 V.     

Capacitance-voltage analysis of InAs quantum dots grown on InAlAs/InP(0 0 1)

The electronic properties of InAs quantum dots (QDs) grown on InAlAs/InP(0 0 1) were studied by using capacitance-voltage (C-V) analysis and photoluminescence (PL) measurements. The level positions of electrons and holes could be studied separately by using n- and p-type InAlAs matrices, respectively. The holes are found to be more confined than electrons in these kinds of dots.     

Convex corners undercutting and rhombus compensation in KOH with and without IPA solution on (1 1 0) silicon

The present investigation introduces convex corners undercutting and results of rhombus compensation patterns in 40% aqueous KOH solution and in KOH saturated with isopropanol (IPA) solution. All experiments are carried out on (1 1 0) silicon at 70 °C. Undercuts take place on convex corners in both solutions. Moreover, the front etch planes governing undercut vary with solutions. Rhombus compensations are used to correct the undercut. Perfect acute corner without residue is obtained, and there are only some residue structures on both sides of obtuse convex corners in KOH with IPA solution, which are better results than those in pure aqueous KOH solution.     

Solid phase epitaxial growth of Dy-germanide films on Ge(0 0 1) substrates

Dy thin films are grown on Ge(0 0 1) substrates by molecular beam deposition at room temperature. Subsequently, the Dy film is annealed at different temperatures for the growth of a Dy-germanide film. Structural, morphological and electrical properties of the Dy-germanide film are investigated by in situ reflection high-energy electron diffraction, and ex situ X-ray diffraction, atomic force microscopy and resistivity measurements. Reflection high-energy electron diffraction patterns and X-ray diffraction spectra show that the room temperature growth of the Dy film is disordered and there is a transition at a temperature of 300-330 °C from a disordered to an epitaxial growth of a Dy-germanide film by solid phase epitaxy. The high quality Dy₃Ge₅ film crystalline structure is formed and identified as an orthorhombic phase with smooth surface in the annealing temperature range of 330-550 °C. But at a temperature of 600 °C, the smooth surface of the Dy₃Ge₅ film changes to a rough surface with a lot of pits due to the reactions further.     

Epitaxial growth of Dy2O3 thin films on epitaxial Dy-germanide films on Ge(0 0 1) substrates

Ultra-thin films of Dy are grown on Ge(0 0 1) substrates by molecular beam deposition near room temperature and immediately annealed for solid phase epitaxy at higher temperatures, leading to the formation of DyGe_x films. Thin films of Dy₂O₃ are grown on the DyGe_x film on Ge(0 0 1) substrates by molecular beam epitaxy. Streaky reflection high energy electron diffraction (RHEED) patterns reveal that epitaxial DyGe_x films grow on Ge(0 0 1) substrates with flat surfaces. X-ray diffraction (XRD) spectrum suggests the growth of an orthorhombic phase of DyGe_x films with (0 0 1) orientations. After the growth of Dy₂O₃ films, there is a change in RHEED patterns to spotty features, revealing the growth of 3D crystalline islands. XRD spectrum shows the presence of a cubic phase with (1 0 0) and (1 1 1) orientations. Atomic force microscopy image shows that the surface morphology of Dy₂O₃ films is smooth with a root mean square roughness of 10 Å.     

Growth mechanism of iron nanoparticles on (0 0 0 1) sapphire wafers

Laser ablation of a high purity (99.7%) iron target was used to accomplish the depositions of iron nanoparticles on the (0 0 0 1) face of single crystal sapphire wafers. The nanoparticles were characterized in situ by means of X-ray photoelectron spectroscopy (XPS). The growth mechanism was determined by applying the QUASES-Tougaard methodology to the extended part of the background intensity of the Fe KMM peak in XPS spectra. The heights of nanoparticles obtained are between 3.5 and 6.5 nm. In the first 150 laser pulses, the height of the nanoparticles remained constant while the coverage was increased.     

AFM observation of OMVPE grown ErP on InP (0 0 1), (1 1 1)A and (1 1 1)B substrates

ErP has been grown on InP (0 0 1), (1 1 1)A and (1 1 1)B substrates by low-pressure organometallic vapor-phase epitaxy. The morphological change with growth temperature has been explored by atomic force microscope. On all the substrates, ErP is grown in island structure. Height and area size of the ErP islands on (1 1 1)A substrate exhibit an obvious dependence on growth temperature. ErP islands grown at 540°C, that is the suitable temperature for ErP formation, gather to step edges to make wires.     

Formation speed of atomically flat surface on Si (1 0 0) in ultra-pure argon

The flattening speed of the low temperature atomically flattening technology is evaluated in order to apply atomically flat surface of (1 0 0) orientation on large-diameter silicon wafers to the LSI manufacturing. The atomically flatness of the whole surface of wafers with the diameter of 200 mm can be obtained after annealing at 800 °C or above. The process time required to obtain the atomically flatness for the whole wafer surface can be shortened by increasing the annealing temperature as well as by increasing the gas flow rate. With the off angle of 0.50° or below, it was found that only mono-atomic steps appear on the surfaces and the flattening speed is independent of the off angle. These indicate that the process speed is independent of the migration speed of Si atoms on the surface, but depends on the gas replacement efficiency near the Si surface in this technique.     

The structure of the Si (211) surface

Silicon (211) has been proposed as an alternative substrate for CdTe/HgCdTe molecular beam epitaxial growth. Silicon has a clear advantage over other substrates because of its low cost, high strength, and thermal-expansion coefficient, which matches that of the silicon readout integrated circuit. The (211) orientation has been shown to yield high-quality CdTe and HgCdTe/CdTe layers over other orientations. The reconstruction and faceting of the Si (211) surface is poorly understood despite the importance of the (211) orientation. The results of low-energy electron diffraction (LEED) studies have been contradictory, and their conclusions are inconsistent with recent scanning tunneling microscopy (STM) studies. LEED and STM images were used to determine the most probable Si (211) surface facet structure as a function of annealing temperature. Samples annealed at a high temperature (i.e., >1260°C) allowed the formation of ordered LEED spot patterns as opposed to the typically reported $[\bar 111]$ streaks. The pattern in the $[0\bar 11]$ direction gave a consistent 2× (7.68 Å) reconstruction.     

Effect of AlN buffer thickness on GaN epilayer grown on Si(1 1 1)

We studied the influence of high temperature AlN buffer thickness on the property of GaN film on Si (1 1 1) substrate. Samples were grown by metal organic chemical vapor deposition. Optical microscopy, atomic force microscopy and X-ray diffraction were employed to characterize the samples. The results demonstrated that thickness of high temperature AlN buffer prominently influenced the morphology and the crystal quality of GaN epilayer. The optimized thickness of the AlN buffer is found to be about 150 nm. Under the optimized thickness, the largest crack-free range of GaN film is 10 mm×10 mm and the full width at half maximum of GaN (0 0 0 2) rocking curve peak is 621.7 arcsec. Using high temperature AlN/AlGaN multibuffer combined with AlN/GaN superlattices interlayer we have obtained 2 μm crack-free GaN epilayer on 2 in Si (1 1 1) substrates.     

Influence of arsenic on the atomic structure of the Si(112) surface

The surface science techniques of low-energy electron diffraction (LEED), x-ray photoelectron spectroscopy (XPS), and scanning tunneling microscopy (STM) have been used to characterize the clean Si(112) surface and the influence of an As monolayer on the properties and structure of the surface. In agreement with previous studies, the clean surface is found by both LEEd and atomically resolved STM images to be unstable with respect to faceting into other stable planes. Procedures for in-situ deposition of As onto clean Si surfaces were devised and XPS results show that approximately one monolayer of As can be deposited free of any contamination. The As/Si(112) surface is characterized by a sharper LEED pattern than for the clean surface and by STM images characterized by long rows along the direction with a regular width of 1.9 nm. This is consistent with a doubling of the periodicity in the direction of the bulk-terminated unit cell. This implies that As yields a stable but reconstructed Si(112) surface.     

Electron tunneling in MIS capacitors with the MBE-grown fluoride layers on Si(1 1 1) and Ge(1 1 1): Role of transverse momentum conservation

The current-voltage characteristics of the metal-insulator-semiconductor tunneling structures with calcium fluoride are simulated using different theoretical models. The results are compared to the data of current measurements on the fabricated capacitors with 1-3 nm epitaxial fluorides. Best agreement is achieved imposing a condition of transverse momentum k_⊥ conservation for a tunneling electron. This fact may be treated as an experimental proof for the k_⊥ conservation in the examined high-quality structures which was not directly confirmed on more traditional structures with oxide dielectrics.     

Simulation of Nano Si and Al Wires Growth on Si(1O0) Surface

Growth of nano Si and Al wires on the Si(100) surfaces is investigated by computer simulation, including the anisotropic diffusion and the anisotropic sticking. The diffusion rates along and across the substrate dimer rows are different, so are the sticking probabilities of an adatom, at the end sites of existing islands or the side sites. Both one-dimensional wires of Si and Al are perpendicular to the dimer rows of the substrate, though the diffusion of Si adatoms is contrary to that of Al adatoms, i.e. Si adatoms diffuse faster along the dimer rows while Al adatoms faster across the dimer rows. The simulation results also show that the shape anisotropy of islands is due to the sticking anisotropy rather than the diffusion anisotropy,which is in agreement with the experiments.     

Simulation of Nano Si and Al Wires Growth on Si(1O0) Surface

Growth of nano Si and Al wires on the Si(100) surfaces is investigated by computer simulation, including the anisotropic diffusion and the anisotropic sticking. The diffusion rates along and across the substrate dimer rows are different, so are the sticking probabilities of an adatom, at the end sites of existing islands or the side sites. Both one-dimensional wires of Si and Al are perpendicular to the dimer rows of the substrate, though the diffusion of Si adatoms is contrary to that of Al adatoms, i.e. Si adatoms diffuse faster along the dimer rows while Al adatoms faster across the dimer rows. The simulation results also show that the shape anisotropy of islands is due to the sticking anisotropy rather than the diffusion anisotropy,which is in agreement with the experiments.     

Growth and structural properties of crystalline LaAlO3 on Si (0 0 1)

Crystalline LaAlO₃ was grown by oxide molecular beam epitaxy (MBE) on Si (0 0 1) surfaces utilizing a 2 ML SrTiO₃ buffer layer. This SrTiO₃ buffer layer, also grown by oxide MBE, formed an abrupt interface with the silicon. No SiO₂ layer was detectable at the oxide-silicon interface when studied by cross-sectional transmission electron microscopy. The crystalline quality of the LaAlO₃ was assessed during and after growth by reflection high energy electron diffraction, indicating epitaxial growth with the LaAlO₃ unit cell rotated 45° relative to the silicon unit cell. X-ray diffraction indicates a (0 0 1) oriented single-crystalline LaAlO₃ film with a rocking curve of 0.15° and no secondary phases. The use of SrTiO₃ buffer layers on silicon allows perovskite oxides which otherwise would be incompatible with silicon to be integrated onto a silicon platform.     

Spacer defined FinFET: Active area patterning of sub-20 nm fins with high density

We present a method to obtain Si-fins with a critical dimension (CD) below 20 nm, separated by a minimum distance of 25 nm and connected by a common source/drain (S/D) pad. The method comprises of recursive spacer defined patterning to quadruple the line density of a 350 nm pitch resist pattern defined by 193 nm lithography. Spacer defined patterning is combined with resist based patterning to simultaneously define fins and S/D pads in a Silicon on Insulator (SOI) film. CD and Line Width Roughness (LWR) analysis was done on top down SEM images taken in a center die and in an edge die of a 200 mm wafer. The average CD is 17 nm in the center of the wafer and 18 nm at the edge. The LWR is 3 nm for both center and edge. Additional process steps to remove etch damage and round the top corner of the fin (i.e. oxidation followed by H₂ anneal) further reduce the CD to 13 nm.     

Nucleation of ZnTe on the As-Terminated Si(112) Surface

We employ a suite of surface analysis techniques that probe the outermost ZnTe/As-Si(112) surface to generate an understanding of the initial stages of the heteroepitaxial HgCdTe/CdTe/ZnTe/As-Si(112) layer formation. Ion scattering spectroscopy (ISS), reflection-high energy electron diffraction (RHEED), along with nondestructive depth profiles by angle-resolved x-ray photoelectron spectroscopy (XPS) are successfully applied to clarify and support the nucleation stages of ZnTe formation on the As-terminated Si(112) substrate. Data indicate a slow growth of the first ZnTe layer. In addition, no evidence of thick ZnTe island formation exists. The current ZnTe formation process generates full coverage on the Si(112) surface after six to nine MBE cycles. In order to fully understand the details of the ZnTe nucleation process on the Si(112) substrate, we present an inelastic background analysis with the Tougaard method to study surface morphology.     

Structural and electrical properties of Er-doped HfO2 and of its interface with Ge (0 0 1)

Er-doped HfO₂ thin films with Er content ranging from 0% to 15% are deposited by atomic layer deposition on native oxide free Ge(001). The crystallographic phase is investigated by X-ray diffraction and is found to depend on the Er%. The cubic fluorite structure develops on Ge for Er% as low as 4% and is stable after annealing at 400 °C in N₂. Microstrain increases with increasing the Er content within the fluorite structure. Time of flight secondary ion mass and electron energy loss spectroscopy evidence a Ge diffusion from the substrate that results in the formation of a Ge-rich interfacial region which does not present a structural discontinuity with the oxide. The diffusion of Ge is enhanced by the annealing and causes a reordering of the crystal lattice. In annealed films the interface defect density measured by low temperature conductance measurements is found to decrease with decreasing the Er content.     

Growth and characterization of ZnO nanowires grown on the Si(1 1 1) and Si(1 0 0) substrates: Optical properties and biaxial stress of nanowires

In this paper the effects of silicon substrates with different orientations on the morphological and optical properties as well as biaxial stress of ZnO nanowires were investigated. The ZnO nanowires were grown on Si(1 0 0) and Si(1 1 1) substrates by the vapor–solid (VS) method using a physical vapor deposition reactor. In addition ZnO nanowires were grown on Si(1 1 1) substrate by the vapor–liquid–solid (VLS) method using an Au film as catalyst, which were deposited on Si(1 1 1) substrate using a sputtering method, with the same conditions. Room temperature photoluminescence (PL) spectrum showed a stronger ultraviolet (UV) peak at 381 nm for the nanowires that were grown on Si(1 1 1) by the VS method than those that were grown on Si(1 0 0) with the same green emission (deep-level emission (DLE)) intensities at about 520 nm peak. On the other hand, the PL result of the ZnO nanowires, which were grown by the VLS method, showed the same intensities for the both UV and DLE peaks. Furthermore, the effects of silicon substrate orientation and Au catalyst on biaxial stress of the nanowires were studied by Raman spectrometer. It was discussed that Au catalyst was one of the important factors that could affect the biaxial stress value of the ZnO nanowires that were grown on Si substrates.