Multilevel charge storage in Si nanocrystals arranged in double-dot-layers within SiO2

We investigated charging/discharging characteristics of a MOS structure with two layers of Si-nanocrystals (NCs) embedded in the SiO₂ dielectric. The two-dimensional (2D) arrays of nanocrystals, of sizes 3 and 5 nm in the lower and upper NCs layer, respectively, were fabricated by low pressure chemical vapor deposition (LPCVD) of amorphous Si (a-Si), followed by oxidation/annealing. The tunnel oxide was 3.5 nm thick. Successive charging of the NCs layers by both electrons and holes injected from the substrate was clearly demonstrated by the observed steps in the flatband voltage shift (ΔV_FB) as a function of the applied positive (electrons) or negative (holes) pulses on the gate, thus opening the potential for multiple bit operation of the memory. Discharging of the structure by pulses of opposite sign was consistently obtained. The current-voltage (I-V) curves exhibited two transient peaks at voltages corresponding to the two steps in ΔV_FB vs. V_gate that were attributed to a displacement current from the substrate to the nanocrystal layers. Clear improvement of charge retention in the double-nanocrystal layer structure compared to the single one was obtained, opening the possibility for lowering the gate oxide thickness of the NC memory without compromising device reliability.     

Nitrogen doped multilayer photo catalytically reduced graphene oxide floating gate: Al/PMMA/NrGO/SiO2/p–Si/Au based hybrid gate stack for non volatile memory applications

Photo catalytically assisted, multi–layer nitrogen doped reduced graphene oxide (ML–NrGO) is investigated as a promising charge storage layer in Al/PMMA/NrGO/SiO₂/p–Si/Au structure. A considerable memory window (ΔW) of ∼3.3 V at ± 7 V sweep voltage and long data retention upto ∼ 10⁵ s is demonstrated as an encouraging candidature for emerging memory hierarchies. The clockwise hysteresis supports the hole charge trapping mechanism in the NrGO based structure. The ML–NrGO memory devices provide the rapid programming, saturation of the program transients, store more data at less cost and reduced ballistic transport in the plane perpendicular to NrGO. The facile, solution processable, cost effective device processing and stable retention of the fabricated ML–NrGO based Al/PMMA/NrGO/SiO₂/p–Si/Au flash memory structures proves to be a potential alternative for existing EEPROM based embedded applications and also for commercial scale production of flash memory based on flexible organic electronics.     

Role of tunneling layer in graphene-oxide based organic nonvolatile memory transistors

This paper demonstrates non-volatile memory transistor using solution processable graphene oxide (GO) as charge storage nodes in the configuration, p⁺⁺Si/SiO₂/GO/Tunneling layer/Pentacene/Au. The tunneling layers are polymethylmethacrylate (PMMA) and polyvinylphenol (PVP). GO film could be deposited as single layered flakes with a uniform distribution using spin coating technique. The devices with PMMA as charge tunneling layer exhibited higher mobility and on/off ratio than PVP based devices. The devices show a large positive threshold voltage shift (∼24 V for PMMA and ∼15 V for PVP) from initial value during programming at gate voltage of +80 V kept for 10 s. The transfer curves can be restored approximately to its initial condition by applying an erasing voltage of −30 V for 10 s for both the devices. Since such a large shift is not observed without GO layer, we consider that memory effect was due to electron trapping in GO. Further, retention of the initial memory window was measured to be 63% and 37% after 3000 s for PMMA and PVP based devices, respectively.     

Stack engineering of TANOS charge-trap flash memory cell using high-κ ZrO2 grown by ALD as charge trapping layer

ZrO₂ with a κ value of 30 grown by atomic layer deposition has been integrated as charge trapping layer alternative to Si₃N₄ in TANOS-like memory capacitors, with Al₂O₃ as blocking oxide, SiO₂ as tunnel oxide and TaN metal gate. The fabricated device featuring 24 nm ZrO₂ exhibits efficient program and erase operations under Fowler-Nordheim tunneling when compared to a Si₃N₄ based reference device with similar EOT and fabricated under the same process conditions. The effect of stack thermal budget (900-1030 °C range) on memory performance and reliability is investigated and correlated with physical analyses. Finally, scaling ZrO₂ down to 14 nm allows program and erase at lower voltages, even if the trapping efficiency and retention of these device need further improvements for the integration of ZrO₂ in next generation charge trapping nonvolatile memories.     

Improved performance by using TaON/SiO2 as dual tunnel layer in Charge-Trapping nonvolatile memory

Tunneling–barrier engineered stacks with different high-κ dielectrics are investigated by fabricating the stacked structures of Al/Al₂O₃/HfLaON/ (TaON/SiO₂)/Si and Al/Al₂O₃/HfLaON/ (HfON/SiO₂)/Si. As compared to the device with HfON/SiO₂ dual tunnel layer (DTL), the one with TaON/SiO₂ DTL shows larger memory window (3.85 V at ± 13 V/1 s), higher program/erase speeds (1.85 V/−2.00 V at ± 12 V/100 μs), better endurance (window narrowing rate of 5.7% after 10⁵ cycles). The main mechanisms involved lie in (1) the higher dielectric constant of TaON which induces high electric field in the SiO₂ layer, (2) the smaller conduction/valence-band offsets between TaON and the Si substrate, and (3) better interface quality with SiO₂. Furthermore, compared with SiO₂ single tunnel layer, better retention characteristics can be achieved for the TaON/SiO₂ DTL due to its larger thickness.     

Growth ambient on memory characteristics in Au nanoclusters embedded in high-k dielectric as novel non-volatile memory

In this work, we report on the findings of the effects of different ambient on memory characteristics of a floating gate memory structure containing HfAlO control gate, self-organized Au nanoclusters (NCs), and a HfAlO tunnel layer deposited by the pulsed-laser deposition. The optimized fabrication environment has been found and stored charge density up to 10¹³ cm⁻² has been achieved. As the sizes of the Au NCs are smaller than 4 nm, they may be potentially used in multilayer-structured multi-bit memory cell.     

Low operational voltage and high performance organic field effect memory transistor with solution processed graphene oxide charge storage media

Low voltage organic field effect memory transistors are demonstrated by adapting a hybrid gate dielectric and a solution processed graphene oxide charge trap layer. The hybrid gate dielectric is composed of aluminum oxide (AlO_x) and [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) plays an important role of both preventing leakage current from gate electrode and providing an appropriate surface energy to allow for uniform spin-casting of graphene oxide (GO). The hybrid gate dielectric has a breakdown voltage greater than 6 V and capacitance of 0.47 μF/cm². Graphene oxide charge trap layer is spin-cast on top of the hybrid dielectric and has a resulting thickness of approximately 9 nm. The final device structure is Au/Pentacene/PMMA/GO/PhO-19-PA/AlO_x/Al. The memory transistors clearly showed a large hysteresis with a memory window of around 2 V under an applied gate bias from 4 V to −5 V. The stored charge within the graphene oxide charge trap layer was measured to be 2.9 × 10¹² cm⁻². The low voltage memory transistor operated well under constant applied gate voltage and time with varying programming times (pulse duration) and voltage pulses (pulse amplitude). In addition, the drain current (I_ds) after programming and erasing remained in their pristine state after 10⁴ s and are expected to be retained for more than one year.     

A study on the improved programming characteristics of flash memory with Si3N4/SiO2 stacked tunneling dielectric

The programming characteristics of memories with different tunneling-layer structures (Si₃N₄, SiO₂ and Si₃N₄/SiO₂ stack) dielectrics are investigated using 2-D device simulator of MEDICI. It is theoretically confirmed that the memory with the SiO₂/Si₃N₄ stacked tunneling layer exhibits better programming characteristics than ones with single tunneling layer of SiO₂ or Si₃N₄ for programming by channel hot electron (CHE) injection. A 10-μs programming time with a threshold-voltage shift of 5 V can be obtained for the memory with SiO₂/Si₃N₄ stacked tunneling layer at V_cg = 10 V and V_ds = 3.3 V. This is attributed to the fact that the floating-gate voltage is close to drain voltage for the stacked tunneling dielectric (TD), and thus the CHE injection current is the largest. Furthermore, optimal substrate concentration is determined to be 5 × 10¹⁶–2 × 10¹⁷ cm⁻³, by considering a trade-off between the programming characteristics and power dissipation/lifetime of the devices. Lastly, the effects of interface states on the programming characteristics are investigated. Low interface-state density gives short programming time and small post-programming control-gate current.     

Improved retention characteristic of charge-trapped flash device with sealing layer/Al2O3 or Al2O3/high-k stacked blocking layers

Although programming and erase speeds of charge trapping (CT) flash memory device are improved by using Al₂O₃ as blocking layer, its retention characteristic is still a main issue. CT flash memory device with Al₂O₃/high-k stacked blocking layer is proposed in this work to enhance data retention. Moreover, programming and erase speeds are slightly improved. In addition, sealing layer (SL), which is formed by an advanced clustered horizontal furnace between charge trapping layer and Al₂O₃ as one of the blocking layers is also studied. The retention characteristic is enhanced by SL approach due to lower gate leakage current with less defect. With the combination of SL and Al₂O₃/high-k stacked blocking layer approaches, retention property can be further improved.     

Improved characteristics for Pd nanocrystal memory with stacked HfAlO–SiO2 tunnel layer

Stacked HfAlO-SiO₂ tunnel layers are designed for Pd nanocrystal nonvolatile memories. For the sample with 1.5 nm-HfAlO/3.5 nm-SiO₂ tunnel layer, a smaller initial memory window is obtained compared to the sample with 3.5 nm-HfAlO/1.5 nm-SiO₂ tunnel layer. Owing to the thermally induced traps in HfAlO-SiO₂ films are located at a farther distance from the Si substrate and more effective blocking of charge leakage by asymmetric tunnel barrier, a larger final memory window and better retention characteristic can be obtained for Al/blocking oxide SiO₂/Pd NCs/1.5 nm-HfAlO/3.5 nm-SiO₂/Si structure. A N₂ plasma treatment can further improve the memory characteristics. Better memory characteristics can be obtained for Pd-nanocrystal-based nonvolatile memory with an adequate thickness ratio of HfAlO to SiO₂.     

Investigation of charge-trap memories with AlN based band engineered storage layers

This paper presents the investigation of the electrical properties of charge-trap memories with AlN based storage layers. The memory performance and reliability are studied in details and compared with the ones of a reference device using standard Si₃N₄ as storage layer. An engineered charge trapping layer is also proposed, made by an AlN/Si₃N₄ double layer, which shows reduced program/erase voltages, combined with 10⁶ excellent endurance and good retention (ΔV_T > 5 V after 10 years at 125 °C).     

Characteristics of metal-ferroelectric-insulator-semiconductor structure using Sr0.8Bi2.2Ta2O9 and Sr0.8Bi2.2Ta2O9-BaZrO3 for ferroelectric gates

Characteristics of BaZrO₃ (BZO) modified Sr_0.8Bi_2.2Ta₂O₉ (SBT) thin films fabricated by sol-gel method on HfO₂ coated Si substrates have been investigated in a metal-ferroelectric-insulator-semiconductor (MFIS) structure for potential use in a ferroelectric field effect transistor (FeFET) type memory. MFIS structures consisting of pure SBT and doped with 5 and 7 mol% BZO exhibited memory windows of 0.81, 0.82 and 0.95 V with gate voltage sweeps between −5 and +5 V, respectively. Leakage current density levels of 10⁻⁸ A/cm² for BZO doped SBT gate materials were observed and attributed to the metallic Bi on the surface as well as intrinsic defects and a porous film microstructure. The higher than expected leakage current is attributed to electron trapping/de-trapping, which reduces the data retention time and memory window. Further process improvements are expected to enhance the electronic properties of doped SBT for FeFET.     

Effect of biasing at elevated temperature on the electronic structure of Pt/HfO2/Si stacks

The spatial distribution of charges in a Pt/HfO₂/Si stack has been manipulated by applying a cyclic bias voltage ±2.5 V in combination with moderate (T ∼ 630 K) heating. The modifications were monitored in situ by room temperature capacitance-voltage (C-V) and current-voltage (I-V) measurements and analyzed ex situ by hard X-ray photoelectron spectroscopy which additionally provides information on possible chemical changes at the interfaces. The experimental data on the charge/potential distributions resulting from the different steps of bias-temperature stress (BTS) are consistent with the model that additional oxygen vacancies, which are generated in HfO₂ and positively charged by charge transfer across the interface with a high work function metal (Pt), are driven across the HfO₂ layer. These vacancies ultimately control the observed growth/dissolution of SiO_x at the bottom interface upon negative/positive BTS, respectively.     

Measurements and modelling of thermal step current in GaN/SiO2/Si structure

In this work, we report results of measurement of space charge in GaN/SiO₂/Si structure by means of thermal step method (TSM) and capacitance-voltage (C-V). TSM is a non destructive method for quantifying and localizing the electric charges in insulating materials. Its principle consists to apply a low thermal step to a short-circuited or dc-biased sample and to record a current response, which depends on the charge present in the device. The C-V characteristics show an almost metal-oxide-semiconductor (MOS) behaviour and retention of charges after forward bias sweeping. The space charge dynamics in the structure are followed under low applied dc voltages. Results show a significant inversion of the TSM currents above applied voltage of 200 mV. A theoretical model is then presented in order to estimate the amount of the trapped charges and to interpret the variation of the TS currents as a function of the applied gate voltages.     

Enhanced charge storage characteristics by ZrO2 nanocrystallites precipitated from amorphous (ZrO2)0.8(SiO2)0.2 charge trapping layer

Charge trapping memory capacitors using (ZrO₂)_0.8(SiO₂)_0.2 film as charge trapping layer and amorphous Al₂O₃ as the tunneling layer and blocking layer were fabricated for nonvolatile semiconductor memory application. The ZrO₂ nanocrystallites with a size of 3–5 nm precipitated from amorphous (ZrO₂)_0.8(SiO₂)_0.2 during rapid thermal annealing at 800 °C can serve as the storage nodes, with which a large hysteresis memory window of 7.5 V at a sweeping gate voltage of 8 V has been achieved. At 150 °C bake temperature, the memory capacitor exhibited an excellent endurance up to 10⁵ write/erase cycles, after which a small charge loss of about 12% was achieved.     

Investigation of atomic vapour deposited TiN/HfO2/SiO2 gate stacks for MOSFET devices

HfO₂ films were grown by atomic vapour deposition (AVD) on SiO₂/Si (1 0 0) substrates. The positive shift of the flat band voltage of the HfO₂ based metal-oxide-silicon (MOS) devices indicates the presence of negative fixed charges with a density of 5 × 10¹² cm⁻². The interface trap charge density of HfO₂/SiO₂ stacks can be reduced to 3 × 10¹¹ eV⁻¹ cm⁻² near mid gap, by forming gas annealing. The extracted work function of 4.7 eV preferred the use of TiN as metal gate for PMOS transistors. TiN/HfO₂/SiO₂ gate stacks were integrated into gate-last-formed MOSFET structures. The extracted maximum effective mobility of HfO₂ based PMOS transistors is 56 cm²/Vs.     

Comparison of electrical stress-induced charge carrier generation/trapping and related degradation of SiO2 and HfO2/SiO2 gate dielectric stacks

We compare charge carrier generation/trapping related degradation in control oxide (SiO₂) and HfO₂/SiO₂ stack of an identical equivalent-oxide-thickness (EOT) during constant gate voltage stress of n-type metal-oxide-semiconductor (nMOS) capacitors. Irrespective of these two dielectrics, the kinetics of generation of both surface states and oxide-trapped positive charges are found to be similar. Our analysis shows that the positive oxide charge buildup during CVS is due to trapping of protons by the strained SiOSi bonds in either of the devices. We demonstrate that compared to SiO₂ devices, HfO₂ devices with an equal EOT better perform in CMOS logic applications. On the other hand, our results indicate that the control oxide is better in charge trapping memory devices. Furthermore, the lifetime of the control oxide devices is observed longer than that of HfO₂ devices at a given operating voltage.     

Drain current enhancement and negligible current collapse in GaN MOSFETs with atomic-layer-deposited HfO2 as a gate dielectric

Accumulation-type GaN metal-oxide-semiconductor field-effect-transistors (MOSFET’s) with atomic-layer-deposited HfO₂ gate dielectrics have been fabricated; a 4 μm gate-length device with a gate dielectric of 14.8 nm in thickness (an equivalent SiO₂ thickness of 3.8 nm) gave a drain current of 230 mA/mm and a broad maximum transconductance of 31 mS/mm. Owing to a low interfacial density of states (D_it) at the HfO₂/GaN interface, more than two third of the drain currents come from accumulation, in contrast to those of Schottky-gate GaN devices. The device also showed negligible current collapse in a wide range of bias voltages, again due to the low D_it, which effectively passivate the surface states located in the gate-drain access region. Moreover, the device demonstrated a larger forward gate bias of +6 V with a much lower gate leakage current.     

Constant current stress-induced leakage current in mixed HfO2-Ta2O5 stacks

The electrical characteristics of HfO₂-Ta₂O₅ mixed stacks under constant current stress (CCS) at gate injection with 20 mA/cm² and stressing times of 50 and 200 s have been investigated. A very weak effect of the stress on the global dielectric constant, on fast and slow states in the stack as well as on the dominant conduction mechanism is detected. The most sensitive parameter to the CCS is the leakage current. The stress-induced leakage current (SILC) is voltage and thickness dependent. The pre-existing traps govern the trapping kinetics and are a key parameter to evaluate the stress response. Two processes - positive charge build-up and new bulk traps generation - are suggested to be responsible for SILC: the domination of one of them depends on both the film thickness and the stressing time. The positive charge build-up is localized close to the gate electrode implying gate-induced defects could be precursors for it. It is established that unlike the case of single SiO₂ layer, the bulk traps closer to the gate electrode control SILC in the mixed Ta₂O₅-HfO₂-based capacitors.     

Organic nonvolatile memory transistors based on fullerene and an electron-trapping polymer

We report for the first time organic n-type nonvolatile memory transistors based on a fullerene (C₆₀) semiconductor and an electron-trapping polymer, poly(perfluoroalkenyl vinyl ether) (CYTOP). The transistors with a Si++/SiO₂/CYTOP/C₆₀/Al structure show good n-type transistor performance with a threshold voltage (V_th) of 2.8 V and an electron mobility of 0.4 cm² V⁻¹ s⁻¹. Applying gate voltages of 50 or −45 V for about 0.1 s to the devices induces the reversible shifts in their transfer characteristics, which results in a large memory window (ΔV_th) of 10 V. A memory on/off ratio of 10⁵ at a small reading voltage below 5 V and a retention time greater than 10⁵ s are achieved. The memory effect in the transistor is ascribed to electrons trapped at the CYTOP/SiO₂ interface. Because of the use of high-electron-mobility C₆₀, the switching voltages of our memory transistors become significantly lower than those of conventional memory transistors based on pentacene.