先进CMOS器件中poly-Si/TaN/HfSiON栅结构的干法刻蚀研究

研究了先进CMOS器件中poly-Si/TaN/HfSiON栅结构的干法刻蚀工艺。对于poly-Si/TaN/HfSiON栅结构的刻蚀,我们采用的策略是对栅叠层中的每一层都进行高选择比地、陡直地刻蚀。首先,对于栅结构中poly-Si的刻蚀,开发了一种三步的等离子体刻蚀工艺,不仅得到了陡直的poly-Si刻蚀剖面而且该刻蚀可以可靠地停止在TaN金属栅上。然后,为了得到陡直的TaN刻蚀剖面,研究了多种BCl3基刻蚀气体对TaN金属栅的刻蚀,发现BCl3/Cl2/O2/Ar等离子体是合适的选择。而且,考虑到Cl2对Si衬底几乎没有选择比,采用优化的BCl3/Cl2/O2/Ar等离子体陡直地刻蚀掉TaN金属栅以后,我们采用BCl3/Ar等离子体刻蚀HfSiON高K介质,改善对Si衬底的选择比。最后,采用这些新的刻蚀工艺,成功地实现了poly-Si/TaN/HfSiON栅结构的刻蚀,该刻蚀不仅得到了陡直的刻蚀剖面且对Si衬底几乎没有损失。     

Dry etching of poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor devices

A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor（CMOS） devices is investigated.Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile.First,a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate.Then different BCl₃-based plasmas are applied to etch the TaN metal gate and find that BCl₃/Cl₂/O₂/Ar plasma is a suitable choice to get a vertical TaN profile.Moreover,considering that Cl₂ almost has no selectivity to Si substrate, BCl₃/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl₃/Cl₂/O₂/Ar plasma.Finally,we have succeeded in etching a poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.     

Plasma Etching for Sub-45-nm TaN Metal Gates on High-k Dielectrics

Etching of TaN gates on high-k dielectrics (HfO₂ or HfAlO) is investigated using HBr/Cl₂ chemistry in a decoupled plasma source (DPS). The patterning sequence includes 248-nm lithography, plasma photoresist trimming, etching of a SiN-SiO₂ hard mask, and photoresist stripping, followed by TaN etching. TaN etching is studied by design of experiment (DOE) with four variables using a linear model with interactions. It is found that at a fixed substrate temperature and wafer chuck power, etch critical dimensions (CD) gain decreases with decreasing HBr/Cl₂ flow rate ratio and pressure and with increasing source power and total gas flow rate. Based on these DOE findings, subsequent optimization is performed and a three-step etching process is developed; a main feature of the process is progressively increasing HBr/Cl₂ flow rate ratio. The optimized process provides etch CD gain within 2 nm and gate profile close to vertical and reliable etch-stop on high-k dielectric. This process is successfully applied to the fabrication of the 40-nm HfAlO/TaN gate stack p-MOSFETs with good electrical parameters     

以非晶硅为硬掩膜的TaN金属栅的选择性湿法腐蚀

提出了一种在HfSiON介质上,采用非晶硅为硬掩膜的选择性去除TaN的湿法腐蚀工艺。由于SC1(NH4OH:H2O2:H2O)对金属栅具有合适的腐蚀速率且对硬掩膜和高K材料的选择比很高,所以选择它作为TaN的腐蚀溶液。与光刻胶掩膜和TEOS硬掩膜相比,因非晶硅硬掩膜不受SC1溶液的影响且很容易用NH4OH溶液去除（NH4OH溶液对TaN和HfSiON薄膜无损伤）,所以对于在HfSiON介质上实现TaN的选择性去除来说非晶硅硬掩膜是更好的选择。另外,在TaN金属栅湿法腐蚀和硬掩膜去除后, 高K介质的表面是光滑的,这可防止器件性能退化。因此,采用非晶硅为硬掩膜的TaN湿法腐蚀工艺可以应用于双金属栅集成,实现先淀积的TaN金属栅的选择性去除。     

Carrier separation analysis for clarifying carrier conduction and degradation mechanisms in high-k stack gate dielectrics

The carrier conduction and the degradation mechanism in n⁺gate p-channel metal-insulator-semiconductor field-effect-transistors with HfAlO_X (Hf: 60 at.%, Al: 40 at.%)/SiO₂ dielectric layers have been investigated using carrier separation method. Since gate current depends on substrate bias and both electron and hole currents are independent of temperature over the range of 25–150 °C, the conduction mechanism for both currents is controlled by a tunneling process. As the interfacial SiO₂ layer (IL) thickness increases in a fixed high-k layer thickness (T_high-k), a dominant carrier in the leakage current changes from hole to electron around 2.2-nm-thick IL. This is due to an asymmetric barrier height for electrons and holes at the SiO₂/Si interface. On the contrary, in the case of a fixed IL thickness of 1.3 nm, the hole current is dominant in the leakage current, regardless of T_high-k. It is shown that the dominant carrier in the leakage current depends on the structure of the high-k stack. Both electron and hole currents for the stress-induced-leakage-current (SILC) state increase slightly relative to the initial currents, which means that the trap generation in the high-k stack occurs near both the conduction band edge of n⁺poly-Si gate and the valence band edge of Si substrate. The electron current at soft breakdown (SBD) state dramatically increases over that for the SILC state, while the hole currents for both the SILC state and SBD are almost the same. This indicates that the defect sites generated in the high-k stack after SBD are located at energies near the conduction band edge of n⁺poly-Si gate. Both the defect generation rate and the defect size in the HfAlO_X/SiO₂ stacks are large compared with those in SiO₂. It is inferred that, in high-k dielectric stack, the defect generation mainly occurs in the high-k side rather than the IL side, and the defect size larger than the case of SiO₂ could be related to a larger dielectric constant of the high-k layer.     

Etching characteristics of ZnO thin films in chlorine-containing inductively coupled plasmas

This study examined the plasma etching characteristics of ZnO thin films etched in BCl₃/Ar, BCl₃/Cl₂/Ar and Cl₂/Ar plasmas with a positive photoresist mask. The ZnO etch rates were increased in a limited way by increasing the gas flow ratio of the main etch gases in the BCl₃/Ar, BCl₃/Cl₂/Ar and Cl₂/Ar plasmas at a fixed dc self-bias voltage (V_dc). However, the ZnO etch rate was increased more effectively by increasing the V_dc. Optical emission spectroscopy (OES) and X-ray photoelectron spectroscopy (XPS) analyses of the ZnO surfaces etched at various Cl₂/(Cl₂ + Ar) mixing ratios revealed the formation of the ZnO_xCl_y reaction by-products as a result of the increased etch rate with increasing Cl₂ addition, compared with 100% Ar⁺ sputter etching. This suggests that at Cl₂/Ar flow ratios ⩾20%, the ZnO etch process is controlled by an ion-assisted removal mechanism where the etch rate is governed by the ion-bombardment energy under the saturated chlorination conditions.     

Effect of dry etching on surface properties of III-nitrides

Dry etched InAlN and GaN surfaces have been characterized by current-voltage measurement, Auger electron spectroscopy, and atomic force microscopy. Electron cyclotron resonance discharges of BCl₃. BCl₃/Ar, BCl₃/N₂, or BCl₃/N₂ plus wet chemical etch all produce nitrogen surfaces that promote leakage current in rectifying gate contacts, with the BCl₃/N₂ plus wet chemical etch producing the least disruption on the surface properties. The conductivity of the immediate InAlN or GaN surface can be increased by preferential loss of N during BCl₃ plasma etching, leading to poor rectifying contact characteristics when the gate metal is deposited on this etched surface. Careful control of plasma chemistry, ion energy, and stoichiometry of the etched surface are necessary for acceptable pinch-off characteristics. Hydrogen passivation during the etch was also studied.     

A study of the role of HBr and oxygen on the etch selectivity and the post-etch profile in a polysilicon/oxide etch using HBr/O2 based high density plasma for advanced DRAMs

The role of HBr and oxygen on the etch selectivity and the post-etch profile in a polysilicon/oxide etch using HBr/O₂ based high density plasma was studied. HBr/O₂-based polysilicon etch process used in this study seems to be highly selective to the underlying oxide and produce a dielectric fill-friendly post-etch profile depending on the flow rates of HBr and oxygen. When appropriate amounts of HBr and oxygen (∼30 sccm of HBr and ∼3 sccm of oxygen) are present in the etch plasma, brominated silicon oxide seems to be deposited on the original gate oxide and the gate stack sidewall from the reaction of SiBr_x (reaction product during polysilicon etch step) and oxygen during the HBr/O₂-based oxide etch process. The deposited brominated oxide on the thin gate oxide seems to make the HBr/O₂-based plasma etch process extremely selective to the thin gate oxide by protecting the underlying gate oxide. The deposited brominated oxide on the gate stack sidewall seems to prevent the notching by protecting the sidewall during gate stack etching. The etch rate of the brominated oxide seems to be much faster than that of the thermal oxide during the 200:1 diluted HF cleaning. However, the deposited brominated oxide on the thin gate oxide and the gate stack sidewall during the plasma etching survived the following 1 min 200:1 diluted HF cleaning, as was observed in a TEM micrograph (Fig. 2(a)).     

Electron cyclotron resonance plasma etching of materials for magneto-resistive random access memory applications

Dry etching of multilayer magnetic thin film materials is necessary for the development of sensitive magnetic field sensors and memory devices. The use of high ion density electron cyclotron resonance (ECR) plasma etching for NiFe, NiFeCo, TaN, and CrSi in SF₆/Ar, CH₄/H₂/Ar, and Cl₂/Ar plasmas was investigated as a function of microwave source power, rf chuck power, and process pressure. All of the plasma chemistries are found to provide some enhancement in etch rates relative to pure Ar ion milling, while Cl₂/Ar provided the fastest etch rate for all four materials. Typical etch rates of 3000Å/min were found at high microwave source power. Etch rates of these metals were found to increase with rf chuck power and microwave source power, but to decrease with increasing pressure in SF₆/Ar, CH₄/H₂/Ar, and Cl₂/Ar. A significant issue with Cl₂/Ar is that it produces significant metal-chlorine surface residues that lead to post-etch corrosion problems in NiFe and NiFeCo. However, the concentration of these residues may be significantly reduced by in-situ H₂ or O₂ plasma cleaning prior to removal of the samples from the etch reactor.     

Hot carrier effects in n-MOSFETs with SiO2/HfO2/HfSiO gate stack and TaN metal gate

Charge trapping and trap generation in field-effect transistors with SiO₂/HfO₂/HfSiO gate stack and TaN metal gate electrode are investigated under uniform and non-uniform charge injection along the channel. Compared to constant voltage stress (CVS), hot carrier stress (HCS) exhibits more severe degradation in transconductance and subthreshold swing. By applying a detrapping bias, it is demonstrated that charge trapping induced degradation is reversible during CVS, while the damage is permanent for hot carrier injection case.     

TiN/TaN 厚度变化对nMOSCAP栅叠层有效功函数的影响

We evaluated the TiN/TaN/TiA1 triple-layer to modulate the effective work function （EWF） of a metal gate stack for the n-type metal-oxide-semiconductor （NMOS） devices application by varying the TiN/TaN thickness. In this paper, the effective work function of EWF ranges from 4.22 to 4.56 eV with different thicknesses of TiN and TaN. The thinner TiN and/or thinner in situ TaN capping, the closer to conduction band of silicon the EWF is, which is appropriate for 2-D planar NMOS. Mid-gap work function behavior is observed with thicker TiN, thicker in situ TaN capping, indicating a strong potential candidate of metal gate material for replacement gate processed three-dimensional devices such as FIN shaped field effect transistors. The physical understandings of the sensitivity of EWF to TiN and TaN thickness are proposed. The thicker TiN prevents the A1 diffusion then induces the EWF to shift to mid-gap. However, the TaN plays a different role in effective work function tuning from TiN, due to the Ta-O dipoles formed at the interface between the metal gate and the high-k layer.     

Comparison of ECR plasma chemistries for etching of InGaP and AlGaP

Etch rates for InGaP and AlGaP are examined under electron cyclotron resonance (ECR) conditions in Cl₂/Ar, BCl₃/Ar, BCl₃/N₂, ICl/Ar, and IBr/Ar discharges. All the plasmas except IBr/Ar provide rapid etching of InGaP at rates above 1 μm min⁻¹. ICl/Ar provides the highest etch rates. Unlike the Cl₂/Ar and BCl₃-based chemistries, the rates in ICl/Ar and IBr/Ar are almost independent of microwave power in the range 400–1000 W. Much lower rates were obtained for AlGaP in every discharge due to the greater difficulties in bond breaking that must precede formation and desorption of the etch products.     

Etch damage evaluation on (Bi4−xLax)Ti3O12 thin films during the etch process using inductively coupled plasma sources

The etching mechanism of (Bi_4−xLa_x)Ti₃O₁₂ (BLT) thin films in Ar/Cl₂ inductively coupled plasma (ICP) and plasma-induced damages at the etched surfaces were investigated as a function of gas-mixing ratios. The maximum etch rate of BLT thin films was 50.8 nm/min of 80% Ar/20% Cl₂. From various experimental data, amorphous phases on the etched surface existed on both chemically and physically etched films, but the amorphous phase was thicker after the 80% Ar/20% Cl₂ process. Moreover, crystalline “breaking” appeared during the etching in Cl₂-containing plasma. Also the remnant polarization and fatigue resistances decreased more for the 80% Ar/20% Cl₂ etch than for pure Ar plasma etch.     

金属栅/高k基FinFET研究进展

对比传统的平面型晶体管,总结了三维立体结构FinFET器件的结构特性。结合MOS器件栅介质材料研究进展,分别从纯硅基、多晶硅/高k基以及金属栅/高k基三个阶段综述了Fin-FET器件的发展历程,分析了各阶段FinFET器件的材料特性及其在等比缩小时所面临的关键问题,并着重从延迟时间、可靠性和功耗三方面分析了金属栅/高k基FinFET应用于22 nm器件的性能优势。基于短沟道效应以及界面态对器件性能的影响,探讨了FinFET器件尺寸等比缩小可能产生的负面效应及其解决办法。分析了FinFET器件下一步可能的发展方向,主要为高迁移率沟道材料、立体型栅结构以及基于新原理的电子器件。     

高k栅介质的可靠性问题

随着集成电路特征尺寸的不断缩短,利用先进的高k/金属栅堆叠来取代传统的SiO2/多晶硅栅结构成为微电子技术发展的必然,确保这些新的栅极堆叠类型具有足够的可靠性是非常重要的.综述了高k栅介质可靠性的研究现状,阐明了瞬态充电效应导致的阈值电压不可靠问题,对偏压温度不稳定现象(BTI)和高k击穿特性进行了探讨.     

ECR plasma etch fabrication of C-doped base InGaAs/InP DHBT structures: A comparison of CH4/H2/Ar vs BCl3/N2 plasma etch chemistries

We compare ECR plasma etch fabrication of self-aligned thin emitter carbondoped base InGaAs/InP DHBT structures using either CH₄/H₂/Ar or BCl₃/N₂ etch chemistries. Detrimental hydrogen passivation of the carbon doping in the base region of our structure during CH₄/H₂/Ar dry etching of the emitter region is observed. Initial conductivity is not recovered with annealing up to a temperature of 500°C. This passivation is not due to damage from the dry etching or from the MOMBE growth process, since DHBT structures which are ECR plasma etched in BCl₃/N₂ have the same electrical characteristics as wet etched controls. It is due to hydrogen implantation from the plasma exposure. This is supported with secondary ion mass spectroscopy profiles of structures which are etched in CH₄/D₂/Ar showing an accumulation of deuterium in the C-doped base region.     

Electrical characteristics of MOSFETs with La2O3/Y2O3 gate stack

A metal oxide semiconductor field effect transistor (MOSFET) with ultra-thin La₂O₃/Y₂O₃ high-k gate dielectric was fabricated. The effects of thermal treatment process on both physical and electrical characteristics of the La₂O₃/Y₂O₃ stack were studied using XPS and electrical measurements. It was observed that the effective mobility of the fabricated MOSFETs with La₂O₃/Y₂O₃ gate stack was not degraded with increasing the annealing temperatures up to 600 °C. X-ray photoelectron spectroscopy (XPS) analysis also revealed that the formation of SiO₂ and silicate layer at the interface was suppressed in La₂O₃/Y₂O₃ stack compare to that of in La₂O₃ single layer. Obtained results suggesting that La₂O₃/Y₂O₃ gate stack is one of the promising candidates for high-k gate insulator to be used in the future metal oxide field effect transistors.     

Effect of O2/CHF3 plasma treatment on n-type GaN grown on sapphire by MOCVD

Plasma-induced damage of n-type GaN in Cl₂/CH₄/Ar reactants and its recovery by the O₂/CHF₃ plasma treatment in reactive ion etching (RIE) system were studied by etching rate, self-bias voltage and Hall measurement. RIE of n-type GaN was performed at a radio frequency power of 250 W in Cl₂/CH₄/Ar ambient prior to in the O₂/CHF₃ plasma treatment. The effect of O₂/CHF₃ plasma treatment on electrical characteristics of n-type GaN was investigated by changing the ratio of O₂/CHF₃ flow rate. It is found that the damage caused by conventional RIE processing could be partly recovered by CHF₃/O₂ plasma treatment.     

Characterization of GaN films etched using reactive ion etching technique by secondary ion mass spectrometry

We investigated GaN films etched by using reactive ion etching (RIE) technique to fabricate the GaN-based devices. The samples were grown on sapphire substrate by metal organic chemical vapor deposition (MOCVD), and Ti/Al contacts were formed on n-GaN surfaces after etching processes. The effects of the kinds of reactive gases were evaluated by secondary ion mass spectrometry (SIMS). The results showed that in the sample etched using BCl₃ gas, the signal from boron contaminations was strongly detected at the interface between the contact metal and n-GaN, and we found that additional etching in Cl₂ plasma after etching with BCl₃ gas was essential to make a good contact.     

先栅工艺中高K/双金属栅集成研究新进展

随着高K、金属栅材料引入到CMOS工艺,高K/双金属栅的集成已成为研究热点.利用多晶硅回刻和摻杂结合两步全硅化工艺的方案,可实现低功耗和高性能电路的高K与双FUSI金属栅的集成.采用淀积-刻蚀-再淀积、双高K双金属栅的集成方案,也可实现高K与双金属栅的集成.为缓解费米能级钉扎效应,通过盖帽层或离子注入技术对高K或金属栅掺杂,可得到具有带边功函数的高K/双金属栅集成.多晶硅/金属栅复合结构为高K与双金属栅的集成提供了更灵活的选择.