A diketopyrrolopyrrole containing molecular semiconductor: Synthesis,characterization and solution-processed 1D-microwire based electronic devices

Highly oriented 1D-microwires of a diketopyrrolopyrrole (DPP) based semiconductor i.e. DPP(CBZ)₂ (Carbazole capped DPP) were synthesized, characterized and applied to the fabrication of organic optoelectronic devices. 1D-microwires of DPP(CBZ)₂ were prepared by solution processing on capillary tubes serving to pin solution. A bottom-gate, top-contact field-effect transistor employing 1D-microwire and polymeric gate dielectric showed a hole mobility of 1.24 × 10⁻² cm²/V s, an on-to-off drain current ratio (I_on/I_off) of 4.7 × 10³ and subthreshold slopes of 4 V/dec under ambient conditions. Under white light, a photosensitivity of 800 at V_G = −40 V and photoresponsivity of 830 mW/A were achieved. This work demonstrates the potential of this new molecule and the solution method for use in various opto-electronic devices such transistors, photosensors and photovoltaics.     

Electrical and photovoltaic properties of a n-Si/chitosan/Ag photodiode

The electrical and photovoltaic properties of AuSb/n-Si/chitosan/Ag diode have been investigated. The ideality factor, barrier height and Richardson constant values of the diode at room temperature were found to be 1.91, 0.88 eV and 121.4 A/cm² K², respectively. The ideality factor of the diode is higher than unity, suggesting that the diode shows a non-ideal behaviour due to series resistance and barrier height inhomogeneities. The barrier height and ideality factor values of Ag/CHT/n-Si diode at room temperature are significantly larger than that of the conventional Ag/n-Si Schottky diode. The φ_B value obtained from C-V measurement is higher than that of φ_B value obtained from I-V measurement. The discrepancy between φ_B(C-V) and φ_B(I-V) barrier height values can be explained by Schottky barrier height inhomogeneities. AuSb/n-Si/chitosan/Ag diode indicates a photovoltaic behaviour with open circuit voltage (V_oc = 0.23 V) and short-circuit current density (J_sc = 0.10 μA/cm⁻²) values.     

Study of gate dielectric permittivity variation with different equivalent oxide thickness on channel engineered deep sub-micrometer n-MOSFET device for mixed signal applications

The impact of high permittivity gate dielectrics with different equivalent oxide thickness (EOT) for conventional, low and high tilt angle halo implants on the performance of 100 nm n-MOSFETs device is studied using device simulator Synopsys ISE-TCAD. In this paper, we systematically increase the value of gate dielectric (3.9-50) and investigate its effects on conventional, low angle of tilt (10^o) and high angle of tilt (50^o) halo implants for different device parameters of 100 nm n-MOSFETs using two different EOT viz. 1.5 nm and 2.0 nm. The impact of gate dielectric permittivity along with the different angles of halo implants on short channel performance contributing to the DIBL, the subthreshold swing, I_ON/I_OFF ratio, and the threshold voltage V_T are studied for two different EOT thicknesses. The device has been investigated for digital performance parameters like the variation of substrate-body voltage on DIBL, I_OFF, I_ON and the threshold voltage V_T for sub 100 nm technology generation. It has also been investigated for analog performance like trans-conductance generation factor (gm/I_D) and overall gain (gmR₀).     

Calculation from the current-voltage and capacitance-voltage measurements of characteristics parameters of Cd/CdS/n-Si/Au-Sb structure with CdS interface layer grown on n-Si substrate by SILAR method

The CdS thin film has been directly formed on n-type Si substrate to form an interfacial layer between cadmium (Cd) and n-type Si with Successive Ionic Layer Adsorption and Reaction (SILAR) method. An Au-Sb electrode has been used as an ohmic contact. The Cd/CdS/n-Si/Au-Sb structure has demonstrated clearly rectifying behaviour by the current-voltage (I-V) curves studied at room temperature. The characteristics parameters such as barrier height, ideality factor and series resistance of Cd/CdS/n-Si/Au-Sb structure have been calculated from the forward bias I-V and reverse bias C⁻²-V characteristics. The diode ideality factor and the barrier height have been calculated as n = 2.06 and Φ_b = 0.92 eV by applying a thermionic emission theory, respectively. The diode shows non-ideal I-V behaviour with an ideality factor greater than unity that can be ascribed to the interfacial layer, the interface states and the series resistance. At high current densities in the forward direction, the series resistance (R_s) effect has been observed. The values of R_s obtained from dV/d(lnI)-I and H(I)-I plots are near to each others (R_s = 182.24 Ω and R_s = 186.04 Ω, respectively). This case shows the consistency of the Cheung′s approach. In the same way, the barrier height calculated from C⁻² -V characteristics varied from 0.698 to 0.743 eV. Furthermore, the density distribution of interface states (N_ss) of the device has been obtained from the forward bias I-V characteristics. It has been seen that, the N_ss has almost an exponential rise with bias from the mid gap toward the bottom of conduction band.     

Power performance and scalability study of AlGaAs/GaAs double-recessed pseudomorphic high electron mobility transistors on unthinned substrate for coplanar waveguide circuit applications

We have investigated the power performance and scalability of AlGaAs/GaAs Double-Recessed Pseudomorphic High Electron Mobility Transistors (DR-PHEMTs) at 10 GHz on an unthinned GaAs substrate for CoPlanar Waveguide (CPW) circuit applications. It was found that the output power varied linearly with the logarithm of the device’s gate width ranging from 200 to 1000 μm. It increased at a rate of 0.01 dB/μm. That worked out to a doubling of output power (or 3 dB) for every 300 μm increase in the gate width. Gain decreased at a rate of about 0.005 dB/μm while PAE generally improved when the gate width was increased. As for DC measurement, the maximum transconductance of the device was about 375 mS/mm at V_G = −0.5 V and V_DS = 3 V. The gate-drain breakdown voltage (BV_GD) measured was −20 V, defined at I_G = −1 mA/mm. The microwave performance of the devices was measured on-wafer using a load-pull system at a bias of V_G = −0.5 V and V_DS = 8 V. For a device with a gate width of 1 mm, its saturated CW output power, gain and PAE value at 10 GHz was 27.5 dBm (0.55 W), 8 dB and 48%, respectively. At this same set of bias conditions, the value of f_t and f_max was 40 and 80 GHz, respectively.     

Air-stability and bending properties of flexible organic field-effect transistors based on poly[N-9′-heptadecanyl-2,7-carbazole-alt-5,5-(4′,7′-di-2-thienyl-2′,1′,3′-benzothiadiazole)]

We have fabricated flexible field-effect transistors (FETs) using poly[N-9′-heptadecanyl-2,7-carbazole-alt-5,5-(4′,7′-di-2-thienyl-2′,1′,3′-benzothiadiazole)], PCDTBT, as an active channel, poly(methyl methacrylate) (PMMA) as gate dielectric and biaxially oriented polyethyleneterephthalate (BOPET) as supporting substrate. The output and transfer characteristics of the devices were measured as a function of channel length. It has been observed that various OFET parameters viz. on–off ratio (∼10⁵), mobility (μ ∼ 10⁻⁴ cm² V⁻¹ s⁻¹), threshold voltage (V_th ∼ −14 V), switch-on voltage (V_so ∼ −6 V), subthreshold slope (S ∼ 7 V/decade) and trap density (N_it ∼ 10¹⁴ cm⁻² V⁻¹) are almost independent of the channel length, which suggested a very high uniformity of the PCDTBT active layer. These devices were highly stable under atmospheric conditions (temperature: 20–35 °C and relative humidity: 70–85%), as no change in mobility was observed on a continuous exposure for 70 days. The studies on the effect of strain on mobility revealed that devices are stable up to a compressive or tensile strain of 1.2%. These results indicate that PCDTBT is a very promising active layer for the air stable and flexible FETs.     

AlGaN/GaN self-aligned MODFET with metal oxide gate for millimeter wave application

As promising candidates for future microwave power devices, GaN-based high-electron mobility transistors (HEMTs) have attracted much research interest. An investigation of the operation of AlGaN/GaN n type self-aligned MOSFET with modulation doped GaN channels is presented. Liquid phase deposited (LPD) SiO₂ is used as the insulating material. An analytical model based on modified charge control equations is developed. The investigated critical parameters of the proposed device are the maximum drain current (I_Dmax), the threshold voltage (V_th), the peak DC trans-conductance (g_m), break down voltage (V_br) and unity current gain cut-off frequency (f_T). The typical DC characteristics for a gate length of 1 μm with 100 μm gate width are following: I_max=800 mA/mm, V_break-down=50 V, g_{m_extrinsic}=200 mS/mm, V_pinchoff=−10 V. The analysis and simulation results on the transport characteristics of the MOS gate MODFET structure is compared with the previously measured experimental data. The calculated values of f_T (20-130 GHz) suggest that the operation of the proposed device effectively, has sufficiently high current gain cutoff frequencies over a wide range of drain voltage, which is essential for high-power performance at microwave frequencies. The proposed device offers lower on-state resistance. The results so obtained are in close agreement with the experimental data.     

Organic memristive devices based on silver nanoparticles and DNA

A novel organic memory device ‘Al/silver nanoparticles-deoxyribonucleic acid-cetyltrimethylammonium Bromide/ITO’ (Al/Ag NPs–DNA–CTMA/ITO) was fabricated. The measured I–V curve of the device exhibits unipolar switching. The conductivity and the memristive characteristics are significantly improved by the introduction of Ag nanoparticles, but with a poor stability. Better stability is achieved by annealing the device, which also changes the switching characteristic from unipolar to bipolar. As the annealing temperature is raised, the switching voltage first decreases and then increases, while the current I_RESET first increases and then decreases. The range of the optimal annealing temperature is from 383 K to 403 K and the maximum ON/OFF current ratio (I_ON/I_OFF) can reach 10⁴. The switching voltage, the current, and I_ON/I_OFF all increase with the applied voltage amplitude, and V_SET and I_ON/I_OFF obey a quadratic and Boltzmann relationship, respectively.     

Dibenzothiophene-S,S-dioxide based medium-band-gap polymers for efficient bulk heterojunction solar cells

Medium-band-gap polymers based on indacenodithiophene (IDT) and dibenzothiophene-S,S-dioxide (SO) derivatives, PIDT-SO and PIDT-DHTSO, were synthesized via a microwave assisted Stille polycondensation. The polymers have the maximum absorption ∼500 nm, high absorption coefficients above 0.6 × 10⁻² nm⁻¹, and medium band gaps of ∼2.2 eV. Their hole mobilities are around 2 × 10⁻⁴ cm² V⁻¹ s⁻¹ as measured by field effect transistors. The photovoltaic performances of the polymers were investigated on the inverted bulk heterojunction (BHJ) devices of ITO/PFN/PIDT-DHTSO:PC₇₁BM (1:3, w/w)/MoO₃/Al, and a power conversion efficiency (PCE) of 3.81% with an open-circuit voltage (V_oc) of 0.95 V, a short-circuit current (J_sc) of 8.20 mA cm⁻² and a fill factor (FF) of 48% were achieved. Those results indicated that dibenzothiophene-S,S-dioxide derivatives could be an excellent electron-deficient building block for medium-band-gap electron-donor polymers.     

Electrical characterisation of SiON/n-Si structures for MOS VLSI electronics

In the present work, we examine the properties of SiON films grown on Si substrates by CVD in order to investigate their suitability as potential materials in replacing SiO₂ in metal-oxide-semiconductor (MOS) devices. Suitable metallization created MOS devices and electrical characterisation took place in order to identify their electrical properties. Electrical measurements included current-voltage (I-V), capacitance-conductance-voltage (C-V) measurements and admittance spectroscopy (Y−ω) allowing determination of the bulk charges and the dielectric response of the films. The analysis of the data also took into account the presence of traps at the Si/SiON interface calculated by a fast conductance technique. The interface states density was of the order of 10¹² eV⁻¹ cm⁻². The dielectric constant was found to lie between 16 and 4.5 and the corresponding bulk trapped charges were found between 8 and 113 μCb cm⁻². Post deposition annealing altered these values showing an improvement of the device behaviour. A short explanation of the above is also provided.     

The interface states analysis of the MIS structure as a function of frequency

The energy distribution of interface states (N_ss) and their relaxation time (τ) were of the fabricated the Al/SiO₂/p-Si (MIS) structures were calculated using the forward bias current-voltage (I-V), capacitance-frequency (C-f) and conductance-frequency (G-f) measurements. Typical ln[I/(1 − exp(−qV/kT)] versus V characteristics of MIS structure under forward bias show one linear region. From this region, the slope and the intercept of this plot on the current axis allow to determine the ideality factor (n), the barrier height (Φ_b) and the saturation current (I_S) evaluated to 1.32, 0.77 eV and 3.05 × 10⁻⁹ A, respectively. The diode shows non-ideal I-V behaviour with ideality factor greater than unity. This behaviour is attributed to the interfacial insulator layer at metal-semiconductor interface, the interface states and barrier inhomogeneity of the device. The energy distribution of interface states (N_ss) and their relaxation time (τ) have been determined in the energy range from (0.37 − E_v) to (0.57 − E_v) eV. It has been seen that the N_ss has almost an exponential rise with bias from the mid gap toward the top of valance band. In contrary to the N_ss, the relaxation time (τ) shows a slow exponential rise with bias from the top of the E_v towards the mid gap energy of semiconductor. The values of N_ss and τ change from 6.91 × 10¹³ to 9.92 × 10¹³ eV⁻¹ cm⁻² and 6.31 × 10⁻⁴ to 0.63 × 10⁻⁴ s, respectively.     

Cubic GaN/AlGaN Schottky-barrier devices on 3C-SiC substrates

In this work, we focus on the fabrication of cubic GaN based Schottky-barrier devices (SBDs) and measured current voltage (I-V) characteristics and the critical field for electronic breakdown. Phase-pure cubic GaN and c-Al_xGa_1 − xN/GaN structures were grown by plasma assisted molecular beam epitaxy (MBE) on 200 μm thick free-standing 3C-SiC (1 0 0) substrates, which were produced by HOYA Advanced Semiconductor Technologies Co., Ltd. The thickness of the c-GaN and c-Al_0.3Ga_0.7N epilayers were about 600 and 30 nm, respectively. Ni/In Schottky contacts 300 μm in diameter were produced on c-GaN and c-Al_0.3Ga_0.7N/GaN structures by thermal evaporation using contact lithography. A clear rectifying behavior was measured in our SBDs and the I-V behavior was analyzed in detail, indicating the formation of a thin surface barrier at the Ni-GaN interface. Annealing of the Ni Schottky contacts in air at 200 °C reduces the leakage current by three orders of magnitude. The doping density dependence of breakdown voltages derived from the reverse breakdown voltage characteristics of c-GaN SBDs is investigated. The experimental values of breakdown voltage in c-GaN are in good agreement with theoretical values and show the same dependence on doping level as in hexagonal GaN. From our experimental data, we extrapolate a blocking voltage of 600 V in c-GaN films with a doping level N_D = 5 × 10¹⁵ cm⁻³.     

Effect of series resistance on the electrical characteristics and interface state energy distributions of Sn/p-Si (MS) Schottky diodes

In this study, electrical characteristics of the Sn/p-type Si (MS) Schottky diodes have been investigated by current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The barrier height obtained from C-V measurement is higher than obtained from I-V measurement and this discrepancy can be explained by introducing a spatial distribution of barrier heights due to barrier height inhomogeneities, which are available at the nanostructure Sn/p-Si interface. A modified Norde’s function combined with conventional forward I-V method was used to extract the parameters including barrier height (Φ_b) and the series resistance (R_S). The barrier height and series resistance obtained from Norde’s function was compared with those from Cheung functions. In addition, the interface-state density (N_SS) as a function of energy distribution (E_SS-E_V) was extracted from the forward-bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_b) and series resistance (R_S) for the Schottky diodes. While the interface-state density (N_SS) calculated without taking into account series resistance (R_S) has increased exponentially with bias from 4.235 × 10¹² cm⁻²eV⁻¹ in (E_SS - 0.62) eV to 2.371 × 10¹³ cm⁻²eV⁻¹ in (E_SS - 0.39) eV of p-Si, the N_SS obtained taking into account the series resistance has increased exponentially with bias from of 4.235 × 10¹² to 1.671 × 10¹³ cm⁻²eV⁻¹ in the same interval. This behaviour is attributed to the passivation of the p-doped Si surface with the presence of thin interfacial insulator layer between the metal and semiconductor.     

Schottky barrier SOI-MOSFETs with high-k La(2)O(3)/ZrO(2) gate dielectrics

Schottky barrier SOI-MOSFETs incorporating a La₂O₃/ZrO₂ high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N′-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500 °C. Excellent drive current properties, low interface trap densities of 1.9 × 10¹¹ eV⁻¹ cm⁻², a low subthreshold slope of 70-80 mV/decade, and an I_ON/I_OFF current ratio greater than 2 × 10⁶ are obtained.     

Molybdenum and low-temperature annealing of a silicon power P-i-N diode

High-power P⁺P-N-N⁺ diodes (V_RRM = 2.5 kV, I_FAV = 150 A) with sputtered Mo layer at anode were annealed in the range 550-800 °C with and without the presence of radiation defects from helium implantation (10 MeV, 1 × 10¹² cm⁻²). The devices were characterized using DLTS, spreading resistance, OCVD lifetime, leakage current, forward voltage drop and reverse recovery measurements. The diffusion of Mo from the 50 nm thick surface layer was not registered even after 4 h between 550 and 800 °C in a rough vacuum. The DLTS confirms the existence of hole deep levels H1 and H2 in the He implanted devices with the Mo anode layer. Similar levels have been already found in the devices with Pt and Pd anode layers, but with different annealing behavior between 600 and 700 °C. Contrary to that of the Pt and Pd, no radiation enhanced diffusion was found from the 50 nm thick Mo surface layer in a rough vacuum.     

Normally-off trench JFET technology in 4H silicon carbide

A double gate normally-off silicon carbide (SiC) trench junction field effect transistors (JFET) design is considered. Innovative migration enhanced embedded epitaxial (ME³) growth process was developed to replace the implantation process and realize high device performance. Strong anisotropic behavior in electrical characteristics of the pn junction fabricated on (1 1 −2 0) and (1 −1 0 0) trench a-planes was observed, although quality of the pn diodes was found to be independent of trench plane orientations. Fabricated normally-off trench 4H-SiC JFET demonstrates the potential for lower specific on-resistance (R_onS) in the range of 5-10 mΩ cm² (1200 V class). A relative high T^−2.6 dependence of R_onS is observed. A breakdown voltage of 400 V in the avalanche mode was confirmed at zero gate bias conditions for cell design without edge termination. It was demonstrated that the normally-off JFETs are suitable for high temperature applications. Average temperature coefficient of threshold voltage (V_th) was calculated as −1.8 mV/°C, which is close to the MOS based Si power devices.     

H-aggregation mode in triple-decker phthalocyaninato-europium semiconductors. Materials design for high-performance air-stable ambipolar organic thin film transistors

Two new tris(phthalocyaninato) europium complexes Eu₂(Pc)[Pc(OPh)₈]₂ (1) and Eu₂[Pc(OPh)₈]₃ (2) [Pc = unsubstituted phthalocyaninate; Pc(OPh)₈ = 2,3,9,10,16,17,23,24-octaphenoxyphthalocyaninate], were designed and synthesized. Introduction of different number of electron-withdrawing phenoxy substituents at the phthalocyanine periphery within the triple-decker complexes not only ensures their good solubility in conventional organic solvents, but more importantly successfully tunes their HOMO and LUMO levels into the range of air-stable ambipolar organic semiconductor required on the basis of electrochemical studies over both 1 and 2, meanwhile fine controlling of aggregation mode (H vs. J) in solution-based film for improving OTFT performance is also achieved. Measurements over the OTFT devices fabricated from these sandwich compounds by a solution-based quasi–Langmuir–Shäfer (QLS) method reveal their ambipolar semiconductor nature associated with suitable HOMO and LUMO energy levels. Due to the H-aggregation mode employed by the heteroleptic triple-decker molecules in the QLS film, excellent performances with the electron and hole mobility in air as high as 0.68 and 0.014 cm² V⁻¹ s⁻¹, respectively, have been revealed for the OTFT devices of heteroleptic triple-decker 1. This represents the best performance so far for solution-processable ambipolar single-component phthalocyanine-based OTFTs obtained under ambient conditions. In good contrast, homoleptic analogue 2 prefers to J-type aggregation and this results in relatively lower electron and hole mobility, around 0.041 and 0.0026 cm² V⁻¹ s⁻¹ in air, respectively, for the devices fabricated. In particular, the performance of the devices fabricated based on 1 was found to remain almost unchanged in terms of both the carrier mobilities and on/off ratio even after being stored under ambient for 4 months.     

n-Doped-layer free amorphous silicon thin film solar cells fabricated with the CuMg alloy as back contact metal

The feasibility of using CuMg alloy as back contact metal for n⁺-doped-layer free a-Si:H thin film solar cell (TFSC) has been investigated in this work. The ohmic-contact characteristic has been achieved by using the CuMg alloy as back contact metal. The proposed structure showed the typical solar cell current-voltage (I-V) characteristic. An initial efficiency of 4.3% has been obtained with a open-circuit voltage V_oc = 0.79 V, short-circuit current J_sc = 13.4 mA/cm² and fill factor F.F. = 0.40. Furthermore, the experimental results also showed the CuMg alloy was suitable for the replacement of n⁺-doped-layer with the production cost reduction of a-Si:H TSFC.     

Electrical characterization of poly(amide-imide) for application in organic field effect devices

The admittance spectra and current–voltage (I–V) characteristics are reported of metal–insulator–metal (MIM) and metal–insulator–semiconductor (MIS) capacitors employing cross-linked poly(amide–imide) (c-PAI) as the insulator and poly(3-hexylthiophene) (P3HT) as the active semiconductor. The capacitance of the MIM devices are constant in the frequency range from 10 Hz to 100 kHz, with tan δ values as low as 7 × 10⁻³ over most of the range. Except at the lowest voltages, the I–V characteristics are well-described by the Schottky equation for thermal emission of electrons from the electrodes into the insulator. The admittance spectra of the MIS devices displayed a classic Maxwell–Wagner frequency response from which the transverse bulk hole mobility was estimated to be ∼2 × 10⁻⁵ cm² V⁻¹s⁻¹ or ∼5 × 10⁻⁸ cm² V⁻¹s⁻¹ depending on whether or not the surface of the insulator had been treated with hexamethyldisilazane (HMDS) prior to deposition of the P3HT. From the maximum loss observed in admittance-voltage plots, the interface trap density was estimated to be ∼5 × 10¹⁰ cm⁻² eV⁻¹ or ∼9 × 10¹⁰ cm⁻² eV⁻¹ again depending whether or not the insulator was treated with HMDS. We conclude, therefore, that HMDS plays a useful role in promoting order in the P3HT film as well as reducing the density of interface trap states. Although interposing the P3HT layer between the insulator and the gold electrode degrades the insulating properties of the c-PAI, nevertheless, they remain sufficiently good for use in organic electronic devices.     

Interface control of conventional n-type silicon/metal by n-channel organic semiconductor

The rectifying and interface state density properties of n-Si/violanthrone-79/Au metal-diode have been investigated by current-voltage and capacitance-conductance-frequency methods. The ideality factor, barrier height and average series resistance of the diode were found to be 2.07, 0.81 eV and 5.04 kΩ respectively. At higher voltages, the organic layer contributes to I-V characteristics of the diode due to space-charge injection into the organic semiconductor layer and the trapped-charge-limited current mechanism is dominant mechanism for the diode. The barrier height obtained from C-V measurement is lower than the barrier height obtained I-V measurement and the organic layer creates an excess physical barrier for the diode. The interface state density of the diode was found to be 1.70 × 10¹¹ eV⁻¹ cm⁻² at 0.2 V and 1.72 × 10¹¹ eV⁻¹ cm⁻² at 0.4 V.The obtained electronic parameters indicate that the organic layer provides the conventional n-type silicon/metal interface control option.