Electrical performance, reliability and microstructure of sub-45 nm copper damascene lines fabricated with TEOS backfill

The fabrication of narrow Cu trenches using a conformal TEOS backfill approach is shown. Cu trenches with widths down to 30-40 nm were achieved. With an adequate Ta-based PVD barrier and Cu seed layer scheme, narrow Cu lines with high yield were obtained. An increase of the electrical resistivity in the narrowest dimensions was observed as a result of the size effect. Electromigration assessment demonstrated that a bilayer TaN/Ta barrier outperforms the monolayer Ta barrier. Electron backscattering diffraction (EBSD) analysis was carried out to determine grain orientation and texture in narrow copper trenches. For the first time, EBSD data reveal that Cu trenches down to 30-40 nm wide have mostly a random texture. The narrower the Cu lines get, the weaker the (1 1 1) texture with both monolayer and bilayer Ta-based barriers.     

Texture and strain in narrow copper damascene interconnect lines: An X-ray diffraction analysis

The behaviour of submicron damascene copper lines raises a number of fundamental issues such as grain growth in narrow trenches, thermomechanical properties of copper in these confined geometries, etc. This experimental study is aimed at evaluating the influence of annealing, polishing and line width on the room temperature strain and texture of narrow copper damascene lines. X-ray diffraction has been performed on arrays of lines with widths ranging between 3 μm and 0.09 μm. Two annealing conditions (150 °C and 400 °C) have been used either prior or after Chemical Mechanical Polishing (CMP). A clear influence of the Cu overburden on the in-line microstructure is evidenced. X-ray diffraction analysis shows that strains in line longitudinal direction are higher in those annealed at 400 °C and decrease with the width of the lines.Effect of CMP on structure and relationship between both texture and strain and temperature of thermal treatments is discussed in light of these observations.     

Microstructure in copper interconnects - Influence of plating additive concentration

Downscaling of copper interconnects is demanding more knowledge about the microstructure and grain growth mechanisms in sub 100 nm dimensions. Large grains are needed to reduce the resistivity and to increase the reliability of narrow lines. Plating additives are used for a void free filling of the interconnecting vias and lines. Fractions of these additives are incorporated into the copper as impurities during electrochemical deposition. In the present paper the role of additive concentration on grain growth is investigated. Interconnect lines from 72 nm to 1.9 μm line width were completely filled with copper using different additive concentrations in the electrolyte. The impurity level was measured by time of flight secondary ion mass spectrometry. The samples were stored at room-temperature to achieve self-annealing or tempered at low and high temperatures. Self-annealing slows down with increasing additive concentration whereas bamboo-like grains are present after annealing all samples at high temperatures. Grain growth was studied as well as the average grain size, resistivity, and {1 1 1} texture.     

Fabrication of nickel stamp with improved sidewall roughness for optical devices

We proposed the simple and attractive fabrication method of nickel stamp with improved sidewall roughness for polymeric optical devices. For this, the imprinted optical devices patterns under optimum imprinting conditions were annealed to improve the sidewall roughness generated by the DRIE process in the silicon stamp fabrication. The annealed sidewall roughness is reduced to 24.6 nm, nearly decreasing by 76% compared with the result before the annealing. Then, low cost and durable nickel stamp with improved sidewall roughness was fabricated by the annealed polymeric patterns being used as original master for electroforming process. And, we verified the superiority of the improved nickel stamp by comparing the optical propagation losses for optical waveguides to be fabricated, respectively, using the nickel stamp and original silicon stamp. The optical waveguides fabricated by the imprint lithography using the improved nickel stamp was demonstrated that their optical losses were reduced as 0.21 dB/cm, which was less than the propagation loss for polymeric waveguides using the conventional original silicon stamp. This result could show the effectiveness of the fabricated nickel stamp with improved sidewall roughness. Furthermore, we were able to successfully fabricate a polymeric 1 × 8 beam splitter device using the improved nickel stamp. And, the insertion loss for eight channels obtained to be from 10.02 dB to 10.91 dB.     

The influence of the AlN film texture on the wet chemical etching

The influence of the aluminum nitride (AlN) film texture on the chemical etching in KOH solution was invested. The AlN films with the different texture and crystal quality were prepared by sputtering. It is found that the chemical etching behaviors, including the etch rate, the activation energy, the surface morphology and the anisotropy, are strongly dependent on the film texture. There is a faster etching in the case of mixed (1 0 0) and (0 0 2) texture and a lower rate in the case of only (0 0 2) texture. The etch rate also decreases with the crystal quality. The sample with the only (0 0 2) texture forms discontinuous column structure after etching and exhibits lower porosity compared to that of the mixed (1 0 0) and (0 0 2) texture. Due to the strong anisotropy of the AlN wurtzite structure, the morphology of the film deposited at 700 °C shows the homogeneous pyramid shape after etching. The cross-section micrographs of etching patterns indicate that the anisotropy of the chemical etching is improved with the improving of the crystal quality.     

High aspect ratio nano mold fabrication by advanced edge lithography without CVD

Very narrow SiO₂ line patterns with extremely high aspect ratio are fabricated on a silicon wafer by new edge lithography process. The simple process without chemical vapor deposition process is developed. The Si step etching is carried out by F radical dominant etching by reducing the loading effect. The straight line of 25 nm width and 700 nm height is fabricated. The circular line with 40 nm width and 400 nm height is also fabricated. The aspect ratios for the straight and circular lines are 28 and 10, respectively. In order to the fabricate imprint mold, the fabricated narrow lines are replicated to a nickel by the electro forming. The nickel replica with 40 nm cavity width is successfully fabricated.     

Fabrication of cantilever arrays with nano-aperture hollow tips for parallel microplasma etching

For the application of parallel microplasma etching, cantilever arrays with nano-aperture hollow pyramid tips have been successfully fabricated. The SiO₂ cantilever arrays and hollow tips are formed by thermal oxidation on a Si (1 0 0) wafer with pyramid cavities. Due to the stress-dependent nonuniform oxidation, the oxide thickness is about 400 nm at the tip apexes which is much thinner than the 1.2 μm thick sidewalls. Based on these nonuniform oxide hollow tips, nano-apertures of 50-200 nm in diameter are obtained at the apexes after the following 1:10 water-diluted HF isotropic etching. The base widths of the hollow tips are designed to be 50 and 100 μm with the final sidewall thickness of only 600 nm. Consequently, the width-thickness ratio (hollow pyramid tip base width/sidewall thickness) is up to 150:1. Some improvements are made in the fabrication process and these fragile tips are obtained with a product yield of more than 90%. Then, cantilever arrays with hollow tips are released consistently and the bending behavior is discussed. In addition, preliminary experiments and simulations of microplasma generation and extraction confirm the application feasibility of this structure in parallel microplasma etching.     

In situ X-ray diffraction study of self-forming barriers from a Cu-Mn alloy in 100 nm Cu/low-k damascene interconnects using synchrotron radiation

An in situ study of self-forming barriers from a Cu-Mn alloy was performed to investigate the barrier growth using X-ray diffraction on damascene lines. The associated evolution in interconnect texture and Cu stress was also observed. The shift in Cu diffraction peak position was used to determine the change in Mn concentration and hence, estimate the thickness of the MnSi_xO_y barrier. The observed peak shift followed a log(t) behaviour and is described well by metal oxidation kinetics, following the field enhanced diffusion model. We used multiple anneal temperatures to study the activation of the formation process, demonstrating a faster barrier formation with higher ion excitation. A strong [1 1 1] Cu texture was shown to develop during the anneal in contrast to traditional PVD barrier systems. Finally, the stress in the 100 nm Cu lines was calculated, observing a large in-plane relaxation when using a self-forming barrier due to reduced confinement.     

Grain morphology of Cu damascene lines

The evolution of the grain structure through annealing of narrow damascene Cu interconnects is important for any further design of highly integrated circuits. Here we present a comprehensive transmission electron microscopy study of damascene lines between 80 nm and 3000 nm wide. Experimental results clearly indicate that morphology evolutions through annealing are strongly influenced by the line width. If the lines are wider than 250 nm a strong connection between the grain structure within the lines and the overburden copper is present at least after sufficient annealing. Once the lines are as small as 80 nm the grain structure within the lines are only weakly connected to the overburden copper grown above.     

Behavior of (1 1 1) grains during the thermal treatment of copper film studied in situ by electron back-scatter diffraction

An annealed Cu blanket film was investigated in situ at high temperature using electron back-scatter diffraction (EBSD). The primary aim of the experiment was to study the changes in the (1 1 1) texture in the Cu film where the microstructure was already stabilized by previous annealing treatment. Two separate investigations were carried out at the same location of the film for better statistical reliability of data. It was found that the (1 1 1) planes got increasingly inclined to the specimen surface with increasing temperature. Additionally, a change in the strength of {1 1 1}〈1 1 0〉 and {1 1 1}〈1 1 2〉 texture components was observed with increasing temperature. Absence of these phenomena in freestanding Cu film indicates the impact of substrate on the behavior of (1 1 1) grains. The effect of substrate on the peculiar behavior of the (1 1 1) grains has been explained by a model which describes the contribution of both dislocations and diffusion to the observed phenomenon. The tilting of the (1 1 1) grains is discussed with reference to the recently reported Bauschinger effect in the Cu films.     

Dry etching fin process for SOI finFET manufacturing: Transition from 32 to 22 nm node on a 6T-SRAM cell

This work describes the main challenges encountered for patterning crystalline silicon (c-Si) fins when we scaled down the fin pitch from 124 to 90 nm on a 6T-SRAM cell. The target fins consist of straight structures (40 nm height and 17 nm of critical dimension) patterned on a 22 nm node with 90 nm fin pitch. The patterning stack consists of 70 nm of amorphous carbon as a hard mask with 25 nm of antireflective coating. Scaling down the fin pitch had a direct influence on the fin critical dimension, profile and sidewall roughness. We found out that the fin etching process developed for a 32 nm node with 124 nm fin pitch was no longer functional for patterning fins on a 22 nm node with 90 nm fin pitch, i.e., the critical dimension was wider than the target, the fins sidewalls were isotropically attacked and the profile was sloped. In order to reach 17 nm of critical dimension on 90 nm pitch we had to implement a new hard mask opening step. The c-Si fin sidewall roughness and fin profile were tuned by improving the uniformity across the wafers, optimizing the softlanding etch time and introducing a new overetch step with notch capability.     

Characterization of QWIP structures prepared on GaAs-patterned substrates

In this work we investigate the preparation of quantum well infrared photodetectors (QWIP) on planar and patterned GaAs substrates. Mesa ridges with various angles between sidewall and substrate (1 0 0) plane were prepared by wet chemical etching. The QWIP structures were grown at a temperature of 700 °C by use of low-pressure MOVPE. Electrical properties and spectral sensitivity of QWIP structures prepared on tilted sidewalls were measured. Our results showed that mesa ridges confined at the sides by facets tilted at 30° to (1 0 0) were most suitable for the QWIP preparation. Asymmetry in room temperature I-V characteristics and a small photovoltaic effect observed at 77 K was ascribed to asymmetric position of delta doping plane in the quantum well.     

Interpretation of texture changes during self-annealing of electroplated copper

Electroplating of copper is widely used for the fabrication of interconnections of printed circuit boards, in which via-holes are used to connect conductive layers. Self-annealing is an important feature of electroplated copper which significantly alters its microstructures. The degradation of 〈1 1 0〉 texture and the enhancement of 〈3 1 1〉 texture in electroplated copper during self-annealing process are observed by X-ray diffraction (XRD) and electron backscattering diffraction (EBSD). The mechanism of this transformation is discussed and illustrated.     

Surface characterization of epitaxial lateral overgrowth of InP on InP/GaAs substrate by MOCVD

Epitaxial lateral overgrowth (ELO) of InP on InP/GaAs substrates by low-pressure metalorganic chemical vapor deposition (LP-MOCVD) was investigated. The lateral overgrowth InP layers were obtained on the SiO₂ masked InP seed layer, which was deposited on the (1 0 0) GaAs substrate by the two-step method. The surface characterization of overgrowth InP was dependent on the V/III ratio, the mask width and the growth time. When decreasing the V/III ratio or reducing the mask width respectively, the sidewalls “competition effect” was obviously observed. After a longer time, new (1 0 0)-like top surfaces were formatted because of the precursors migrating from the sidewall facets to the (1 0 0) top surfaces. The experimental findings will be explained by growth kinetics in conjunction with the different dominant source supply mechanism.     

Characterization of SiC MESFETs with narrow channel layer

SiC MESFETs with a narrow channel layer are proposed to alleviate the short-channel effects, in particular the drain-induced barrier lowering (DIBL) effect that results in threshold voltage that is dependent on the gate length and the drain voltage applied. Such narrow channel layer 4H-SiC MESFETs were fabricated and characterized. The thickness and doping concentration of the channel layer are 0.08 μm and 8.0 × 10¹⁷ cm⁻³, respectively. The measurement results showed that the threshold voltage of the MESFETs is about −1.1 V and is independent of the gate length from 1 to 3 μm, and the drain voltage applied up to 40 V. Good saturation behavior with fairly low output conductance was also achieved, which is desirable for small signal applications. The results obtained for the narrow channel layer MESFETs are also compared with those measured for conventional devices with thicker channel layer of 0.20 μm and doping concentration of 2.5 × 10¹⁷ cm⁻³.     

Microstructure and electromigration in copper damascene lines

Grain sizes and crystallographic orientations of Cu were analyzed versus linewidth in damascene Cu interconnects. Pure bamboo lines were not obtained because grain size decreased as linewidth was reduced. Comparison of electromigration results, for wide line Chemical vapor deposition-Cu (3 μm) polycrystalline structure, and narrow lines (0.5 μm) quasi-bamboo structure, provided almost the same activation energy E_a0.65 eV, even though the poor (2 0 0) texture has rotated in the film plane for the narrow damascene lines. These results are in agreement with copper diffusion involving surface diffusion. Besides, even with a polycrystalline crystallographic orientation, PVD-Cu samples showed a better activation energy value E_a=1.02 eV.     

Analysis of the propagation losses of InP/InGaAsP trench waveguides fabricated by focused ion beam

Focused ion beam was used to fabricate 2 mm-long, 4 μm-wide and 4 μm-deep multimode trench waveguides in InP/InGaAsP. An automated stitching method was developed to fabricate mm-long structures using alignment marks. The waveguides were sputtered or etched using I₂ at room temperature and 150 °C stage temperature. The propagation losses induced by the different fabrication techniques were measured and ranged between 50 and 82 dB/cm. A damaged layer with implanted Ga and the sidewall roughness are identified to be the most important causes for the losses. FIB is shown to be a single-step fabrication technique for rapid-prototyping of photonic structures in InP/InGaAsP.     

Electronic properties of GST for non-volatile memory

Impacts of annealing temperature and film thickness to the resistivity of Ge₂Sb₂Te₅(GST) have been studied. The resistivity of GST drops when the annealing temperature reaches 180 °C, rises above 360 °C and the thicker film crystallized more easily. Electronic device of phase change memory also has been fabricated with metal sidewall technology using 5 μm lithographic technology. The device was successfully programmed by 100 ns of 5 V pulse for SET and 10 ns of 10 V pulse for RESET. More than 100 times on/off ratio has been reached.     

Atomic hydrogen assisted molecular beam epitaxy on patterned GaAs (311)A substrates: Formation of highly uniform quantum-dot arrays

The idea of combining self-organized growth with growth on patterned substrates to produce new types of nanostructures in a controlled manner is realized in atomic hydrogen assisted molecular beam epitaxy (MBE) on patterned GaAs (311)A substrates. In conventional MBE on patterned substrates mesa stripes along [01 ] develop a fast growing sidewall to form quasi-planar lateral quantum wires having a smooth, convex curved surface profile. In atomic hydrogen assisted MBE, the surface naturally develops quasiperiodic one-dimenional step arrays by step bunching along [ 33], i.e., perpendicular to the wire direction with a lateral periodicity around 40 nm. The step array is maintained over the curved sidewall without displacement. Thus, a dense array of dotlike nanostructures is realized with precise control of the position on the substrate surface. High uniformity of the dot array is revealed in micro-photoluminescence spectroscopy with the emission dominated by one single sharp line.     

Modelling the self-alignment of passive chip components during reflow soldering

In my research a 3D model was created to investigate the restoring force arising and the self-alignment occurring during reflow soldering; and simulations were performed to examine the assumptions given by the model. Besides, experiments were carried out to verify both the assumptions and the simulation predictions. Passive components with the size of 0603 (1.5 × 0.75 mm) were placed with intended misplacements and their position was measured before and after soldering. Three cases were examined: how misplacements perpendicular to the longer sides of components affects the restoring force, how parallel misplacements affect the same, and how a sidewall metallization on the component influences that. Based on the results, it is shown that the degree of restoring force is higher in the case of misplacements perpendicular to the longer side of components (x-direction) than in the case of misplacements parallel to that (y-direction). However, in the case of y-direction misplacements, the restoring force increases when sidewall metallization on the components is present.