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1.
《Microelectronics Journal》2014,45(11):1508-1514
In this paper Gate Material Engineered (GME) Gate-Stack (GS) silicon nanowire Schottky-Barrier (SB) Gate All Around (GAA) MOSFET and Single Material Gate Stack Schottky-Barrier Source/Drain Gate All Around (SM-GS-SB-S/D GAA) structures are proposed for low- power wireless applications. The Analog/RF performance for wireless applications of these devices are demonstrated. The effect of Schottky-Barrier (Metal) S/D is studied for Single Metal (SM)–SB-GAA, (Dual Metal) DM-SB-GAA, SM-GS-SB-GAA and GME-GS-SB-GAA MOSFETs, and it is found that GME-GS-SB-GAA MOSFET with metal drain source shows much improved performance in terms of transconductance (gm), output conductance (gd), Early Voltage (VEA), Maximum Transducer Power Gain, cut-off frequency (fT), and Ion/Ioff ratio. Further, harmonic distortion for wireless applications is also studied using ATLAS-3D device simulator. Due to low parasitic S/D resistance the metal Source/Drain DM-GS-SB-S/D-GAA MOSFET demonstrates remarkable Ion of~31.8 μA/μm and saturation transconductance gm of~68.2 μS with improved third order derivative of transconductance gm3. 相似文献
2.
Chihoon Lee Sang Yong No Da Il Eom Cheol Seong Hwang Hyeong Joon Kim 《Journal of Electronic Materials》2005,34(8):1104-1109
In order to examine the electrical and physical properties of Al2O3 layers with dual thickness on a chip, Pt gate/Al2O3 with dual thickness/p-type Si (100) samples were fabricated using atomic-layer deposition, separation photolithography, and
100:1 HF wet etching to remove the first Al2O3 layer. Dual metal-oxide-semiconductor (MOS) capacitors with thin (physical thickness, ∼4.5 nm, equivalent oxide thicknesses
(EOT): 2.8 nm) and thick (physical thickness, ∼8.2 nm, EOT: 4.3 nm) Al2O3 layers showed a good leakage current density of −5.4×10−6 A/cm2 and −2.5×10−9 A/cm2 at −1 V, respectively; good reliability characteristics as a result of the good surface roughness; low capacitance versus
voltage measurements (C-V) hysteresis; and a good interface state density (∼7×1010 cm−2eV−1 near the midgap) as a result of pre-rapid thermal annealing (pre-RTA) after depositing the Al2O3 layer compared with the single MOS capacitors without the pre-RTA. These results suggest that dual Al2O3 layers using the dual gate oxide (DGOX) process can be used for the simultaneous integration of the low power transistors
with a thin Al2O3 layer and high reliability regions with a thick Al2O3 layer. 相似文献