Measurement of As diffusivity in Ni2Si thin films

The lattice and grain boundary diffusion coefficients of As in 260 nm-thick Ni₂Si films were measured. The Ni₂Si layers were prepared via the reaction between a Si layer deposited by low pressure chemical vapor deposition and a Ni layer deposited by magnetron sputtering on a Si substrate covered with a SiO₂ film. As was implanted in the silicide. Its concentration profiles were measured using secondary ion mass spectroscopy before and after annealing (550-700 °C). 2D finite element diffusion simulations taking into account lattice diffusion and grain boundary (GB) diffusion were performed based on the microstructure of the samples. They were found to fit accurately the measured profiles and allowed to measure the diffusion coefficients for each temperature. Lattice diffusion is characterized by a pre-exponential factor D⁰v ∼ 1.5 × 10⁻¹ cm² s⁻¹ and an activation energy Qv ∼ 2.72 eV. In the case of GB diffusion P⁰ = sδD⁰gb = 9.0 × 10⁻³ cm³ s⁻¹ and the activation energy was found to be higher than for lattice diffusion with Qgb ∼ 3.07 eV. Existing data concerning diffusion in silicides and other materials is used to discuss these results. The diffusion of As in Ni₂Si could be reduced due to impurity segregation in GBs.     

A novel thermally-stable zirconium amidinate ALD precursor for ZrO2 thin films

ZrO₂ thin films were deposited by the atomic layer deposition process on Si substrates using tetrakis(N,N′-dimethylacetamidinate) zirconium (Zr-AMD) as a Zr precursor and H₂O as an oxidizing agent. Tetrakis (ethylmethylamino) zirconium (TEMA-Zr) was also evaluated for a comparative study. Physical properties of ALD-derived ZrO₂ thin films were studied using ellipsometry, grazing incidence XRD (GI-XRD), high resolution TEM (HRTEM), and atomic force microscopy (AFM). The ZrO₂ deposited using Zr-AMD showed a better thermal stability at high substrate temperature (>300 °C) compared to that using TEMA-Zr. GI-XRD analysis reveals that after 700 °C anneal both ZrO₂ films enter tetragonal phase. The electrical properties of N₂-annealed ZrO₂ film using Zr-AMD exhibit an EOT of 1.2 nm with leakage current density as low as 2 × 10⁻³ A/cm² (@V_fb−1 V). The new Zr amidinate is a promising ALD precursor for high-k dielectric applications.     

The structural and electrical properties of the SrTa2O6/In0.53Ga0.47As/InP system

The structural and electrical properties of SrTa₂O₆(SrTaO)/n-In_0.53GaAs_0.47(InGaAs)/InP structures where the SrTaO was grown by atomic vapor deposition, were investigated. Transmission electron microscopy revealed a uniform, amorphous SrTaO film having an atomically flat interface with the InGaAs substrate with a SrTaO film thickness of 11.2 nm. The amorphous SrTaO films (11.2 nm) exhibit a dielectric constant of ∼20, and a breakdown field of >8 MV/cm. A capacitance equivalent thickness of ∼1 nm is obtained for a SrTaO thickness of 3.4 nm, demonstrating the scaling potential of the SrTaO/InGaAs MOS system. Thinner SrTaO films (3.4 nm) exhibited increased non-uniformity in thickness. From the capacitance-voltage response of the SrTaO (3.4 nm)/n-InGaAs/InP structure, prior to any post deposition annealing, a peak interface state density of ∼2.3 × 10¹³ cm⁻² eV⁻¹ is obtained located at ∼0.28 eV (±0.05 eV) above the valence band energy (E_v) and the integrated interface state density in range E_v + 0.2 to E_v + 0.7 eV is 6.8 × 10¹² cm⁻². The peak energy position (0.28 ± 0.05 eV) and the energy distribution of the interface states are similar to other high-k layers on InGaAs, such as Al₂O₃ and LaAlO₃, providing further evidence that the interface defects in the high-k/InGaAs system are intrinsic defects related to the InGaAs surface.     

Correlation between chemical and electrical profiles in Si+, Se+ and S+ implanted bulk and epitaxial GaAs

We compare the chemical profiles of Cr, Mn, Si and Se with the electron concentration profiles in Si, Se and S implanted semi-insulating Cr-O doped bulk GaAs substrates and undoped VPE buffer layers annealed with and without a SiO₂ encapsulant in a H₂-As₄ atmosphere. A higher activation efficiency in the net electron concentration and the gateless saturated channel current is measured for SiO₂ encapsulated wafers annealed under arsine overpressure than for capless annealed ones using Cr-O doped bulk GaAs substrates. On the other hand, the net donor concentration peak is higher for implanted buffer epi layers capless annealed under arsine overpressure than for SiO₂ encapsulated ones. Secondary ion mass spectrometry (SIMS) studies of the Cr decoration of the implant damage indicate that the damage from the 100 keV Si implant anneals out at 840°C while a temperature of 900°C is required to anneal out the 260 keV Se implant damage. An explanation of these differences is provided using an impurity redistribution model and charge neutrality considerations. Excellent Hall electron mobilities at liquid nitrogen temperature of 5400–9200 cm²/V-sec are measured for Si-implanted buffer epi substrates.     

A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

Annealing effects on electrical characteristics and reliability of MOS device with HfO₂ or Ti/HfO₂ high-k dielectric are studied in this work. For the sample with Ti/HfO₂ higher-k dielectric after a post-metallization annealing (PMA) at 600 °C, its equivalent oxide thickness value is 7.6 Å and the leakage density is about 4.5 × 10⁻² A/cm². As the PMA is above 700 °C, the electrical characteristics of MOS device would be severely degraded.     

Effective formation of interface controlled Y2O3 thin film on Si(1 0 0) in a metal-(ferroelectric)-insulator-semiconductor structure

Yttrium was deposited on the chemical oxide of Si and annealed under vacuum to control the interface for the formation of Y₂O₃ as an insulating barrier to construct a metal-ferroelectric-insulator-semiconductor structure. Two different pre-annealing temperatures of 600 and 700 °C were chosen to investigate the effect of the interface state formed after the pre-annealing step on the successive formation of Y₂O₃ insulator and Nd₂Ti₂O₇ (NTO) ferroelectric layer through annealing under an oxygen atmosphere at 800 °C. Pre-anneal treatments of Y-metal/chemical-SiO₂/Si at 600 and 700 °C induced a formation of Y₂O₃ and Y-silicate, respectively. The difference in the pre-anneal temperature induced almost no change in the electrical properties of the Y₂O₃/interface/Si system, but degraded properties were observed in the NTO/Y₂O₃/interface/Si system pre-annealed at 600 °C when compared with the sample pre-annealed at 700 °C. C-V characteristics of the NTO/Y₂O₃/Si structured system showed a clockwise direction of hysteresis, and this gap could be used as a memory window for a ferroelectric-gate. A smaller hysteric gap and electrical breakdown values were observed in the NTO/Y₂O₃/Si system pre-annealed at 600 °C, and this was due to an unintentional distribution of the applied field from the presence of an interfacial layer containing Y-silicate and SiO₂ phases.     

Interface state densities, low frequency noise and electron mobility in surface channel In0.53Ga0.47As n-MOSFETs with a ZrO2 gate dielectric

This paper reports on an investigation of interface state densities, low frequency noise and electron mobility in surface channel In_0.53Ga_0.47As n-MOSFETs with a ZrO₂ gate dielectric. Interface state density values of D_it ∼ 5 × 10¹² cm⁻² eV⁻¹ were extracted using sub-threshold slope analysis and charge pumping technique. The same order of magnitude of trap density was found from low frequency noise measurements. A peak effective electron mobility of 1200 cm²/Vs has been achieved. For these surface channel In_0.53Ga_0.47As n-MOSFETs, it was found that η parameter, an empirical parameter used to calculate the effective electric field, was ∼0.55, and is to be comparable to the standard value found in Si device.     

Thermal stability of Ni silicide films on heavily doped n and p Si substrates

Electrical and structural properties of Ni silicide films formed at various temperatures ranged from 200 °C to 950 °C on both heavily doped n⁺ and p⁺ Si substrates were studied. It was found that surface morphology as well as the sheet resistance properties of the Ni silicide films formed on n⁺ and p⁺ Si substrates at the temperatures higher than 600 °C were very different. Agglomerations of Ni silicide films on n⁺ Si substrates begin to occur at around 600 °C while there is no agglomeration observed in Ni silicide films on p⁺ Si substrates up to a forming temperature of 700 °C. It was also found that the phase transition temperature from NiSi phase to NiSi₂ phase depend on substrate types; 900 °C for NiSi film on n⁺ Si substrate and 750 °C for NiSi film on p⁺ Si substrate, respectively. Our results show that the agglomeration is, especially, important factor in the process temperature dependency of the sheet resistance of Ni silicides formed on n⁺ Si substrates.     

Charge trapping and interface characteristics in normally-off Al2O3/GaN-MOSFETs

Normally-off GaN-MOSFETs with Al₂O₃ gate dielectric have been fabricated and characterized. The Al₂O₃ layer is deposited by ALD and annealed under various temperatures. The saturation drain current of 330 mA/mm and the maximum transconductance of 32 mS/mm in the saturation region are not significantly modified after annealing. The subthreshold slope and the low-field mobility value are improved from 642 to 347 mV/dec and from 50 to 55 cm² V⁻¹ s⁻¹, respectively. The I_D-V_G curve shows hysteresis due to oxide trapped charge in the Al₂O₃ before annealing. The amount of hysteresis reduces with the increase of annealing temperature up to 750 °C. The Al₂O₃ layer starts to crystallize at a temperature of 850 °C and its insulating property deteriorates.     

Atomic-layer-deposited tantalum silicate as a gate dielectric for III-V MOS devices

TaSiO_x thin films with Si/(Ta + Si) mole fractions between 0 and 0.6 have been deposited using atomic-layer deposition on Si and InGaAs at 250 °C. Interface defects on InGaAs were on the order of 10¹² cm⁻² eV⁻¹, which is comparable to state-of-the-art Al₂O₃ deposited by atomic-layer deposition using Al(CH₃)₃ and H₂O while the dielectric permittivity of TaSiO_x is considerably higher.     

In0.53Ga0.47As(1 0 0) native oxide removal by liquid and gas phase HF/H2O chemistries

The native oxide removal, surface termination, and stoichiometry of InGaAs(1 0 0) surfaces using liquid and gas phase HF/H₂O etching were studied using X-ray photoelectron spectroscopy. Oxide removal in liquid phase HF stopped at the As layer, producing either elemental or H-terminated As. The surface oxidized upon air exposure, forming a 4.8 Å As₂O₃ layer on an As rich InGaAs sub-surface (17% In, 16% Ga, 66% As). A sub atmospheric gas phase HF/H₂O process (100 Torr, 29 °C, 0.5 min) completely removed As₂O₃ and produced mainly In and Ga fluorides, since As fluoride is volatile at these experimental conditions. Once enough F accumulated on the surface, the water sticking probability decreased and the etching reaction proceeded at a much lower rate. The highest oxide removal (4.2 Å residual oxide) was achieved after 5 min of etching. As₂O₃ and As₂O₅ were completely removed and considerably more InF₃ and GaF₃ were produced. The surface contained a group III-fluoride rich overlayer (34% In, 36% Ga) on a slightly As rich bulk (21% In, 21% Ga, and 58% As). The As rich InGaAs sub-surface produced with both liquid and the longer gas phase HF treatments is intrinsic to HF-InGaAs chemistry, although the oxide removal mechanism is likely different.     

MOS devices with tetragonal ZrO2 as gate dielectric formed by annealing ZrO2/Ge/ZrO2 laminate

A Ge-stabilized tetragonal ZrO₂ (t-ZrO₂) film with permittivity (κ) of 36.2 was formed by depositing a ZrO₂/Ge/ZrO₂ laminate and a subsequent annealing at 600 °C, which is a more reliable approach to control the incorporated amount of Ge in ZrO₂. On Si substrates, with thin SiON as an interfacial layer, the SiON/t-ZrO₂ gate stack with equivalent oxide thickness (EOT) of 1.75 nm shows tiny amount of hysteresis and negligible frequency dispersion in capacitance-voltage (C-V) characteristics. By passivating leaky channels derived from grain boundaries with NH₃ plasma, good leakage current of 4.8 × 10⁻⁸ A/cm² at V_g = V_fb − 1 V is achieved and desirable reliability confirmed by positive bias temperature instability (PBTI) test is also obtained.     

High thermal stability AlGaAs/InGaAs enhancement-mode pHEMT using palladium-gate technology

The dc, flicker noise, power, and temperature dependence of AlGaAs/InGaAs enhancement-mode pseudomorphic high electron mobility transistors (E-pHEMTs) were investigated using palladium (Pd)-gate technology. Although the conventional platinum (Pt)-buried gate has a high metal work function, which is beneficial for increasing the Schottky barrier height of the E-pHEMT, the high rate of intermixing of the Pt-GaAs interface owing to the effect of the continuous production of PtAs₂ on the device influenced the threshold voltage (V_th) and transconductance (g_m) at high temperatures or over the long-term operation. Variations in these parameters make Pt-gate E-pHEMT-related circuits impractical. Furthermore, a PtAs₂ interlayer caused a serious gate leakage current and unstable Schottky barrier height. This study presents the Pd-GaAs Schottky contact because Pd, an inert material with high work function of 5.12 eV. Stable Pd inhibited the less diffusion at high temperatures and simultaneously suppressed device flicker noise. The V_th of Pd/Ti/Au Schottky gate E-pHEMT was 0.183 V and this value shifted to 0.296 V after annealing at 200 °C. However, the V_th shifted from 0.084 to 0.231 V after annealing of the Pt/Ti/Au Schottky gate E-pHEMT because the Pt sunk into a deeper channel. The slope of the curve of power gain cutoff frequency (f_max) as a function of temperature was −5.76 × 10⁻² GHz/°C for a Pd/Ti/Au-gate E-pHEMT; it was −9.17 × 10⁻² GHz/°C for a Pt/Ti/Au-gate E-pHEMT. The slight variation in the dc and radio-frequency characteristics of the Pd/Ti/Au-gate E-pHEMT at temperatures from 0 to 100 °C revealed that the Pd-GaAs interface has great potential for high power transistors.     

Low gate interface traps AlGaN/GaN HEMTs using a lattice matched ZrZnO transparent gate design

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) using a radio-frequency magnetron sputtered ZrZnO transparent oxide layer as a gate insulator are investigated and compared with traditional GaN HEMTs. A negligible hysteresis voltage shift in the C–V curves is seen, from 0.09 V to 0.36 V, as the thickness of ZrZnO films increases. The composition of ZrZnO at different annealing temperatures is observed using X-ray photoelectron spectroscopy (XPS). The ZrZnO thin film achieves good thermal stability after 600 °C, 700 °C and 800 °C post-deposition annealing (PDA) because of its high binding energy. Based on the interface trap density analysis, D_it has a value of 2.663 × 10¹² cm⁻²/eV for 10-nm-thick ZrZnO-gate HEMTs and demonstrates better interlayer characteristics, which results in a better slopes for the I_ds degradation (5.75 × 10⁻¹ mA/mm K⁻¹) for operation from 77 K to 300 K. The 10-nm-thick ZrZnO-gate device also exhibits a flat and a stable 1/f noise, as V_GS–V_th, and at various operating temperatures. Therefore, ZrZnO has good potential for use as the transparent film for a gate insulator that improves the GaN-based FET threshold voltage and improves the number of surface defects at various operating temperatures.     

Effects of annealing schedule on orientations of Bi3.2Nd0.8Ti3O12 ferroelectric films prepared by metalorganic solution deposition

Fatigue-free Bi_3.2Nd_0.8Ti₃O₁₂ ferroelectric thin films were successfully prepared on p-Si(1 1 1) substrate using metalorganic solution deposition process. The orientation and formation of thin film under different annealing schedules were studied using XRD and AFM. XRD analysis indicated that (2 0 0)-oriented films with degree of orientation of I₍₂₀₀₎/I₍₁₁₇₎ = 2.097 and 0.466 were obtained by preannealing the film at 400 °C for 10 min followed by rapid thermal annealing at 700 °C for 3 min, 10 min and 20 min, respectively, (0 0 8)-oriented film with degree of orientation of I₍₀₀₈₎/I₍₁₁₇₎ = 1.706 were obtained by rapid thermal annealing the film at 700 °C for 3 min without preannealing, and (0 0 8)-oriented film with degree of orientation of I₍₀₀₈₎/I₍₁₁₇₎ = 0.719 were obtained by preheating the film from room temperature to 700 °C at 20 °C/min followed by annealing for 10 min. The a-axis and c-axis orientation decreased as increase in annealing time due to effects of (1 1 1)-oriented substrate. AFM analysis further indicated that preannealing at 400 °C for 10 min followed by rapid thermal annealing at 700 °C for 3 min resulted in formation of platelike crystallite parallel to substrate surface, however rapid thermal annealing at 700 °C for 3 min without preannealing resulted in columnar crystallite perpendicular to substrate surface.     

Improving electrical characteristics of W/HfO2/In0.53Ga0.47As gate stacks by altering deposition techniques

The effects of controlling InGaAs substrate temperature during electron beam deposition of HfO₂ on electrical characteristics of W/HfO₂/n-In_0.53Ga_0.47As capacitors are investigated. It is found that by depositing a thin HfO₂ layer at the interface when substrate temperature is raised to 300 °C, frequency dispersion at depletion and accumulation conditions is reduced and interface state density is lowered regardless of the HfO₂ thickness. Cross-sectional transmission electron microscopy images have revealed that the formation of mesoscopic voids in the InGaAs substrate near the interface is suppressed with HfO₂deposition at 300 °C at the interface. A band diagram with an additional bulk trap energy level has been proposed to explain the frequency dispersion and conductance peaks at accumulation condition.     

Remote phonon and surface roughness limited universal electron mobility of In0.53Ga0.47As surface channel MOSFETs

The inversion layer electron mobility in n-channel In_0.53Ga_0.47As MOSFET’s with HfO₂ gate dielectric with several substrate impurity concentrations (∼1 × 10¹⁶ cm⁻³ to ∼1 × 10¹⁸ cm⁻³) and various surface preparations (HF surface clean, (NH₄)₂S surface clean and PECVD a-Si interlayer with a HfO₂ gate dielectric) have been studied. The peak electron mobility is observed to be strongly dependent on the surface preparation, but the high field mobility is observed to be almost independent of the surface preparation. A detailed analysis of the effective mobility as a function of electric field, substrate doping, and temperature was used to determine the various mobility components (surface roughness, phonon, and coulombic scattering limited mobility components). For the substrates with high doping concentration, the electron mobility at low vertical electric field is dominated by Coulomb scattering from the substrate dopants, whereas, for lower substrate doping the Coulombic scattering is dominated by the disorder induced gap states. Low temperature measurements were used to determine the surface roughness scattering and phonon components. The results show that room temperature mobility of In_0.53Ga_0.47As surface channel MOSFETs with HfO₂ gate dielectric at high electric field is limited primarily by remote phonons whereas the Al₂O₃ gate dielectric is limited by surface roughness scattering.     

Investigation of atomic vapour deposited TiN/HfO2/SiO2 gate stacks for MOSFET devices

HfO₂ films were grown by atomic vapour deposition (AVD) on SiO₂/Si (1 0 0) substrates. The positive shift of the flat band voltage of the HfO₂ based metal-oxide-silicon (MOS) devices indicates the presence of negative fixed charges with a density of 5 × 10¹² cm⁻². The interface trap charge density of HfO₂/SiO₂ stacks can be reduced to 3 × 10¹¹ eV⁻¹ cm⁻² near mid gap, by forming gas annealing. The extracted work function of 4.7 eV preferred the use of TiN as metal gate for PMOS transistors. TiN/HfO₂/SiO₂ gate stacks were integrated into gate-last-formed MOSFET structures. The extracted maximum effective mobility of HfO₂ based PMOS transistors is 56 cm²/Vs.     

High performance n/p and p/n germanium diodes at low-temperature activation annealing

In this work we demonstrate the fabrication and characterization of high performance junction diodes using annealing temperatures within the temperature range of 300-350 °C. The low temperature dopant activation was assisted by a 50 nm platinum layer which transforms into platinum germanide during annealing. The fabricated diodes exhibited high forward currents, in excess of 400 A/cm² at ∼|0.7| V for both p⁺/n and n⁺/p diodes, with forward to reverse ratio I_F/I_R greater than 10⁴. Best results for the n⁺/p junctions were obtained at the lower annealing temperature of 300 °C. These characteristics compare favorably with the results of either conventional or with Ni or Co assisted dopant activation annealing. The low-temperature annealing in combination with the high forward currents at low bias makes this method suitable for high performance/low operating power applications, utilizing thus high mobility germanium substrates.     

Influence of rapid thermal annealing temperature on structure and electrical properties of high permittivity HfTiO thin film used in MOSFET

HfTiO thin films were prepared by r.f. magnetron co-sputtering on Si substrate. To improve the electrical properties, HfTiO thin films were post heated by rapid thermal annealing (RTA) at 400 °C, 500 °C, 600 °C and 700 °C in nitrogen. It was found that the film is amorphous below 700 °C and at 700 °C monoclinic phase HfO₂ has occurred. With the increase of the annealing temperature, the film becomes denser and the refractive index increases. By electrical measurements, we found at 500 °C annealed condition, the film has the best electrical property with the largest dielectric constant of 44.0 and the lowest leakage current of 1.81 × 10⁻⁷ A/cm², which mainly corresponds to the improved microstructure of HfTiO thin film. Using the film annealed at 500 °C as the replacement of SiO₂ dielectric layer in MOSFET, combining with TiAlN metal electrode, a 10 μm gate-length MOSFET fabricated by three-step photolithography processes. From the transfer (I_DS–V_G) and output (I_DS–V_DS) characteristics, it shows a good transistor performance with a threshold voltage (V_th) of 1.6 V, a maximum drain current (I_ds) of 9 × 10⁻⁴ A, and a maximum transconductance (G_m) of 2.2 × 10⁻⁵ S.