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1.
After a long period of developing integrated circuit technology through simple scaling of silicon devices, the semiconductor industry is now embracing technology boosters such as strain for higher mobility channel material. Germanium is the logical supplement to enhance existing technologies, as its material behaviour is very close to silicon, and to create new functional devices that cannot be fabricated from silicon alone (Hartmann et al. (2004) [1]). Germanium wafers are, however, both expensive and less durable than their silicon counterparts. Hence it is highly desirable to create a relaxed high quality Ge layer on a Si substrate, with the provision that this does not unduly compromise the planarity of the system. The two temperature method, proposed by Colace et al. (1997) [2], can give smooth (RMS surface roughness below 1 nm) and low threading dislocation density (TDD <108 cm−2) Ge layers directly on a Si(0 0 1) wafer (Halbwax et al. (2005) [3]), but these are currently of the order of 1-2 μm thick (Hartmann et al. (2009) [4]).We present an in depth study of two temperature Ge layers, grown by reduced pressure chemical vapour deposition (RP-CVD), in an effort to reduce the thickness. We report the effect of changing the thickness, of both the low temperature (LT) and the high temperature (HT) layers, emphasising the variation of TDD, surface morphology and relaxation.Within this study, the LT Ge layer is deposited directly on a Si(0 0 1) substrate at a low temperature of 400 °C. This low temperature is known to generate monolayer islands (Park et al. (2006) [5]), but is sufficiently high to maintain crystallinity whilst keeping the epitaxial surface as smooth as possible by suppressing further island growth and proceeding in a Frank-van der Merwe growth mode. This LT growth also generates a vast number of dislocations, of the order of 108-109 cm−2, that enable the next HT step to relax the maximum amount of strain possible. The effect of varying the HT layer thickness is studied by depositing on a LT layer of fixed thickness (100 nm) at a higher growth temperature of 670 °C. We find that the HT layer allows Ge-on-Ge adatom transport to minimise the surface energy and smooth the layer. The final step to the technique is annealing at a high temperature that allows the dislocations generated to glide, increasing the degree of relaxation, and annihilate. We find that annealing can reduce the TDD to the order of 107 cm−2, but at a cost of a significantly roughened surface.  相似文献   

2.
We have investigated the crystalline orientation dependence of the electrical properties of Mn germanide/Ge(1 1 1) and (0 0 1) Schottky contacts. We prepared epitaxial and polycrystalline Mn5Ge3 layers on Ge(1 1 1) and (0 0 1) substrates, respectively. The Schottky barrier height (SBH) estimated from the current density-voltage characteristics for epitaxial Mn5Ge3/Ge(1 1 1) is as low as 0.30 eV, while the SBH of polycrystalline Mn5Ge3/Ge(0 0 1) is higher than 0.56 eV. On the other hand, the SBH estimated from capacitance-voltage characteristics are higher than 0.6 eV for both samples. The difference of these SBHs can be explained by the local carrier conduction through the small area with the low SBH regions in the epitaxial Mn5Ge3/Ge(1 1 1) contact. This result suggests the possibility that the lowering SBH takes place due to Fermi level depinning in epitaxial germanide/Ge(1 1 1) contacts.  相似文献   

3.
Density functional theory was used to performed a survey of transition metal oxide (MO2 = ZrO2, HfO2) ordered molecular adsorbate bonding configurations on the Ge(1 0 0)-4 × 2 surface. Surface binding geometries of metal-down (O-M-Ge) and oxygen-down (M-O-Ge) were considered, including both adsorbate and displacement geometries of M-O-Ge. Calculated enthalpies of adsorption show that bonding geometries with metal-Ge bonds (O-M-Ge) are essentially degenerate with oxygen-Ge bonding (M-O-Ge). Calculated electronic structures indicate that adsorbate surface bonding geometries of the form O-M-Ge tend to create a metallic interfaces, while M-O-Ge geometries produce, in general, much more favorable electronic structures. Hydrogen passivation of both oxygen and metal dangling bonds was found to improve the electronic structure of both types of MO2 adsorbate systems, and induced the opening of true semiconducting band gaps for the adsorbate-type M-O-Ge geometries. Shifts observed in the DOS minima for both O-M-Ge and M-O-Ge adsorbate geometries are consistent with surface band bending induced by the adsorbate films, where such band bending extends much further into the Ge substrate than can be modeled by the Ge slabs used in this work.  相似文献   

4.
Ultra-thin films of Dy are grown on Ge(0 0 1) substrates by molecular beam deposition near room temperature and immediately annealed for solid phase epitaxy at higher temperatures, leading to the formation of DyGex films. Thin films of Dy2O3 are grown on the DyGex film on Ge(0 0 1) substrates by molecular beam epitaxy. Streaky reflection high energy electron diffraction (RHEED) patterns reveal that epitaxial DyGex films grow on Ge(0 0 1) substrates with flat surfaces. X-ray diffraction (XRD) spectrum suggests the growth of an orthorhombic phase of DyGex films with (0 0 1) orientations. After the growth of Dy2O3 films, there is a change in RHEED patterns to spotty features, revealing the growth of 3D crystalline islands. XRD spectrum shows the presence of a cubic phase with (1 0 0) and (1 1 1) orientations. Atomic force microscopy image shows that the surface morphology of Dy2O3 films is smooth with a root mean square roughness of 10 Å.  相似文献   

5.
GeO2 was proposed as valuable passivation layer at the surface with Ge to integrate oxide with high dielectric constant in Ge-based logic devices. Hence, the identification of the defects present at different Ge/GeO2 interfaces becomes a mandatory issue to predict the electrical features of devices based on such materials. High sensitive electrically detected magnetic resonance measurements were performed to study the microstructure of defects occurring at such an interface. The influence of the oxidation temperature on the electrically active paramagnetic traps was investigated.  相似文献   

6.
The lateral growth of Ge on, both, chemically and thermally formed silicon oxide layers, from nanoscale silicon seed is studied. We have developed a method using standard local oxidation of silicon to create well-localized nanoscale silicon seeds that enable to grow Ge on thick thermal silicon oxide. The germanium growth starts selectively from the silicon seed lines and proceeds by wetting the SiO2 layer. Analysis by high-resolution transmission electron microscopy have shown that Ge layers grown above silicon oxide were perfectly monocrystalline and are free of defect. The only detected defects are situated at the Ge/Si interface.  相似文献   

7.
The identification of a nontrigonal Ge dangling bond at SiO2/Si1−xGex/SiO2 heterostructures and its electrical activity are discussed, both from experimental and theoretical points of view. This dangling bond is observed from multifrequency electron-spin resonance experiments performed at 4.2 K, for typical Ge concentrations in the range 0.4 ≤ x ≤ 0.85. The electrical activity of this defect is revealed from capacitance-voltage characteristics measured at 300 and 77 K, and is found to behave like an acceptor defect. First-principles calculations of the electronic properties of this Ge dangling bond indicate that its energy level approaches the valence band edge of the Si1−xGex layer as the Ge content increases, confirming its acceptor-like nature.  相似文献   

8.
The electrical characterization of Ge pMOSFETs having <1 1 0> and <1 0 0> orientations with gate lengths of 3 μm have been demonstrated with a Si-compatible process flow. Employment of <1 0 0> orientation in Ge pMOSFETs without incorporation of strain provided ∼10% enhancement in effective hole mobility and drive current when compared to <1 1 0> oriented regular transistors. In this fabrication technology, the effective hole mobility improves from 190 cm2/V s for <1 1 0> devices to 210 cm2/V s for the <1 0 0> oriented Ge devices at room temperature, which is ∼2 times the hole mobility of Si pFET devices. This study also presents first time investigation of post metallization anneal (PMA) at 350 °C in H2 ambient for <1 0 0> Ge pMOSFETs. The overall performance of the devices has been enhanced by 15% after performing PMA. It is likely attributed to a strong decrease of Dit, improving the transistor performance. These results indicate that the <1 0 0> Ge pMOSFETs could be a viable candidate for future low voltage high speed CMOS applications.  相似文献   

9.
Dy thin films are grown on Ge(0 0 1) substrates by molecular beam deposition at room temperature. Subsequently, the Dy film is annealed at different temperatures for the growth of a Dy-germanide film. Structural, morphological and electrical properties of the Dy-germanide film are investigated by in situ reflection high-energy electron diffraction, and ex situ X-ray diffraction, atomic force microscopy and resistivity measurements. Reflection high-energy electron diffraction patterns and X-ray diffraction spectra show that the room temperature growth of the Dy film is disordered and there is a transition at a temperature of 300-330 °C from a disordered to an epitaxial growth of a Dy-germanide film by solid phase epitaxy. The high quality Dy3Ge5 film crystalline structure is formed and identified as an orthorhombic phase with smooth surface in the annealing temperature range of 330-550 °C. But at a temperature of 600 °C, the smooth surface of the Dy3Ge5 film changes to a rough surface with a lot of pits due to the reactions further.  相似文献   

10.
A study of the structural and optical properties of an InAsP/InP quantum well heterostructure grown on a crystalline SrTiO3 (STO)/Si(0 0 1) template is presented. The mismatch between InP and STO is fully accommodated by an array of geometric dislocations confined at the heterointerface. As a consequence, InP takes its bulk lattice parameter as soon as growth begins, and does not contain threading dislocations related to plastic relaxation. It contains twins related to the initially three-dimensional growth. Despite these twins, photoluminescence from the quantum well is detected at room temperature, showing that STO/Si(0 0 1) templates have an interesting potential for the monolithic integration of III-V semiconductors on silicon.  相似文献   

11.
A fundamental issue regarding the introduction of high-mobility Ge channels in CMOS circuits is the electrical passivation of the interface with the high-k gate dielectric. In this paper, we investigate the passivation of p-Ge(0 0 1) using molecular H2S. The modification of the semiconductor surface is monitored in situ by RHEED and the interface is characterized by XPS analyses. MOS capacitors are fabricated to extract interface state density, and finally we demonstrate the efficiency of the passivation scheme using a combination with an ultra thin Al interlayer.  相似文献   

12.
We have demonstrated that sub-10 nm-thick heteroepitaxial Ge films on Si (001) having smooth surfaces can be obtained by DC magnetron sputtering. Ge films grown at 350 °C preserve the smooth surfaces with a roughness root mean square (RMS) of 0.39 nm, whereas, the Ge films grown at 500 °C show significant roughness with an island-like morphology. In samples grown at 350 °C, it is confirmed that the Ge films are grown epitaxially by cross-section transmission electron microscopy (TEM) and X-ray diffraction (XRD) rocking curve measurements. Rapid thermal annealing (RTA) at 720 °C is effective in improving the crystalline quality and the degradation in the roughness is negligible. Raman spectra and an XRD reciprocal space map reveal that the epitaxial Ge grown at 350 °C show an in-plane compressive strain and that the strain continues to remain after a 720 °C RTA.  相似文献   

13.
The flattening speed of the low temperature atomically flattening technology is evaluated in order to apply atomically flat surface of (1 0 0) orientation on large-diameter silicon wafers to the LSI manufacturing. The atomically flatness of the whole surface of wafers with the diameter of 200 mm can be obtained after annealing at 800 °C or above. The process time required to obtain the atomically flatness for the whole wafer surface can be shortened by increasing the annealing temperature as well as by increasing the gas flow rate. With the off angle of 0.50° or below, it was found that only mono-atomic steps appear on the surfaces and the flattening speed is independent of the off angle. These indicate that the process speed is independent of the migration speed of Si atoms on the surface, but depends on the gas replacement efficiency near the Si surface in this technique.  相似文献   

14.
Experiments on the diffusion of Si and Ge in Si1-xGex-isotope heterostructures with Ge contents x=0, 0.05, and 0.25 were performed at temperatures between 870 and . The concentration profiles of the stable Si- and Ge-isotopes were recorded by means of time-of-flight secondary ion mass spectrometry. For all compositions, an Arrhenius type temperature dependence of diffusion was observed. The activation enthalpy of Si diffusion in SiGe equals the activation enthalpy of Ge diffusion and the pre-exponential factors agree within experimental accuracy. However, the absolute values of the Si and Ge diffusion coefficients indicate a clear trend. In elemental Si the diffusion coefficients of Si and Ge agree, but the difference between the diffusion coefficients of Ge and Si in Si1-xGex increases with x. This indicates that with increasing Ge content the diffusional jumps of Ge atoms become more successful compared to that of Si. This trend is explained with an increasing contribution of vacancies to self-diffusion in Si1-xGex with an increase of the Ge content x.  相似文献   

15.
The energy distribution of extended and localized electron states at the Ge/HfO2 interface is determined by combining the internal photoemission of electrons and holes from Ge into the Hf oxide and AC capacitance/conductance measurements. The inferred offsets of the conduction and valence band at the interface, i.e., 2.0 ± 0.1 and 3.0 ± 0.1 eV, respectively, suggest the possibility to apply the deposited HfO2 layer as a suitable insulator on Ge. The post-deposition annealing of the Ge/HfO2 structures in oxygen results in 1 eV reduction of the valence band offset, which is attributed to the growth of a GeO2 interlayer. However, this treatment enables one to substantially reduce the density of Ge/HfO2 interface traps, approaching ≈1×1012 cm−2 eV−1 near the Ge midgap.  相似文献   

16.
Epitaxial Ge layer growth of low threading dislocation density (TDD) and low surface roughness on Si (1 0 0) surface is investigated using a single wafer reduced pressure chemical vapor deposition (RPCVD) system. Thin seed Ge layer is deposited at 300 °C at first to form two-dimensional Ge surface followed by thick Ge growth at 550 °C. Root mean square of roughness (RMS) of ∼0.45 nm is achieved. As-deposited Ge layers show high TDD of e.g. ∼4 × 108 cm−2 for a 4.7 μm thick Ge layer thickness. The TDD is decreasing with increasing Ge thickness. By applying a postannealing process at 800 °C, the TDD is decreased by one order of magnitude. By introducing several cycle of annealing during the Ge growth interrupting the Ge deposition, TDD as low as ∼7 × 105 cm−2 is achieved for 4.7 μm Ge thick layer. Surface roughness of the Ge sample with the cyclic annealing process is in the same level as without annealing process (RMS of ∼0.44 nm). The Ge layers are tensile strained as a result of a higher thermal expansion coefficient of Ge compared to Si in the cooling process down to room temperature. Enhanced Si diffusion was observed for annealed Ge samples. Direct band-to-band luminescence of the Ge layer grown on Si is demonstrated.  相似文献   

17.
We report on the plasma-assisted molecular-beam epitaxial growth of (1 1 2¯ 2)-oriented GaN/AlN nanostructures on (1 1¯ 0 0) m-plane sapphire. Moderate N-rich conditions enable to synthesize AlN(1 1  2) directly on m-sapphire, with in-plane epitaxial relationships [1 1 2¯ 3¯]AlN∥[0 0 0 1]sapphire and [1  0 0]AlN∥[1 1 2¯ 0]sapphire. In the case of GaN, a Ga-excess of one monolayer is necessary to achieve two-dimensional growth of GaN(1 1 2¯ 2). Applying these growth conditions, we demonstrate the synthesis of (1 1 2¯ 2)-oriented GaN/AlN quantum well structures, showing a strong reduction of the internal electric field. By interrupting the growth under vacuum after the deposition of few monolayers of GaN under slightly Ga-rich conditions, we also demonstrate the feasibility of quantum dot structures with this orientation.  相似文献   

18.
《Microelectronics Journal》2007,38(4-5):606-609
Epitaxial lateral overgrowth (ELOG) was used to grow InP on GaAs(1 0 0) substrates by metalorganic chemical vapor deposition (MOCVD). The selectivity of InP by ELOG is excellent and the regrowth InP epilayers have good morphology without polycrystalline on SiO2 mask. The [01¯1] directional mask stripes and high V/III ratio are benefit to InP lateral growth. Compared to conventional direct growth, ELOG is effective in reducing the dislocation density, relaxing compressing strain in epilayers. In addition, the full width at half maximum (FWHM) of X-ray diffraction (XRD) ω scans and room temperature (RT) photoluminescence (PL) for a 3 μm thick epilayer by ELOG are 198 arcsec and 44 meV, respectively.  相似文献   

19.
The current-voltage characteristics of the metal-insulator-semiconductor tunneling structures with calcium fluoride are simulated using different theoretical models. The results are compared to the data of current measurements on the fabricated capacitors with 1-3 nm epitaxial fluorides. Best agreement is achieved imposing a condition of transverse momentum k conservation for a tunneling electron. This fact may be treated as an experimental proof for the k conservation in the examined high-quality structures which was not directly confirmed on more traditional structures with oxide dielectrics.  相似文献   

20.
Lattice disregistry that exists in epitaxial overgrowths is often accommodated by interfacial dislocation arrays. The transition between strain accommodation by uniform interfacial shear and by interfacial dislocations is fairly sharp and thought to be controlled by energy minimization considerations. In this paper we demonstrate an extension of the Frank-van der Merwe approach by incorporating the continuum methodology of Eshelby to the analysis of strain interactions between arrays of interfacial dislocations in a bi-layered epitaxial film. Numerical examples are given for a Si/Si x Ge1-x /Si heterostructure. The importance of such an analysis to the study of defect propagation through strained layer superlattices is briefly discussed.  相似文献   

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