Electronic properties of GST for non-volatile memory

Impacts of annealing temperature and film thickness to the resistivity of Ge₂Sb₂Te₅(GST) have been studied. The resistivity of GST drops when the annealing temperature reaches 180 °C, rises above 360 °C and the thicker film crystallized more easily. Electronic device of phase change memory also has been fabricated with metal sidewall technology using 5 μm lithographic technology. The device was successfully programmed by 100 ns of 5 V pulse for SET and 10 ns of 10 V pulse for RESET. More than 100 times on/off ratio has been reached.     

Characterization of high-K/metal gate using picosecond ultrasonics

Transition from oxide gates to replacement metal gates is well underway and performance benefits have been demonstrated in state-of-the-art microprocessors. High-K/metal gate combination is important for all emerging new applications that require high-performance and low gate-leakage including all silicon and non-silicon nanoelectronic transistors. Picosecond ultrasonic measurements are used as checkpoints during various stages of development and integration of high-K/metal gate. The small spot, non-destructive nature of this technology allows for measurements directly on product wafers and on various line array structures in small measurement sites (30 μm × 30 μm). The technique has shown excellent correlation with cross-section TEM, demonstrating capability for monitoring advanced gate stacks. Picosecond ultrasonics provides high-throughput and can be used for in-line monitoring after the process is transferred to high volume manufacturing.     

Phase change materials and their application to random access memory technology

Phase change materials can exist in two different phases, the amorphous and the crystalline phase, which exhibit distinctly different physical properties. It is possible to repeatedly switch the state of these materials, from the amorphous phase to the crystalline phase by heating the material above its crystallization temperature, and from the crystalline to the amorphous phase by melt-quenching. Phase change materials have been utilized very successfully in all modern optical re-writable storage media such as CDs, DVDs and Blu-ray disks. Recently, they have also been applied to solid-state memory devices where their large difference in electrical resistivity is used to store information. This paper reviews the unique properties of phase change materials in particular as they are important for their application to these devices.     

嵌入式相变存储器的技术特点和研究现状

从2001年Intel在IEDM发表第一篇相变存储器的论文以来,相变存储器的发展十分迅猛.相变存储器由于具有非易失性、循环寿命长、元件尺寸小、功耗低、可多级存储、高速读取、抗辐射、耐高低温、抗振动、抗电子干扰和制造工艺简单等优点,被认为最有可能取代目前的FLASH和DRAM而成为未来半导体存储器主流产品.文中系统地介绍了嵌入式相变存储器的存储机理及其主要工作特点,从相变材料,器件结构,存储阵列等方面分析国内外研究现状,并讨论了器件失效与可靠性问题.     

Fabrication of Ge2Sb2Te5 based PRAM device at 60 nm scale by using UV nanoimprint lithography

Phase change memory is one of the most promising non-volatile memory for the next generation memory media due to its simplicity, wide dynamic range, fast switching speed and possibly low power consumption. Low power consuming operation of phase change random access memory (PRAM) can be achieved by confining the switching volume of phase change media into nanometer scale. Nanoimprint lithography is an emerging lithographic technique in which surface protrusions of a mold such as sub-100 nm patterns are transferred into a resin layer easily. In this study, crossbar structures of phase change device array based on Ge₂Sb₂Te₅ were successfully fabricated at 60 nm scale by two consecutive UV nanoimprint lithography and metal lift-off process, which showed on/off resistance ratio up to 3000.     

一种1kb相变存储芯片的设计

以中科院上海微系统与信息技术研究所自主研发的相变存储器工艺为基础,开发了一款容量为1 kb、可应用于射频标签(RFID)的嵌入式相变存储芯片.该芯片以1T1R为基本单元结构,采用箝位读出方式以及电流镜式写驱动电路,成功实现了相变存储器的读写功能.测试结果显示,该芯片可重复擦写次数达到107次,在80℃条件下数据保持力达...     

一种基于电流阶梯波的相变存储器擦驱动电路

基于相变存储器的擦操作(SET)特性,设计了一种能够产生电流阶梯波的相变存储器擦驱动电路,采用130 nm标准CMOS工艺将其与128 kb的相变存储器实验芯片集成.相比传统的单一电流脉冲擦驱动电路,这种改进后的擦驱动电路能将相变存储单元的电阻均值从15 kΩ左右降至7 kΩ左右,并且存储阵列的阻值分布一致性也得到提升...     

一种相变存储器读出电路及其快速读出方法

针对大规模相变存储器所具有的寄生电容大、可能出现读破坏现象等特性,提出了一种读电压模式的相变存储器读出电路及其快速读出方法。基于SMIC 40nm CMOS工艺的仿真结果表明,在2.5V电源电压下,该方法可以在90ns的读出周期内正确读出位线寄生电容为30pF的存储单元数据,同时,该读出周期随位线寄生电容的减小而减小。另外,该方法可以和传统的Burst等快速读出方式并存,非常适用于带数据预读机制的高端存储器技术。     

Fabrication process not limited by the lithography resolution of lateral phase change memory

To improve the performance of phase change memory (PCM) and reduce the cost of fabrication, we propose a new lateral PCM structure based on the technology of angle evaporation to define the critical dimension controllable, not limited by the limitation of lithography resolution. The fabrication process is cost-effective. PCM cells featured 80 nm×100 nm were successfully demonstrated, although the resolution of the aligned used was 1 µm only. Compared with the traditional lateral PCM structure, finite element simulation results show that the new structure has better thermal stability.     

基于编程电流/电压的相变存储器写驱动电路

相变存储器发生相变时各个单元存在差异性,为了改善其写入数据时的可靠性及芯片的成品率,设计了一种可分别用电流扣电压脉冲编程的写驱动电路.针对相变存储器SET过程的特性,写驱动电路可有选择地产生电流阶梯波或电压阶梯波.设计采用SMIC 130 nm CMOS标准工艺库.对相变存储单元进行了测试,结果表明,用电流梯度波写驱动电路替代传统单一脉高电流脉冲波写驱动电路,相变存储器的低阻分布更加集中,可提高实验芯片的成品率.     

相控阵天线波瓣置零综合的相位加权闭环实数算法

本文提出了一种相控阵天线仅相应加权波瓣置零的新算法,此算法基于“单元零点向量法”和Ｇｒａｍ－Ｓｃｈｍｉｄｔ正交化方法,它能有效地设置宽零点低凹口。另外,对由于 相位量化而引起的凹口电平上升也进行了分析。     

大型相控阵天线阵面相位中心定位技术研究

介绍了相位中心的定位方法--相位梯度法,分析了大型相控阵天线远场主瓣相位特性,明确指出大型相控阵天线相位中心位于天线的口径面上.在此基础上,结合相位梯度法与大型相控阵天线相位中心的特点,推导出了大型相控阵天线相位中心的定位方程组,该方程组可直接用于大型相控阵天线的相位中心定位,最后通过求解一个非对称加权的相控阵天线相位中心的实例验证了该大型相控阵天线相位中心定位技术的正确性.     

容量可变的嵌入式同步SRAM电路的设计与实现

提出了一种容量可变的嵌入式同步ＳＲＡＭ。通过采用存储阵列的分块,敏感放大器的分级等技术,对电路的结构进行了优化。着重讨论了存储阵列的分块原则,分析了分块的字长,字数对电路的面积,速度,功耗等因素的影响。     

基于PCRAM数据页聚簇的缓冲算法

针对Flash写前需擦除,读写I／0开销不均衡等固有缺陷,研究面向闪存缓冲区管理,对提高基于Flash的固态硬盘（Solid State Disk,SSD）访问性能以及降低系统功耗具有重要理论意义和应用价值。文章提出了一种新型存储架构,并实现了一种适用于SSD的基于相变存储器（Phase Change Memory,PCRAM）数据页聚簇的缓冲算法。文章中详细介绍了基于PCRAM聚簇的缓冲算法关键技术及原理,充分阐述算法相关元数据、存储数据、FTL管理与控制以及详尽分析了缓冲算法的读、写操作控制原理,最后通过F1ashSim仿真平台实现SSD写缓冲。基于仿真结果与传统缓冲算法性能比对,分析得出该缓冲算法可降低SSD随机写次数和SSD数据存储分散性,并提升SSD响应速度,降低系统功耗。