High mobility compressive strained Si0.5Ge0.5 quantum well p-MOSFETs with higher-k/metal-gate

Strained SiGe quantum well p-MOSFETs with LaLuO₃ higher-k dielectric were fabricated and characterized. The strained Si/strained Si_0.5Ge_0.5/strained SOI heterostructure transistors showed good output and transfer characteristics with an I_on/I_off ratio of 10⁵. The extracted hole mobility shows an enhancement of about 2.5 times over Si universal hole mobility and no degradation compared to HfO₂ or even SiO₂ gate dielectric devices.     

Fully strained Si0.75Ge0.25 epitaxial films with HfSiO gate dielectrics for high mobility channel metal-oxide semiconductor devices

The authors report on fully strained Si_0.75Ge_0.25 metal-oxide-semiconductor capacitors with HfSiO₂ high-k gate dielectric and TaN metal gate fabricated on Si substrates. Fully strained Si_0.75Ge_0.25 films are directly grown on Si substrates below the critical thickness. HfSiO₂ high-k gate dielectrics exhibit an equivalent oxide thickness of 13-18 Å with a permittivity of 17.7 and gate leakage current density lower than SiO₂ gate oxides by >100×. Interfacial oxide of the HfSiO₂/Si_0.75Ge_0.25 stack consists primarily of SiO₂ with a small amount of Ge and Hf. High performance SiGe field effect transistors are highly manufacturable with excellent electrical characteristics afforded by the fully strained HfSiO₂/SiGe gate stack.     

Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics

Low-frequency noise was characterized in Si_0.7Ge_0.3 surface channel pMOSFETs with ALD Al₂O₃/HfO₂/Al₂O₃ stacks as gate dielectrics. The influences of surface treatment prior to ALD processing and thickness of the Al₂O₃ layer at the channel interface were investigated. The noise was of the 1/f type and could be modeled as a sum of a Hooge mobility fluctuation noise component and a number fluctuation noise component. Mobility fluctuation noise dominated the 1/f noise in strong inversion, but the number fluctuation noise component, mainly originating from traps in HfO₂, also contributed closer to threshold and in weak inversion. The number fluctuation noise component was negligibly small in a device with a 2 nm thick Al₂O₃ layer at the SiGe channel interface, which reduced the average 1/f noise by a factor of two and decreased the device-to-device variations.     

Reliability assessment of SiO2/ZrO2 stack gate dielectric on strained-Si/Si0.8Ge0.2 heterolayers under dynamic and AC stress

The reliability characteristics of SiO₂/ZrO₂ gate dielectric stacks on strained-Si/Si_0.8Ge_0.2 have been investigated under dynamic and pulsed voltage stresses of different amplitude and frequency in order to analyze the transient response and the degradation of oxide as a function of stress parameters. The current transients observed in dynamic voltage stresses have been interpreted in terms of the charging/discharging of interface and bulk traps. The evolution of the current during unipolar pulsed voltage stresses shows the degradation being much faster at low frequencies than at high frequencies. Results have been compared with those obtained after CVS, as a function of injected charge and pulse frequency.     

Epitaxial strontium oxide layers on silicon for gate-first and gate-last TiN/HfO2 gate stack scaling

We show that a thin epitaxial strontium oxide (SrO) interfacial layer enables scaling of titanium nitride/hafnium oxide high-permittivity (high-k) gate stacks for field-effect transistors on silicon. In a low-temperature gate-last process, SrO passivates Si against SiO₂ formation and silicidation and equivalent oxide thickness (EOT) of 5 Å is achieved, with competitive leakage current and interface trap density. In a gate-first process, Sr triggers HfO₂-SiO₂ intermixing, forming interfacial high-k silicate containing both Sr and Hf. Combined with oxygen control techniques, we demonstrate an EOT of 6 Å with further scaling potential. In both cases, Sr incorporation results in an effective workfunction that is suitable for n-channel transistors.     

SiC MOSFETs with thermally oxidized Ta2Si stacked on SiO2 as high-k gate insulator

In this paper, we compare the electrical characteristics of MOS capacitors and lateral MOSFETs with oxidized Ta₂Si (O-Ta₂Si) as a high-k dielectric on silicon carbide or stacked on thermally grown SiO₂ on SiC. MOS capacitors are used to determine the dielectric and interfacial properties of these insulators. We demonstrate that stacked SiO₂/O-Ta₂Si is an attractive solution for passivation of innovative SiC devices. Ta₂Si deposition and oxidation is totally compatible with standard SiC MOSFET fabrication materials and processing. We demonstrate correct transistor operation for stacked O-Ta₂Si on thin thermally grown SiO₂ oxides. However the channel mobility of such high-k MOSFETs must be improved investigating the interface properties further.     

Organic thin-film field-effect transistors with MoO3/Al electrode and OTS/SiO2 bilayer gate insulator

An organic thin-film transistor (OTFTs) having OTS/SiO₂ bilayer gate insulator and MoO₃/Al electrode configuration between gate insulator and source–drain (S–D) electrodes has been investigated. Thermally grown SiO₂ layer is used as the OTFT gate dielectric and copper phthalocyanine (CuPc) for an active layer. We have found that using silane coupling agents, octadecyltrichlorosilane (OTS) on SiO₂, surface energy of SiO₂ gate dielectric is reduced; consequently, the device performance has been improved significantly. This OTS/SiO₂ bilayer gate insulator configuration increases the field-effect mobility, reduces the threshold voltage and improves the on/off ratios simultaneously. The device with MoO₃/Al electrode has similar source–drain current (I_DS) compared to the device with Au electrode at same gate voltage. Our results indicate that using double-layer of insulator and modified electrode is an effective way to improve OTFT performance.     

Investigation on the passivation,band alignment,gate charge,and mobility degradation of the Ge MOSFET with a GeOx/Al2O3 gate stack by ozone oxidation

Ge has been an alternative channel material for the performance enhancement of complementary metal–oxide–semiconductor (CMOS) technology applications because of its high carrier mobility and superior compatibility with Si CMOS technology. The gate structure plays a key role on the electrical property. In this paper, the property of Ge MOSFET with Al₂O₃/GeO_x/Ge stack by ozone oxidation is reviewed. The GeO_x passivation mechanism by ozone oxidation and band alignment of Al₂O₃/GeO_x/Ge stack is described. In addition, the charge distribution in the gate stack and remote Coulomb scattering on carrier mobility is also presented. The surface passivation is mainly attributed to the high oxidation state of Ge. The energy band alignment is well explained by the gap state theory. The charge distribution is quantitatively characterized and it is found that the gate charges make a great degradation on carrier mobility. These investigations help to provide an impressive understanding and a possible instructive method to improve the performance of Ge devices.

     

Interface state densities, low frequency noise and electron mobility in surface channel In0.53Ga0.47As n-MOSFETs with a ZrO2 gate dielectric

This paper reports on an investigation of interface state densities, low frequency noise and electron mobility in surface channel In_0.53Ga_0.47As n-MOSFETs with a ZrO₂ gate dielectric. Interface state density values of D_it ∼ 5 × 10¹² cm⁻² eV⁻¹ were extracted using sub-threshold slope analysis and charge pumping technique. The same order of magnitude of trap density was found from low frequency noise measurements. A peak effective electron mobility of 1200 cm²/Vs has been achieved. For these surface channel In_0.53Ga_0.47As n-MOSFETs, it was found that η parameter, an empirical parameter used to calculate the effective electric field, was ∼0.55, and is to be comparable to the standard value found in Si device.