High mobility compressive strained Si0.5Ge0.5 quantum well p-MOSFETs with higher-k/metal-gate

Strained SiGe quantum well p-MOSFETs with LaLuO₃ higher-k dielectric were fabricated and characterized. The strained Si/strained Si_0.5Ge_0.5/strained SOI heterostructure transistors showed good output and transfer characteristics with an I_on/I_off ratio of 10⁵. The extracted hole mobility shows an enhancement of about 2.5 times over Si universal hole mobility and no degradation compared to HfO₂ or even SiO₂ gate dielectric devices.     

Improved self-gain in deep submicrometer strained silicon-germanium pMOSFETs with HfSiOx/TiSiN gate stacks

The self-gain of surface channel compressively strained SiGe pMOSFETs with HfSiO_x/TiSiN gate stacks is investigated for a range of gate lengths down to 55 nm. There is 125% and 700% enhancement in the self-gain of SiGe pMOSFETs compared with the Si control at 100 nm and 55 nm lithographic gate lengths, respectively. This improvement in the self-gain of the SiGe devices is due to 80% hole mobility enhancement compared with the Si control and improved electrostatic integrity in the SiGe devices due to less boron diffusion into the channel. At 55 nm gate length, the SiGe pMOSFETs show 50% less drain induced barrier lowering compared with the Si control devices. Electrical measurements show that the SiGe devices have larger effective channel lengths. It is shown that the enhancement in the self-gain of the SiGe devices compared with the Si control increases as the gate length is reduced thereby making SiGe pMOSFETs with HfSiO_x/TiSiN gate stacks an excellent candidate for analog/mixed-signal applications.     

Investigation of Coulomb scattering on sSi/Si0.5Ge0.5/sSOI quantum-well p-MOSFETs

sSi/Si_0.5Ge_0.5/sSOI quantum-well (QW) p-MOSFETs with HfO₂/TiN gate stack were fabricated and characterized. According to the low temperature experimental results, carrier mobility of the strained Si_0.5Ge_0.5 QW p-MOSFET was mainly governed by phonon scattering from 300 to 150 K and Coulomb scattering below 150 K, respectively. Coulomb scattering was intensified by the accumulated inversion charges in the Si cap layer of this Si/SiGe heterostructure, which led to a degradation of carrier mobility in the SiGe channel, especially at low temperature.     

Fully strained Si0.75Ge0.25 epitaxial films with HfSiO gate dielectrics for high mobility channel metal-oxide semiconductor devices

The authors report on fully strained Si_0.75Ge_0.25 metal-oxide-semiconductor capacitors with HfSiO₂ high-k gate dielectric and TaN metal gate fabricated on Si substrates. Fully strained Si_0.75Ge_0.25 films are directly grown on Si substrates below the critical thickness. HfSiO₂ high-k gate dielectrics exhibit an equivalent oxide thickness of 13-18 Å with a permittivity of 17.7 and gate leakage current density lower than SiO₂ gate oxides by >100×. Interfacial oxide of the HfSiO₂/Si_0.75Ge_0.25 stack consists primarily of SiO₂ with a small amount of Ge and Hf. High performance SiGe field effect transistors are highly manufacturable with excellent electrical characteristics afforded by the fully strained HfSiO₂/SiGe gate stack.     

SrO capping effect for La2O3/Ce-silicate gate dielectrics

The chemical bonding states and electrical characteristics of SrO capped La₂O₃/CeO_x gate dielectric have been examined. Angle-resolved X-ray photoelectron spectroscopy measurement has revealed that Sr atoms diffuse into silicate layer to form SrLa-silicate after annealing. Owing to the incorporation of Sr atoms into silicate layer, a transistor operation with an equivalent oxide thickness (EOT) below 0.5 nm has been demonstrated. A strongly degraded effective electron mobility of 78 cm²/V s at 1 MV/cm has been obtained, which fit well with the general trend in small EOT range below 1 nm. Although process optimization is needed to improve the performance of transistors, Sr capping technique can be useful for EOT scaling.     

New opportunities for SiGe and Ge channel p-FETs

A thin body (fully depleted) strained SGOI device structure (FDSGOI), and a strained SiGe channel layer on SOI, were fabricated using scaled high-κ gate dielectrics and metal gate technology. The uniaxial strain effect and corresponding drive current enhancement reported by Irisawa et al. [1] for narrow-width devices was investigated on these structures. Although the strained FDSGOI device structure exhibited reduced off-state leakage compared to thicker body devices, and long-channel drive current enhancement under uniaxial strain, the loss of drive current enhancement at short channel length led to uncompetitive I_ON-I_OFF characteristics. The SiGe on SOI structure showed the highest long-channel drive current enhancement (nearly 3×) in the narrowest devices, and also showed a significant reduction in off-state current. This trend was maintained down to the shortest channel lengths studied here and resulted in I_ON-I_OFF characteristics that were competitive with contemporary uniaxial strained Si channel devices.     

High performance,foldable, organic memories based on ultra-low voltage,thin film transistors

We report on the fabrication of highly flexible OTFT-based memory elements with excellent mechanical stability and high retention time. The devices have been fabricated using a combination of two ultrathin AlOx and Parylene C as dielectric, and TIPS-Pentacene as the semiconductor, obtaining high performing low voltage transistors with mobility up to 0.4 cm²/V s, and I_on/I_off ratio of 10⁵. Charge trapping in the Parylene C electret layer is the mechanism that allows employing these devices as non volatile memory elements, with retention time as high as 4 × 10⁵ s. The electromechanical characterization demonstrated that such memory elements can be cyclically bent around a cylinder with a radius of 150 μm without losing the stored data.     

Interface state densities, low frequency noise and electron mobility in surface channel In0.53Ga0.47As n-MOSFETs with a ZrO2 gate dielectric

This paper reports on an investigation of interface state densities, low frequency noise and electron mobility in surface channel In_0.53Ga_0.47As n-MOSFETs with a ZrO₂ gate dielectric. Interface state density values of D_it ∼ 5 × 10¹² cm⁻² eV⁻¹ were extracted using sub-threshold slope analysis and charge pumping technique. The same order of magnitude of trap density was found from low frequency noise measurements. A peak effective electron mobility of 1200 cm²/Vs has been achieved. For these surface channel In_0.53Ga_0.47As n-MOSFETs, it was found that η parameter, an empirical parameter used to calculate the effective electric field, was ∼0.55, and is to be comparable to the standard value found in Si device.     

Investigation of atomic vapour deposited TiN/HfO2/SiO2 gate stacks for MOSFET devices

HfO₂ films were grown by atomic vapour deposition (AVD) on SiO₂/Si (1 0 0) substrates. The positive shift of the flat band voltage of the HfO₂ based metal-oxide-silicon (MOS) devices indicates the presence of negative fixed charges with a density of 5 × 10¹² cm⁻². The interface trap charge density of HfO₂/SiO₂ stacks can be reduced to 3 × 10¹¹ eV⁻¹ cm⁻² near mid gap, by forming gas annealing. The extracted work function of 4.7 eV preferred the use of TiN as metal gate for PMOS transistors. TiN/HfO₂/SiO₂ gate stacks were integrated into gate-last-formed MOSFET structures. The extracted maximum effective mobility of HfO₂ based PMOS transistors is 56 cm²/Vs.     

High-mobility pentacene thin-film transistor by using LaxTa(1−x)Oy as gate dielectric

Pentacene organic thin-film transistors (OTFTs) using La_xTa_(1−x)O_y as gate dielectric with different La contents (x = 0.227, 0.562, 0.764, 0.883) have been fabricated and compared with those using Ta oxide or La oxide. The OTFT with La_0.764Ta_0.236O_y can achieve a carrier mobility of 1.21 cm² V⁻¹s⁻¹s, which is about 40 times and two times higher than those of the devices using Ta oxide and La oxide, respectively. As supported by XPS, AFM and noise measurement, the reasons lie in that La incorporation can suppress the formation of oxygen vacancies in Ta oxide, and Ta content can alleviate the hygroscopicity of La oxide, resulting in more passivated and smoother dielectric surface and thus larger pentacene grains, which lead to higher carrier mobility.     

Dielectric enhancement in interface-modified BaTiO3/SrTiO3 multilayered films prepared by pulsed laser deposition

Pulsed-laser-deposited polycrystalline BaTiO₃/SrTiO₃ multilayered films on Pt/Ti/SiO₂/Si substrates have been fabricated with interfacial modification through lowering the oxygen pressure during the time interval in between two adjacent depositions. It is found that the formation of the heterolayered structure is essential to get the dielectric enhancement. Such heterolayered films have large dielectric constant of 1201 with a loss tangent below 0.1 at 10 KHz. This is about two times that of the identically prepared Ba_0.5Sr_0.5TiO₃/Ba_0.5Sr_0.5TiO₃ homolayered and uniform Ba_0.5Sr_0.5TiO₃ films. The enhancement of dielectric properties is attributed to the presence of the interfacial regions with controllable space charges due to the formation of oxygen vacancies at lower oxygen pressure.     

Charge trapping and interface characteristics in normally-off Al2O3/GaN-MOSFETs

Normally-off GaN-MOSFETs with Al₂O₃ gate dielectric have been fabricated and characterized. The Al₂O₃ layer is deposited by ALD and annealed under various temperatures. The saturation drain current of 330 mA/mm and the maximum transconductance of 32 mS/mm in the saturation region are not significantly modified after annealing. The subthreshold slope and the low-field mobility value are improved from 642 to 347 mV/dec and from 50 to 55 cm² V⁻¹ s⁻¹, respectively. The I_D-V_G curve shows hysteresis due to oxide trapped charge in the Al₂O₃ before annealing. The amount of hysteresis reduces with the increase of annealing temperature up to 750 °C. The Al₂O₃ layer starts to crystallize at a temperature of 850 °C and its insulating property deteriorates.     

A deep submicron Si1-xGex/Si vertical PMOSFETfabricated by Ge ion implantation

We report a deep submicron vertical PMOS transistor using strained Si_1-xGe_x channel formed by Ge ion implantation and solid phase epitaxy. These vertical structure Si_1-xGe_x /Si transistors can be fabricated with channel lengths below 0.2 μm without using any sophisticated lithographic techniques and with a regular MOS process. The enhancement of hole mobility in a direction normal to the growth plane of strained Si_1-xGe_x over that of bulk Si has been experimentally demonstrated for the first time using this vertical MOSFET. The drain current of these vertical MOS devices has been found to be enhanced by as much as 100% over control Si devices. The presence of the built-in electric field due to a graded SiGe channel has also been found to be effective in further enhancement of the drive current in implanted-channel MOSFET's     

Performance assessment of (1 1 0) p-FET high-κ/MG: is it mobility or series resistance limited?

In this article the impact of Si-substrate orientation on mobility performance is studied for p-MOSFET’s with both HfSiON and SiON based dielectrics. Consistent with previous studies, the I_on at fixed I_off is 100% larger for Si(1 1 0) larger than for standard Si(1 0 0). A thorough analysis of the factors influencing I_on (EOT, mobility and R_series) for short channel devices (until L_met = 80 nm) indicates that a 200% increase of the mobility at high V_g is the source of this performance enhancement. The lower I_on increase (only 100%) compared to what is expected from the mobility is only explained by a larger impact of the R_series (70% of the total resistance) for short channel devices. As a result additional room for I_on improvement can be reached by device and R_series optimization.     

Performance comparison of pentacene organic field-effect transistors with SiO2 modified with octyltrichlorosilane or octadecyltrichlorosilane

Performance of pentacene organic field-effect transistors (OFETs) is significantly improved by treatment of SiO₂ with octyltrichlorosilane (OTS-8) compared to octadecyltrichlorosilane (OTS-18). The average hole mobility in these OFETs is increased from 0.4 to 0.8 cm²/Vs when treating the dielectric with OTS-8 versus OTS-18 treated devices. The atomic force microscope (AFM) images show that the OTS-8 treated surface produces much larger grains of pentacene (∼500 nm) compared to OTS-18 (∼100 nm). X-ray diffraction (XRD) results confirmed that the pentacene on OTS-8 is more crystalline compared to the pentacene on OTS-18, resulting in higher hole mobility.     

Interfacial transition regions at germanium/Hf oxide based dielectric interfaces: Qualitative differences between non-crystalline Hf Si oxynitride and nanocrystalline HfO2 gate stacks

The contribution from a relatively low-K SiON (K ∼ 6) interfacial transition region (ITR) between Si and transition metal high-K gate dielectrics such as nanocrystalline HfO₂ (K ∼ 20), and non-crystalline Hf Si oxynitride (K ∼ 10-12) places a significant limitation on equivalent oxide thickness (EOT) scaling. This limitation is equally significant for metal-oxide-semiconductor capacitors and field effect transistors, MOSCAPs and MOSFETs, respectively, fabricated on Ge substrates. This article uses a novel remote plasma processing approach to remove native Ge ITRs and bond transition metal gate dielectrics directly onto crystalline Ge substrates. Proceeding in this way we identify (i) the source of significant electron trapping at interfaces between Ge and Ge native oxide, nitride and oxynitride ITRs, and (ii) a methodology for eliminating native oxide, or nitride IRTs on Ge, and achieving direct contact between nanocrystalline HfO₂ and non-crystalline high Si₃N₄ content Hf Si oxynitride alloys, and crystalline Ge substrates. We then combine spectroscopic studies, theory and modeling with electrical measurements to demonstrate the relative performance of qualitatively different nanocrystalline and non-crystalline gate dielectrics for MOS Ge test devices.     

Highly (1 0 0)-oriented Pb(Zr0.20Ti0.80)O3/(Pb1−xLax)Ti1−x/4O3 multilayered thin films prepared by RF magnetron sputtering

The Pb(Zr_0.20Ti_0.80)O₃/(Pb_1−xLa_x)Ti_1−x/4O₃ (x = 0, 0.10, 0.15, 0.20) (PZT/PLT_x) multilayered thin films were in situ deposited on the Pt(1 1 1)/Ti/SiO₂/Si(1 0 0) substrates by RF magnetron sputtering technique with a PbO_x buffer layer. With this method, all PZT/PLT_x multilayered thin films possess highly (1 0 0) orientation. The PbO_x buffer layer leads to the (1 0 0) orientation of the multilayered thin films. The effect of the La content in PLT_x layers on the dielectric and ferroelectric properties of the PZT multilayered thin films was systematically investigated. The enhanced dielectric and ferroelectric properties are observed in the PZT/PLT_x (x = 0.15) multilayered thin films. The dielectric constant reaches maximum value of 365 at 1 KHz for x = 0.15 with a low loss tangent of 0.0301. Along with enhanced dielectric properties, the multilayered thin films also exhibit large remnant polarization value of 2P_r = 76.5 μC/cm², and low coercive field of 2E_c = 238 KV/cm.     

Downscaling of n-channel organic field-effect transistors with inkjet-printed electrodes

In this contribution we demonstrate for the first time a downscaled n-channel organic field-effect transistors based on N,N′-dialkylsubstituted-(1,7&1,6)-dicyanoperylene-3,4:9,10-bis(dicarboximide) with inkjet printed electrodes. First we demonstrate that the use of a high boiling point solvent is critical to achieve extended crystalline domains in spin-coated thin films and thus high electron mobility >0.1 cm² V⁻¹ s⁻¹ in top-gate devices. Then inkjet-printing is employed to realize sub-micrometer scale channels by dewetting of silver nanoparticles off a first patterned gold contact. By employing a 50 nm crosslinked fluoropolymer gate dielectric, ∼200 nm long channel transistors can achieve good current saturation when operated <5 V with good bias stress stability.     

Characterization of ultra-thin SiO2 by capacitance-voltage and charge pumping measurements

In this paper, we present results on electrical measurements of ultra thin SiO₂ layers (from 3.5 nm down to 1.7 nm), used as gate dielectric in metal-oxide-semiconductors (MOS) devices. Capacitance-voltage (C-V) measurements and simulations on MOS capacitors have been used for extracting the electrical oxide thickness. The SiO₂/Si interface and oxide quality have been analyzed by charge pumping (CP) measurements. The mean interface traps density is measured by 2-level CP, and the energy distribution within the semiconductor bandgap of these traps are investigated by 3-level charge pumping measurements. A comparison of the energy distribution of the SiO₂/Si interface traps is made using classical and quantum simulations to extract the surface potential as a function of the gate signal. When the gate oxide thickness <3.5 nm, we prove that it is mandatory to take into account the quantum effects to obtain a more accurate energy distribution of the SiO₂/Si interface traps. We also explain the increase of the apparent interface traps density measured by 2-levels CP with the increase of the oxide thickness, for transistors made from the same technological process.     

Carrier mobility in inversion layers of Si–thin Ta2O5 structures

The behaviour of carrier mobility in the inversion channel of gateless p-MOSFETs with thin (7-50 nm) Ta₂O₅ layers, having a dielectric constant of (23-27) and prepared by rf sputtering of Ta in an Ar-O₂ mixture, has been investigated. It is shown that independently of the high dielectric constant of the layers, the transport properties in the channel are strongly affected by defects in Ta₂O₅/Si system in the form of oxide charge and interface states. These defects act as scattering centers and are responsible for the observed minority carrier mobility degradation. Both, the oxide and the interface state charges are virtually independent on the oxygen content (in the range 10-30%) during the sputtering process. A reduction of the oxide charge and the density of interface states with increasing Ta₂O₅ film thickness was found, which results in the observed increase of the inversion channel mobility with thickness. It is assumed that the bond defects (broken or strained Ta-bonds as well as weak Si-O bonds in the transition region between Ta₂O₅ and Si) are much more probable sources of defect centers rather than Ta and O vacancies or impurities.