Physics of direct bonding: Applications to 3D heterogeneous or monolithic integration

Direct wafer bonding and thinning technologies are now extensively used in combination to produce SOI wafers (silicon-on-insulators) or innovative engineered substrates. Emerging demands of new functionalities at the material or device level for 3D integration have allowed increasing the level of maturity of these technologies. This paper will review the physics of wafer direct bonding and its implementation for vertical integration devices of processed strata with vertical interconnects.     

三维一体化超微定位系统的研制

本文设计并研制了以柔性铰链为弹性导轨、压电陶瓷为驱动器的三维一体化超微定位机构,并以激光干涉仪微位移检测装置和微机控制系统构成了数字闭环控制的三维一体化超微定位系统。     

3D Perception Algorithms:Towards Perceptually Driven Compression of 3D Video

In this paper, we summarize 3D perception-oriented algorithms for perceptually driven 3D video coding. Several perceptual effects have been exploited for 2D video viewing; however, this is not yet the case for 3D video viewing. 3D video requires depth perception, which implies binocular effects such as conflicts, fusion, and rivalry. A better understanding of these effects is necessary for 3D perceptual compression, which provides users with a more comfortable visual experience for video that is delivered over a channel with limited bandwidth. We present state-of-the-art of 3D visual attention models, 3D just-noticeable difference models, and 3D texture-synthesis models that address 3D human vision issues in 3D video coding and transmission.     

Quality factor and frequency bandwidth of 2D self-inductors in 3D integration stacks

Effects due to 3D level stack on high frequency (HF) properties of 2D self-inductors integrated in the back end of line (BEOL) are investigated. Different stacking processes as Back to Face and Face to Face using a molecular SiO₂ bonding or a copper direct bonding are studied in order to determine silicon substrate stack influence on quality factor and frequency bandwidth of 2D self-inductors. Face to Face process with a molecular SiO₂ bonding allows improvements of self-inductor performances, better than Back to Face process with a molecular SiO₂ bonding and better than Face to Face process using a copper direct bonding.     

High aspect ratio copper through-silicon-vias for 3D integration

Three-dimensional (3D) integration, which uses through-silicon-vias (TSVs) to interconnect multiple layers of active circuits, offers significant improvements over planar integrated circuits (ICs) on performance, functionality, and integration density. To address a key issue in 3D integration, the fabrication of high aspect ratio TSVs, this paper presents the bottom-up copper electroplating technique to fill high aspect ratio vias with copper. Deep through-silicon holes with aspect ratio as high as 10:1 are etched using deep reactive ion etching (DRIE) method, and are completely filled with copper using bottom-up copper electroplating technique without forming any voids or seams. Based on this technique, a multi-layer 3D integration method is proposed. This method uses temporary transfer wafer to provide mechanical support to the device wafer during wafer thinning process and to provide the seed layer for copper electroplating. Then bottom-up electroplating is performed to fill the high aspect ratio vias with copper. Experimental results verify the feasibility of the proposed method.     

Advanced methods for mechanical and structural characterization of nanoscale materials for 3D IC integration

Managing the emerging internal mechanical stress in chips, particularly if they are 3D stacked, is a key task to maintain performance and reliability of microelectronic products. Hence, a strong need of a physics-based simulation methodology emerges. This physics-based simulation, however, requires material parameters with high accuracy. A full-chip analysis can then be performed, balancing the need for local resolution and computing time. The key for an efficient simulation of a 3D stacked IC is a comprehensive database with material properties for multiple scales of the affected materials. Therefore, effective “composite-type” material data for several regions of interest are needed. Advanced techniques to measure FEA- and design-relevant properties such as adhesion properties and effective CTE values are presented.     

Experimental characterization of coaxial through silicon vias for 3D integration

Coaxial through silicon via (TSV) technology is gaining considerable interest as a 3D packaging solution due to its superior performance compared to the current existing TSV technology. By confining signal propagation within the coaxial TSV shield, signal attenuation from the lossy silicon substrate is eliminated, and unintentional signal coupling is avoided. In this paper, we propose and demonstrate a coaxial TSV 3D fabrication process. Next, the fabricated coaxial TSVs are characterized using s-parameters for high frequency analysis. The s-parameter data indicates the coaxial TSVs confine electromagnetic propagation by extracting the inductance and capacitance of the device. Lastly, we demonstrate the coaxial TSVs reduce signal attenuation and time delay by 35% and 25% respectively compared to the shield-less standard TSV technology. In addition, the coaxial interconnect significantly decreases electromagnetic coupling compared to traditional TSV architectures. The improved signal attenuation and high isolation of the coaxial TSV make it an excellent option for 3D packaging applications expanding into the millimeter wave regime.     

3D电视的原理及电路解析

2009年12月,随着阿凡达的大热,消费者对3D的狂热在国际上掀起一轮3D热潮。在3D电影的促动下,3D市场已于2010年开始起飞。而且随着全球消费电子厂商陆续推出一批包括电视机、监视器、笔记本电脑、蓝光盘播放器、数码相机、摄像机、电子相框等3D相关产品进军家庭市场。据DisplaySearch的市场调研数据显示,2010年3D电视全球出货量达到420万台。2011年全球3D电视货量达2 340万台,2014年预计将出货达9 000万台。中国的3D电视产业发展备受业内外人士关注,我国不仅是全球最大的平板电视市场,更是全球最大的彩电制造基地。从平板电视到互联网电视再到3D电视,每一次技术升级,国内彩电企业总是紧跟而上。2010年3月,TCL、创维等企业开始推出3D电视;随后在9月份,海信推出了融合网络多媒体技术、3D显示技术的LED背光电视;康佳一举推出4大系列、20多款智能3D电视。文中主要阐述3D电视的原理及技术分类,并以康佳988系列3D电视为例,解析3D部分电路。     

面向CMOS图像传感器芯片的3D 芯粒(Chiplet) 非接触互联技术

在后摩尔时代,3D芯粒(Chiplet)通常利用硅通孔(TSV)进行异构集成,其复杂的工艺流程会提高芯片制造的难度和成本。针对背照式(BSI)CMOS图像传感器(CIS)的倒置封装结构,该文提出了一种低成本、低工艺复杂度的3D Chiplet非接触互联技术,利用电感耦合构建了数据源、载波源和接收机3层分布式收发机结构。基于华润上华(CSMC)0.25 μm CMOS工艺和东部高科(DB HiTek)0.11 μm CIS工艺,通过仿真和流片测试验证了所提出的互联技术的有效性。测试结果表明,该3D Chiplet非接触互联链路采用20 GHz载波频率,收发机通信距离为5～20 μm,在数据速率达到200 Mbit/s时,误码率小于10^–8,接收端功耗为1.09 mW,能效为5.45 pJ/bit。     

Flash Papervision3D中3D Web应用程序设计

为了能将日益应用广泛的Papervision3D、能在Flash Player中播放的目的,采用较为新颖的3D引擎方法,做了三维到二维的转换、Flint粒子系统实验,实现了平滑拉近物体从远处拉近及喷泉的效果.通用开源Flash 3D渲染引擎中Papervision3D是基于ActionScript的开源项目,而Flash在3D领域的应用相对贫乏,在Flash Player中播放,则具备体积小、与用户交互能力强、效果逼真的3D Web应用程序特点.     

Integration challenges of copper Through Silicon Via (TSV) metallization for 3D-stacked IC integration

In this paper we will highlight key integration issues that were encountered during the development of the 3D-stacked IC Through Silicon Via (TSV) module and present solutions to achieve a robust copper TSV. Electrical performance of the obtained TSV module is discussed based on a lumped RC model for 3D ring oscillators containing TSVs between bottom and top tiers.     

基于BGA互联的毫米波模块三维集成设计

设计了一种利用微波基板作为转接板的毫米波系统级封装（System in Package,SIP）模块。采用球栅阵列(Ball Grid Array,BGA)作为射频信号层间垂直互联传输和隔离结构,实现了三维集成毫米波模块的低损耗垂直传输。对样件测试结果显示,在28~31 GHz频率范围之间,其端口驻波小于1.5,增益大于30 dB。该三维集成结构简单,射频传输性能良好,其体积仅为传统二维平面封装结构的20%,实现了模块的小型化,可广泛用于微波和毫米波电路与系统。     

Smooth, 3D Ge transistor channels by heteroepitaxial growth

Crystalline germanium (Ge) is a prime candidate as a material for high-performance transistors due to its higher electron and hole mobility with respect to those of silicon. In this study, we present a novel method of fabricating epitaxial Ge structures of high crystalline and morphological quality directly onto Si substrates, in which 3D Ge structures are grown by selective epitaxy then annealed in a hydrogen ambient at 850 °C. Under such annealing, the surface of the Ge structures deform by surface diffusion to form smooth, rounded shapes for which the surface energy is at a local minima. The apparent smoothness of the surface, along with the decreased defect density expected to exist in these heteroepitaxial Ge structures, suggest they are adequate for use as transistor channels.     

Ultra-Flexible Monolithic 3D Complementary Metal-Oxide-Semiconductor Electronics

Flexible electronics based on complementary metal-oxide-semiconductor (CMOS) technology have enabled a smart soft world. However, the trade-off among flexibility, density, and electrical performance has been a long-lasting unresolved issue. Here, a monolithic three-dimensional (M3D) CMOS design is proposed to address this problem and realize ultra-flexible electronics with high electronic-performance and integration. This design utilizes vertically stacked p-type carbon nanotube transistors and n-type indium gallium zinc oxide ones, which share common gates and drains, saving the inter tier vias required in the traditional M3D structure to reduce routing and improve flexibility. With this design, CMOS logic gates, multi-stage circuits, ring oscillators (ROs) and memory modules, are demonstrated. This design enables circuits to save up to 45% of area compared with their planar counterparts. Particularly, inverters exhibit a record-high gain of 191, and 55-stage ROs can operate well even after bending at a 500-µm radius for 50 cycles, exhibiting the highest flexibility among the reported ones. The ultra-flexible and high-integration RO enables a wearable light recorder to collect harmful blue light shining into human eyes by simply attaching the circuits on a contact lens. This integration method provides possibilities for developing complex-function wearable electronics.     

Java3D在网络三维游戏设计中的应用探讨

随着网络技术、虚拟现实技术的迅猛发展、人们生活娱乐水平的提高,近几年三维网络游戏成为热门焦点.现介绍了三维网络游戏的发展现状,选择Java3D的优点并举例说明,也简要说明了它的一些不足之处.     

3D真的来了吗?——三维结构光传感器漫谈

三维成像与传感技术作为感知真实三维世界的重要信息获取手段,为重构物体真实几何形貌及后续的三维建模、检测、识别等方面提供了数据基础。近年来,计算机视觉和光电成像技术的发展以及消费电子与个人身份验证对3D传感技术日益增长的需求促进了三维成像与传感技术的蓬勃式发展。2D摄像头向3D传感器的转变也将成为继黑白到彩色、低分辨率到高分辨率、静态图像到动态影像后的"第四次影像革命"。《红外与激光工程》本期策划组织的"光学三维成像与传感"专题,共包含高水平稿件20篇,其中综述论文15篇,研究论文5篇。这些论文系统介绍了光学三维成像传感领域热点专题的研究进展与最新动态,主题全面涵盖了当前三维光学成像领域的前沿研究方向:结构光三维成像、条纹投影轮廓术、干涉测量技术、相位测量偏折术、三维立体显示技术(全息显示、集成光场显示等)、三维成像传感技术与计算成像相关交叉领域(如三维鬼成像)等。而此文作为本期专栏的引子,概括性地综述了典型的三维传感技术,并着重介绍了三维结构光传感器技术的发展现状、关键技术、典型应用;讨论了其现存问题、并展望了其未来发展方向,以求抛砖引玉。     

一种基于硅基MEMS三维异构集成技术的T/R组件

基于硅基微电子机械系统(MEMS)三维异构集成工艺,设计并制作了用于相控阵天线系统的三维堆叠式Ku波段双通道T/R组件。该组件由两层硅基结构通过球栅阵列(BGA)植球堆叠而成,上下两层硅基封装均采用5层硅片通过硅通孔(TSV)、晶圆级键合工艺实现。组件集成了六位数控移相、六位数控衰减、串转并、电源调制、逻辑控制等功能,最终组件尺寸仅为15 mm×8 mm×3.8 mm。测试结果表明,在Ku波段内,该组件发射通道饱和输出功率大于24 dBm,单通道发射增益大于20 dB,接收通道增益大于20 dB,噪声系数小于3.0 dB。该组件性能好,质量轻,体积小,加工精确度高,组装效率高。     

基于DMD的真三维显示系统及其三维成像引擎设计

结合在体元式三维显示(Volumetric 3D display)中比较有代表性的3种显示系统,在说明了体元式真三维显示系统的实现思路和方法的基础上,从应用的角度解析以DMD为核心构成的三维成像引擎在体元式真三维显示系统中的应用,并给出3种基于DMD的三维成像引擎架构,能够在不同层次上很好地满足真三维显示对海量数据实时、高速、精确处理的要求。     

基于Java3D的三维模型交互设计系统的开发与应用

首先概括地介绍了Java3D技术在三维模型交互设计的应用.提出了采用Java3D用于虚拟三维模型的描述,通过远端客户机读取服务端客户上传的三维图形数据,实现与用户交互的虚拟三维交互建模方案,使用程序提供的绘图工具对图形进行编辑并将结果保存到服务端相应的文件,通过对服务器端文件的读写操作来实现用户之间的信息交互,共享数字化的设计信息,使Internet成为设计工作的主要协作平台.     

Edge effect aware low-power crosstalk avoidance technique for 3D integration

Metal wires and through silicon vias (TSVs) are frequently performance bottlenecks of 3D ICs due to their high capacitive crosstalk which can be reduced using coding techniques. In this work we show that existing TSV crosstalk avoidance codes (CACs) are impractical for real applications due to the edge effects in TSV bundles. Additionally, these 3D CACs do not reduce the metal wire crosstalk and dramatically increase the power consumption of 2D and 3D interconnects. This work presents a 3D CAC which overcomes previous limitations. The method is based on an intelligent fixed mapping of the bits of existing 2D CACs onto rectangular or hexagonal TSV arrangements. Simulation results, obtained by circuit simulations in combination with an electromagnetic field solver, show that existing 3D CACs only reduce the TSV crosstalk by a maximum of 9.4%, provide no optimization of the metal wire crosstalk and induce an increase in the interconnect power consumption by about 50%. In contrast, the presented technique requires less hardware and reduces the maximum crosstalk of modern TSV and metal wire buses by 37.8% and 47.6%, respectively, while leaving their power consumption almost unaffected. Alternatively, our technique can reduce the TSV and metal wire crosstalk peaks by 20.3% and 47.7%, respectively, while additionally providing a reduction in the TSV and metal wire power consumption by 5.3% and 21.9%, respectively.