Studies of Ti- and Ni-germanide Schottky contacts on n-Ge(1 0 0) substrates

In this study, we investigated fabrication and characteristics of germanides Schottky contacts on germanium. Ti- and Ni-germanides were fabricated on n-Ge(1 0 0) substrates by sputtering metal Ti or Ni on Ge followed by a furnace annealing. The influence of annealing temperature on the electrical properties of Ti- and Ni-germanide on n-Ge(1 0 0) substrates was investigated. The low temperature ∼300 °C annealing helped to obtain the optimized Schottky contact characteristics in both Ti-germanide/Ge and Ni-germanide/Ge substrates contacts. The well-behaved Ti-germanides/n-Ge Schottky contact with 0.34 eV barrier height was obtained by using a 300 °C annealing process.     

Yttrium silicide formation and its contact properties on Si(1 0 0)

Yttrium silicide formation and its contact properties on Si(1 0 0) have been studied in this paper. By evaporating a yttrium metal layer onto Si(1 0 0) wafer in conventional vacuum condition and rapid thermal annealing, we found that YSi_2-x begins to form at 350 °C, and is stable to 950 °C. Atomic force microscopy characterization shows the pinholes formation in the formed YSi_2-x film. By current-voltage measurement, the Schottky barrier height (SBH) of YSi_2-x diode on p-type Si(1 0 0) was shown to be between 0.63 and 0.69 eV for annealing temperature from 500 to 900 °C. By low temperature current-voltage measurement, the SBH of YSi_2-x diode on n-type Si(1 0 0) was directly measured and shown to be 0.46, 0.37, 0.32 eV for annealing temperature of 500, 600, and 900 °C, respectively, and possibly even lower for annealing at 700 or 800 °C.     

Solid phase epitaxial growth of Dy-germanide films on Ge(0 0 1) substrates

Dy thin films are grown on Ge(0 0 1) substrates by molecular beam deposition at room temperature. Subsequently, the Dy film is annealed at different temperatures for the growth of a Dy-germanide film. Structural, morphological and electrical properties of the Dy-germanide film are investigated by in situ reflection high-energy electron diffraction, and ex situ X-ray diffraction, atomic force microscopy and resistivity measurements. Reflection high-energy electron diffraction patterns and X-ray diffraction spectra show that the room temperature growth of the Dy film is disordered and there is a transition at a temperature of 300-330 °C from a disordered to an epitaxial growth of a Dy-germanide film by solid phase epitaxy. The high quality Dy₃Ge₅ film crystalline structure is formed and identified as an orthorhombic phase with smooth surface in the annealing temperature range of 330-550 °C. But at a temperature of 600 °C, the smooth surface of the Dy₃Ge₅ film changes to a rough surface with a lot of pits due to the reactions further.     

An efficient wet-cleaning of SiGe virtual substrates and of thick, pure Ge layers on Si(0 0 1) after a chemical mechanical planarization step

The aim of this study is to propose an efficient wet cleaning of the surfaces of the SiGe virtual substrates just after a chemical mechanical polishing step. We have first of all studied the chemical compatibility of miscellaneous solutions, such as the standard cleaning 1 (SC1), the Standard Cleaning 2 (SC2), the CARO one etc with SiGe. A definite, logarithmic-like increase of the etch rate with the Ge content has been obtained for the SC1, the SC2 and the CARO solutions (with values 1000-10,000 those of Si evidenced for pure Ge), making them unsuitable for Ge contents above 30%. We have thus investigated the efficiency of new cleaning sequences (named “DDC-SiGe” for SiGe and “HF/O₃” for pure Ge) that call upon diluted HF and ozone solutions spiked with HCl, on SiGe and pure Ge. The overall material consumption of those cleaning sequences, which increases from 10 Å for pure Si up to 130 Å for pure Ge, is quite low. The particle removal efficiency of such cleanings is around 99% for Si_0.8Ge_0.2 and Si_0.7Ge_0.3. It drops down to 83% for Si_0.5Ge_0.5 and to 65% for pure Ge. This is most probably due to pre-existing epitaxy defects which are revealed during the wet cleaning then wrongly assimilated to particles by our surface inspection tool. The metallic contaminants present on the surface after the use of our wet cleaning sequences have a surface density lower than 10¹⁰ atoms cm⁻², this whatever the Ge content of the underlying layer.     

Experimental and theoretical investigation of defects at (1 0 0) Si1−xGex/oxide interfaces

The identification of a nontrigonal Ge dangling bond at SiO₂/Si_1−xGe_x/SiO₂ heterostructures and its electrical activity are discussed, both from experimental and theoretical points of view. This dangling bond is observed from multifrequency electron-spin resonance experiments performed at 4.2 K, for typical Ge concentrations in the range 0.4 ≤ x ≤ 0.85. The electrical activity of this defect is revealed from capacitance-voltage characteristics measured at 300 and 77 K, and is found to behave like an acceptor defect. First-principles calculations of the electronic properties of this Ge dangling bond indicate that its energy level approaches the valence band edge of the Si_1−xGe_x layer as the Ge content increases, confirming its acceptor-like nature.     

Epitaxial growth of Dy2O3 thin films on epitaxial Dy-germanide films on Ge(0 0 1) substrates

Ultra-thin films of Dy are grown on Ge(0 0 1) substrates by molecular beam deposition near room temperature and immediately annealed for solid phase epitaxy at higher temperatures, leading to the formation of DyGe_x films. Thin films of Dy₂O₃ are grown on the DyGe_x film on Ge(0 0 1) substrates by molecular beam epitaxy. Streaky reflection high energy electron diffraction (RHEED) patterns reveal that epitaxial DyGe_x films grow on Ge(0 0 1) substrates with flat surfaces. X-ray diffraction (XRD) spectrum suggests the growth of an orthorhombic phase of DyGe_x films with (0 0 1) orientations. After the growth of Dy₂O₃ films, there is a change in RHEED patterns to spotty features, revealing the growth of 3D crystalline islands. XRD spectrum shows the presence of a cubic phase with (1 0 0) and (1 1 1) orientations. Atomic force microscopy image shows that the surface morphology of Dy₂O₃ films is smooth with a root mean square roughness of 10 Å.     

Epitaxial growth of Fe/MgO/Ge(0 0 1) heterostructures

We report on the growth of epitaxial Fe/MgO heterostructures on Ge(0 0 1) by Molecular Beam Epitaxy. The better crystal quality and interfacial chemical sharpness at the oxide-semiconductor interface have been obtained by growing MgO at room temperature, followed by a post-annealing at 773 K, on top of a p(2 × 1)-Ge(0 0 1) clean surface. The growth of Fe at room temperature followed by annealing at 473 K gives the best epitaxial structure with optimized crystallinity of each layer compatible with limited chemical interdiffusion. Tunneling devices based on the epitaxial Fe/MgO/Ge heterostructure have been micro-fabricated and tested in order to probe the electrical properties of the MgO barrier. The current-voltage characteristics clearly show that tunneling is the dominant phenomenon, thus indicating that this system is very promising for practical applications in electronics and spintronics.     

High spatial and energy resolution characterization of lateral inhomogeneous Schottky barriers by conductive atomic force microscopy

We present a novel approach based on conductive atomic force microscope (c-AFM) for nano-scale mapping in laterally inhomogeneous metal-semiconductors Schottky contacts. For ultra-thin (1-5 nm) metal films with resistivity exceeding by about two orders of magnitude the bulk value, the current localization under the tip (10-20 nm diameter) occurs. By spectroscopic analysis of the current-voltage characteristics for different tip positions, the 2D Schottky barrier height (SBH) distribution is obtained with ∼0.1 eV energy resolution. The method was applied to explain the experimentally observed SBH lowering in macroscopic Au/4H-SiC diodes, in the presence of a not uniform SiO₂ layer at the SiC/Au interface. Nano-scale mapping on the oxide free Au/4H-SiC contact demonstrates a SBH distribution peaked at 1.8 eV and with tails from 1.6 eV to 2.1 eV. When ∼2 nm not uniform SiO₂ layer is intentionally grown on SiC before contact formation, the Au/SiO₂/4H-SiC SBH distribution exhibits a 0.3 eV lowering in the peak and a broadening (tails from 1.1 eV to 2.1 eV), thus explaining the macroscopically observed average effect.     

PAMBE growth of (1 1 2¯ 2)-oriented GaN/AlN nanostructures on m-sapphire

We report on the plasma-assisted molecular-beam epitaxial growth of (1 1 2¯ 2)-oriented GaN/AlN nanostructures on (1 1¯ 0 0) m-plane sapphire. Moderate N-rich conditions enable to synthesize AlN(1 1  2) directly on m-sapphire, with in-plane epitaxial relationships [1 1 2¯ 3¯]_AlN∥[0 0 0 1]_sapphire and [1  0 0]_AlN∥[1 1 2¯ 0]_sapphire. In the case of GaN, a Ga-excess of one monolayer is necessary to achieve two-dimensional growth of GaN(1 1 2¯ 2). Applying these growth conditions, we demonstrate the synthesis of (1 1 2¯ 2)-oriented GaN/AlN quantum well structures, showing a strong reduction of the internal electric field. By interrupting the growth under vacuum after the deposition of few monolayers of GaN under slightly Ga-rich conditions, we also demonstrate the feasibility of quantum dot structures with this orientation.     

Growth and structural properties of crystalline LaAlO3 on Si (0 0 1)

Crystalline LaAlO₃ was grown by oxide molecular beam epitaxy (MBE) on Si (0 0 1) surfaces utilizing a 2 ML SrTiO₃ buffer layer. This SrTiO₃ buffer layer, also grown by oxide MBE, formed an abrupt interface with the silicon. No SiO₂ layer was detectable at the oxide-silicon interface when studied by cross-sectional transmission electron microscopy. The crystalline quality of the LaAlO₃ was assessed during and after growth by reflection high energy electron diffraction, indicating epitaxial growth with the LaAlO₃ unit cell rotated 45° relative to the silicon unit cell. X-ray diffraction indicates a (0 0 1) oriented single-crystalline LaAlO₃ film with a rocking curve of 0.15° and no secondary phases. The use of SrTiO₃ buffer layers on silicon allows perovskite oxides which otherwise would be incompatible with silicon to be integrated onto a silicon platform.     

High quality relaxed Ge layers grown directly on a Si(0 0 1) substrate

After a long period of developing integrated circuit technology through simple scaling of silicon devices, the semiconductor industry is now embracing technology boosters such as strain for higher mobility channel material. Germanium is the logical supplement to enhance existing technologies, as its material behaviour is very close to silicon, and to create new functional devices that cannot be fabricated from silicon alone (Hartmann et al. (2004) [1]). Germanium wafers are, however, both expensive and less durable than their silicon counterparts. Hence it is highly desirable to create a relaxed high quality Ge layer on a Si substrate, with the provision that this does not unduly compromise the planarity of the system. The two temperature method, proposed by Colace et al. (1997) [2], can give smooth (RMS surface roughness below 1 nm) and low threading dislocation density (TDD <10⁸ cm⁻²) Ge layers directly on a Si(0 0 1) wafer (Halbwax et al. (2005) [3]), but these are currently of the order of 1-2 μm thick (Hartmann et al. (2009) [4]).We present an in depth study of two temperature Ge layers, grown by reduced pressure chemical vapour deposition (RP-CVD), in an effort to reduce the thickness. We report the effect of changing the thickness, of both the low temperature (LT) and the high temperature (HT) layers, emphasising the variation of TDD, surface morphology and relaxation.Within this study, the LT Ge layer is deposited directly on a Si(0 0 1) substrate at a low temperature of 400 °C. This low temperature is known to generate monolayer islands (Park et al. (2006) [5]), but is sufficiently high to maintain crystallinity whilst keeping the epitaxial surface as smooth as possible by suppressing further island growth and proceeding in a Frank-van der Merwe growth mode. This LT growth also generates a vast number of dislocations, of the order of 10⁸-10⁹ cm⁻², that enable the next HT step to relax the maximum amount of strain possible. The effect of varying the HT layer thickness is studied by depositing on a LT layer of fixed thickness (100 nm) at a higher growth temperature of 670 °C. We find that the HT layer allows Ge-on-Ge adatom transport to minimise the surface energy and smooth the layer. The final step to the technique is annealing at a high temperature that allows the dislocations generated to glide, increasing the degree of relaxation, and annihilate. We find that annealing can reduce the TDD to the order of 10⁷ cm⁻², but at a cost of a significantly roughened surface.     

AP-MOVPE of InGaAs on GaAs (0 0 1): Analysis of in situ reflectivity response

We have investigated in situ monitoring of growth rate and refractive index by laser reflectometry during InGaAs on GaAs (0 0 1) substrate growth in atmospheric pressure metalorganic vapour-phase epitaxy (AP-MOVPE). The indium solid composition (x_In^s) was varied by changing the substrate temperature or the indium vapour composition (x_In^v). The refractive index of InGaAs alloys as a function of temperature and composition was quantified and compared which that of GaAs for 632.8 nm wavelength by simulation of experimental reflectivity responses. Composition analyses were carried out by high-resolution X-ray diffraction (HRXRD) and optical absorption (OA). The layers thicknesses were estimated by scanning electron microscopy (SEM) observations. The temperature dependence of InGaAs growth rate has been investigated in the temperature range 420-680 °C using trimethylgallium (TMGa), trimethylindium (TMIn) and arsine (AsH₃) sources. It shows Arrhenius-type behaviour with an apparent activation energy E_a of 0.62 eV (14.26 kcal/mol). This value is close to that determinate in the AP-MOVPE of GaAs.     

Band offsets at the (1 0 0)GaSb/Al2O3 interface from internal electron photoemission study

From electron internal photoemission and photoconductivity measurements at the (1 0 0)GaSb/Al₂O₃ interface, the top of the GaSb valence band is found to be 3.05 ± 0.10 eV below the bottom of the Al₂O₃ conduction band. This interface band alignment corresponds to conduction and valence band offsets of 2.3 ± 0.10 eV and 3.05 ± 0.15 eV, respectively, indicating that the valence band in GaSb lies energetically well above the valence band of In_xGa_1−xAs (0 ? x ? 0.53) or InP.     

Epitaxy of BaTiO3 thin film on Si(0 0 1) using a SrTiO3 buffer layer for non-volatile memory application

In this study we report the epitaxial growth of BaTiO₃ films on Si(0 0 1) substrate buffered by 5 nm-thick SrTiO₃ layer using both MBE and PLD techniques. The BaTiO₃ films demonstrate single crystalline, (0 0 1)-oriented texture and atomically flat surface on SrTiO₃/Si template. The electrical characterizations of the BaTiO₃ films using MFIS structures show that samples grown by MBE with limited oxygen pressure during the growth exhibit typical dielectric behavior despite post deposition annealing process employed. A ferroelectric BaTiO₃ layer is obtained using PLD method, which permits much higher oxygen pressure. The C-V curve shows a memory window of 0.75 V which thus enable BaTiO₃ possibly being applied to the non-volatile memory application.     

Performance enhancement in Ge pMOSFETs with <1 0 0> orientation fabricated with a Si-compatible process flow

The electrical characterization of Ge pMOSFETs having <1 1 0> and <1 0 0> orientations with gate lengths of 3 μm have been demonstrated with a Si-compatible process flow. Employment of <1 0 0> orientation in Ge pMOSFETs without incorporation of strain provided ∼10% enhancement in effective hole mobility and drive current when compared to <1 1 0> oriented regular transistors. In this fabrication technology, the effective hole mobility improves from 190 cm²/V s for <1 1 0> devices to 210 cm²/V s for the <1 0 0> oriented Ge devices at room temperature, which is ∼2 times the hole mobility of Si pFET devices. This study also presents first time investigation of post metallization anneal (PMA) at 350 °C in H₂ ambient for <1 0 0> Ge pMOSFETs. The overall performance of the devices has been enhanced by 15% after performing PMA. It is likely attributed to a strong decrease of D_it, improving the transistor performance. These results indicate that the <1 0 0> Ge pMOSFETs could be a viable candidate for future low voltage high speed CMOS applications.     

Performance of (1 1 0) p-channel SOI-MOSFETs fabricated by deep-amorphization and solid-phase epitaxial regrowth processes

The impact of local deep-amorphization (DA) and subsequent solid-phase epitaxial regrowth (SPER) are studied for the co-integration of devices with hybrid surface orientation. Thin-body p-channel transistors with 20 nm thick film and HfO₂ gate insulator/metal gate along several directions on a (1 1 0) substrate were fabricated and characterized. No deterioration of transconductance or threshold voltage was induced by DA/SPER process. Device co-integration using DA/SPER process is therefore a realistic option. 〈1 1 0〉 channel on (1 1 0) SOI film yields a 200% gain on the current for the (1 0 0) surface orientation. However, the benefit of it decreases with the channel length.     

In situ atomic layer deposition and synchrotron-radiation photoemission study of Al2O3 on pristine n-GaAs(0 0 1)-4 × 6 surface

This work presents the in situ reflection high-energy electron diffraction (RHEED), scanning tunneling microscopy (STM) and synchrotron-radiation photoemission studies for the morphological and interfacial chemical characterization of in situ atomic layer deposited (ALD) Al₂O₃ on pristine molecular beam epitaxy (MBE) grown Ga-rich n-GaAs (1 0 0)-4 × 6 surface. Both the RHEED pattern and STM image demonstrated that the first cycle of ALD-Al₂O₃ process reacted immediately with the GaAs surface. As revealed by in situ synchrotron-radiation photoemission studies, two types of surface As atoms that have excess in charge in the clean surface served as reaction sites with TMA. Two oxidized states were then induced in the As 3d core-level spectra with chemical shifts of +660 meV and +1.03 eV, respectively.     

Study of deep level defect behavior in undoped n-InP (1 0 0) after rapid thermal annealing

The effects of rapid thermal annealing on deep level defects in the undoped n-type InP with Ru as Schottky contact metal have been characterized using deep level transient spectroscopy (DLTS). It is observed that the as-deposited sample exhibit two deep levels with activation energies of 0.66 and 0.89 eV. For the samples annealed at 300 °C and 400 °C, a deep level is identified with activation energies 0.89 and 0.70 eV, respectively below the conduction band. When the sample is annealed at 500 °C, three deep levels are observed with activation energies 0.25, 0.32 and 0.66 eV. Annealing of the sample at 300 °C, orders the lattice of as-grown material by suppressing the defect 0.66 eV (A1) which is found in the as-deposited sample. The trap concentration of the 0.89 eV deep levels is found to be increased with annealing temperature. The deep level 0.32 eV may be due to the lattice defect by thermal damage during rapid thermal annealing process such as vacancies, interstitials and its complexes, indicating the damage of the sample after annealing at 500 °C. The defects observed in all the samples are possibly due to the creation of phosphorous vacancy or phosphorous antisite.     

Characterization of CMOS sub-65 nm metallic contact by laser scattering: Thermal stability of Ni(Si1−xGex)

Very efficient in particles detection, light scattering also offers fast non-invasive full-mapping wafer surface state. This sensitivity was used in the case of germano-silicide process development. As a matter of fact, we report on haze measurement performances, compared to the usual methods used to investigate thermal stability of Ni(Si_1−xGe_x), such as sheet resistance (SR), X-ray diffraction (XRD) and scanning electron microscopy (SEM). We observed defectivity related to thermal agglomeration and Ge-segregation of Ni(Si_1−xGe_x) on strain Si_1−xGe_x (x ? 30%) by haze measurement (like SEM observations) earlier than SR measurement. Moreover, we noticed that a high Ge content affects at lower temperature the stability of Ni(Si_1−xGe_x) with a segregation phenomena.     

Electron tunneling in MIS capacitors with the MBE-grown fluoride layers on Si(1 1 1) and Ge(1 1 1): Role of transverse momentum conservation

The current-voltage characteristics of the metal-insulator-semiconductor tunneling structures with calcium fluoride are simulated using different theoretical models. The results are compared to the data of current measurements on the fabricated capacitors with 1-3 nm epitaxial fluorides. Best agreement is achieved imposing a condition of transverse momentum k_⊥ conservation for a tunneling electron. This fact may be treated as an experimental proof for the k_⊥ conservation in the examined high-quality structures which was not directly confirmed on more traditional structures with oxide dielectrics.