Electrical properties of vacuum annealed La2O3 thin films grown by E-beam evaporation

In this article, the conduction mechanisms of metal-oxide-semiconductor with vacuum annealed Lanthana (La₂O₃) oxide film are investigated. Lanthana films with thicknesses of 3.5, 4.7, and 11 nm were deposited by E-beam evaporation on n-Si (100), and annealed at various temperatures (300-500 °C) in ultra-high vacuum (10⁻¹⁰-10⁻⁹ Torr) for 90 min. From the measurement of spectroscopic ellipsometry, it is found that film thickness is increased with annealing temperature, which would be cause of flat-band voltage shift (ΔV_FB) due to the growth of interfacial layer. From the capacitance measurement, it is found that ΔV_FB of the film is reduced by post-deposition anneal (PDA) compared to that of as-deposited film, but increase again at high temperature annealing, especially in the case of thin film (3.5 nm). From the applied voltage and temperature dependence of the leakage current of the film, with different gate electrode materials (Ag, Al, and Pt), it is shown that the leakage currents are associated with ohmic and Poole-Frenkel (P-F) conductions when flat-band voltage (V_FB) is less than zero, and ohmic and Space-Charge-Limited Current (SCLC) conductions when V_FB is greater than zero. The dielectric constants obtained from P-F conduction for Al gate electrode case is found to be 11.6, which is consistent with the C-V result 11.9. Barrier height of trap potential well is found to be 0.24 eV from P-F conduction. Based on SCLC theory, leakage currents of 3.5 and 11 nm films with different PDA temperatures are explained in terms of oxide trap density.     

LP-MOCVD growth of ternary BxGa1−xAs epilayers on (0 0 1)GaAs substrates using TEB, TMGa and AsH3

Zinc-blende B_xGa_1−xAs alloys have been successfully grown on exactly oriented (0 0 1)GaAs substrates using triethylboron, trimethylgallium and arsine sources. The growth has been accomplished in a vertical low-pressure metalorganic chemical vapor deposition (LP-MOCVD) reactor. Boron incorporation behaviors have been extensively studied as a function of growth temperature and gas-phase boron mole fraction. The evolution of surface morphology was also observed.The maximum boron composition of 5.8% is obtained at the optimum growth temperature of 580 °C. RMS roughness over the surface area of 1×1 μm² is only 0.17 nm at such growth conditions. Based on the experimental results, it has been clearly shown that boron incorporation will decrease significantly at higher temperature (>610 °C) or at much lower temperature (?550 °C).     

Charge trapping and interface characteristics in normally-off Al2O3/GaN-MOSFETs

Normally-off GaN-MOSFETs with Al₂O₃ gate dielectric have been fabricated and characterized. The Al₂O₃ layer is deposited by ALD and annealed under various temperatures. The saturation drain current of 330 mA/mm and the maximum transconductance of 32 mS/mm in the saturation region are not significantly modified after annealing. The subthreshold slope and the low-field mobility value are improved from 642 to 347 mV/dec and from 50 to 55 cm² V⁻¹ s⁻¹, respectively. The I_D-V_G curve shows hysteresis due to oxide trapped charge in the Al₂O₃ before annealing. The amount of hysteresis reduces with the increase of annealing temperature up to 750 °C. The Al₂O₃ layer starts to crystallize at a temperature of 850 °C and its insulating property deteriorates.     

Plasma-enhanced flexible metal-insulator-metal capacitor using high-k ZrO2 film as gate dielectric with improved reliability

We demonstrate a new flexible metal-insulator-metal capacitor using 9.5-nm-thick ZrO₂ film on a plastic polyimide substrate based on a simple and low-cost sol-gel precursor spin-coating process. The surface morphology of the ZrO₂ film was investigated using scan electron microscope and atomic force microscope. The as-deposited ZrO₂ film under suitable treatment of oxygen (O₂) plasma and then subsequent annealing at 250 °C exhibits superior low leakage current density of 9.0 × 10⁻⁹ A/cm² at applied voltage of 5 V and maximum capacitance density of 13.3 fF/μm² at 1 MHz. The as-deposited sol-gel film was completely oxidized when we employed O₂ plasma at relatively low temperature and power (30 W), hence enhancing the electrical performance of the capacitor. The shift (Zr 3d from 184.1 eV to 184.64 eV) in X-ray photoelectron spectroscopy of the binding energy of the electrons towards higher binding energy; clearly indicates that the O₂ plasma reaction was most effective process for the complete oxidation of the sol-gel precursor at relatively low processing temperature.     

Dependence of electrical properties on interfacial layer of Ta2O5 films

The change in the thickness and chemical states of the interfacial layer and the related electrical properties in Ta₂O₅ films with different annealing temperatures were investigated. The high-resolution transmission electron microscopy and X-ray photoelectron spectroscopy analyses revealed that the 700 °C-annealed Ta₂O₅ film remained to be amorphous and had the thinnest interfacial layer which was caused by Ta-silicate decomposition to Ta₂O₅ and SiO₂. In addition, the electrical properties were improved after annealing treatments. Our results suggest that an annealing treatment at 700 °C results in the highest capacitance and the lowest leakage current in Ta₂O₅ films due to the thinnest interfacial layer and non-crystallization.     

Effective formation of interface controlled Y2O3 thin film on Si(1 0 0) in a metal-(ferroelectric)-insulator-semiconductor structure

Yttrium was deposited on the chemical oxide of Si and annealed under vacuum to control the interface for the formation of Y₂O₃ as an insulating barrier to construct a metal-ferroelectric-insulator-semiconductor structure. Two different pre-annealing temperatures of 600 and 700 °C were chosen to investigate the effect of the interface state formed after the pre-annealing step on the successive formation of Y₂O₃ insulator and Nd₂Ti₂O₇ (NTO) ferroelectric layer through annealing under an oxygen atmosphere at 800 °C. Pre-anneal treatments of Y-metal/chemical-SiO₂/Si at 600 and 700 °C induced a formation of Y₂O₃ and Y-silicate, respectively. The difference in the pre-anneal temperature induced almost no change in the electrical properties of the Y₂O₃/interface/Si system, but degraded properties were observed in the NTO/Y₂O₃/interface/Si system pre-annealed at 600 °C when compared with the sample pre-annealed at 700 °C. C-V characteristics of the NTO/Y₂O₃/Si structured system showed a clockwise direction of hysteresis, and this gap could be used as a memory window for a ferroelectric-gate. A smaller hysteric gap and electrical breakdown values were observed in the NTO/Y₂O₃/Si system pre-annealed at 600 °C, and this was due to an unintentional distribution of the applied field from the presence of an interfacial layer containing Y-silicate and SiO₂ phases.     

Improvement on low-temperature deposited HfO2 film and interfacial layer by high-pressure oxygen treatment

In this study, high-pressure oxygen (O₂ and O₂ + UV light) technologies were employed to effectively improve the properties of low-temperature-deposited metal oxide dielectric films and interfacial layer. In this work, 13 nm HfO₂ thin films were deposited by sputtering method at room temperature. Then, the oxygen treatments with a high-pressure of 1500 psi at 150 °C were performed to replace the conventional high temperature annealing. According to the XPS analyses, integration area of the absorption peaks of O-Hf and O-Hf-Si bonding energies apparently raise and the quantity of oxygen in deposited thin films also increases from XPS measurement. In addition, the leakage current density of standard HfO₂ film after O₂ and O₂ + UV light treatments can be improved from 3.12 × 10⁻⁶ A/cm² to 6.27 × 10⁻⁷ and 1.3 × 10⁻⁸ A/cm² at |Vg| = 3 V. The proposed low-temperature and high pressure O₂ or O₂ + UV light treatment for improving high-k dielectric films is applicable for the future flexible electronics.     

High quality silicon nitride deposited by Ar/N2/H2/SiH4 high-density and low energy plasma at low temperature

The high-quality PECVD silicon nitride has been deposited by high-density and low-ion-energy plasma at 400 °C and the effect of the process parameters, such as silane and nitrogen flow rate, pressure, on its structure and electrical properties has been investigated. The experimental results show that silane flow rate is the most sensitive parameter for determining deposition rate and N/Si atomic ratio of silicon nitride in the range of process parameters employed. The change of nitrogen flow rate leaded to slightly change in deposition rate, however, it effects significantly on the refractive index or densification of silicon nitride. With the addition of hydrogen gas in plasma, the hysteresis of C-V characteristics of MIS structure decreases from 0.4 to 0.1 V. The moderate increment of ion energy makes further reduction in the hysteresis of C-V characteristics of MIS from 0.1 V to below 0.05 V. The interface trap density of 6.2×10¹⁰ (ev⁻¹ cm^-2), deduced from the high frequency and quasistatic C-V characteristics of the MIS structure, is about the same as that of LPECVD silicon nitride deposited at the range of 750-850 °C. The stoichiometric silicon nitride of excellence electric and structural properties is obtained by Ar/N₂/H₂/SiH₄ high-density and low ion energy plasma.     

Composition and electrical characteristics of Al2O3-HfO2-HfTiO nanolaminates on Si

A dielectric constant of 27 was demonstrated in the as deposited state of a 5 nm thick, seven layer nanolaminate stack comprising Al₂O₃, HfO₂ and HfTiO. It reduces to an effective dielectric constant (k_eff) of ∼14 due to a ∼0.8 nm interfacial layer. This results in a quantum mechanical effective oxide thickness (EOT) of ∼1.15 nm. After annealing at 950 °C in an oxygen atmosphere k_eff reduces to ∼10 and EOT increases to 1.91 nm. A small leakage current density of about 8 × 10⁻⁷ and 1 × 10⁻⁴ A/cm², respectively at electric field 2 and 5 MV/cm and a breakdown electric field of about 11.5 MV/cm was achieved after annealing at 950 °C.     

Structure and property of magnetron sputtered ternary cobalt-nickel silicide films

Ternary cobalt-nickel silicide films were prepared using magnetron sputtering from an equiatomic cobalt-nickel alloy target on Si substrate. The effect of post-deposition annealing on the phase formation, structural properties and resistivity of the resultant films has been studied. The results of XRD show that the annealing temperature and impurity level of oxygen play a crucial role in controlling the phase transformation of ternary silicide. Silicide phases are absent in the as-deposited film due to the amorphous nature. At relatively low annealing temperature, the phase of CoNi₃Si (2 2 0) and CoNiSi (2 2 0) coexist. With the increase of annealing temperature, the phase of CoNi₃Si (2 2 0) begins to transform into CoNiSi (2 2 0). At high annealing temperature (800 °C), only the phase of CoNiSi₂ (2 2 2) is formed. For Co-Ni silicide film annealed in pure argon gas ambient, two Raman peaks at 1357 cm⁻¹ and 1591 cm⁻¹ are attributed to the vibrational mode of CoSi₂ and NiSi₂ compounds. For ternary silicide annealed in atmosphere ambient, two Raman peaks located at 538 cm⁻¹ and 690 cm⁻¹ were observed and may be related to Si oxide or Co-Ni oxide. The 3D views of AFM images show that the surface roughness is relatively low when the silicidation temperature is smaller than 550 °C. After silicidation in 800 °C, the surface roughness increases abruptly. The resistance initially decreases with the increase of annealing temperature, and achieves minimum value (19 μΩ cm) in temperature ranges 500-550 °C. When the annealing temperature increases from 600 °C to 800 °C, the resistivity was found to increase slightly to 26 μΩ cm. The ternary silicide shows a temperature window for low resistivity as compared to binary NiSi.     

Hydrogen passivation effects under negative bias temperature instability stress in metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon capacitors for flash memories

The paper presents the passivation effect of post-annealing gases on the negative bias temperature instability of metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon (MONOS) capacitors. MONOS samples annealed at 850 °C for 30 s by a rapid thermal annealing (RTA) are treated by additional annealing in a furnace, using annealing gases N₂ and N₂-H₂ (2% hydrogen and 98% nitrogen gas mixture) at 450 °C for 30 min. MONOS samples annealed in an N₂-H₂ environment are found to have lowest oxide trap charge density shift, ΔN_ot = 8.56 × 10¹¹ cm⁻², and the lowest interface-trap density increase, ΔN_it = 4.49 × 10¹¹ cm⁻² among the three samples as-deposited, annealed in N₂ and N₂-H₂ environments. It has also been confirmed that the same MONOS samples have the lowest interface-trap density, D_it = 0.834 × 10¹¹ eV⁻¹ cm⁻², using small pulse deep level transient spectroscopy. These results indicate that the density of interface traps between the silicon substrate and the tunneling oxide layer are significantly reduced by the additional furnace annealing in the N₂-H₂ environment after the RTA.     

Co gamma irradiation effects on electrical characteristics of Al/Y2O3/n-Si/Al capacitors

Al/Y₂O₃/n-Si/Al capacitors were irradiated by using a ⁶⁰Co gamma ray source and a maximum dose up to 8.4 kGy. The effect of an annealing treatment performed at 600 or 900 °C on the yttrium oxide (Y₂O₃) films was investigated by XRD and Raman spectroscopy. High-frequency capacitance-voltage (C-V) and conductance-voltage (G-V) measurements as well as quasi-static measurements of the MOS structures were analysed. The annealing improves the crystalline state of the Y₂O₃ thin film material and decreases the values of the flat-band voltage and of the interface trap level density indicating an improvement of the electrical properties of the interface thin film-substrate. But at this interface, the formation of an yttrium-silicate layer was also evidenced. After gamma irradiation, the values of the flat-band voltage and of the interface trap level density related to the Al/Y₂O₃/n-Si/Al structure increase and especially for the structure made with the materials annealed at 900 °C for 1 h. In that case, the structure is very sensitive to a gamma irradiation dose up to 8.4 kGy.     

Effect of post annealing on the resistive switching of TiO2 thin film

The effect of annealing on the resistive switching of 35-nm-thick TiO₂ thin film deposited with magnetron sputtering system was studied. Pt and Ag were used as a top electrode (TE), and Pt was used as a bottom electrode (BE). For Pt/as-deposited TiO₂/Pt structure, both unipolar (URS) and bipolar resistive switching (BRS) were observed depending on the current compliance level. For Pt/400 °C annealed TiO₂/Pt structure, only BRS was observed regardless of the current compliance level. The increase in the work function of the TiO₂ film after annealing lowers the potential barrier height and changes the electron transfer process which was also confirmed from Ag/as-deposited TiO₂/Pt structure. Above 600 °C, the film becomes leaky with the increase in grain size and roughness and the resistive switching behavior was not observed.     

Fabrication and characterization of Zr-rich Zr-aluminate films for high-κ gate dielectric applications

Two kinds of Zr-rich Zr-aluminate films for high-κ gate dielectric applications with the nominal composition of (ZrO₂)_0.8(Al₂O₃)_0.2 and (ZrO₂)_0.9(Al₂O₃)_0.1, were deposited on n-type silicon wafer by pulsed laser deposition (PLD) technique at different deposition conditions. X-ray diffraction (XRD) reveals that the (ZrO₂)_0.8(Al₂O₃)_0.2 film could remain amorphous after being rapid thermal annealed (RTA) at the temperature above 800 °C, while the other one displays some crystalline peaks at 700 °C. The energy gap calculated from optical transmittance spectrum of (ZrO₂)_0.8(Al₂O₃)_0.2 film on quartz is about 6.0 eV. Sputtering depth profile of X-ray photoelectron spectroscopy and Auger electron spectroscopy indicate that a Zr-Si-O interfacial layer was formed at the near surface of the silicon substrate. The dielectric constant of the (ZrO₂)_0.8(Al₂ O₃)_0.2 film has been determined to be 22.1 by measuring a Pt/(ZrO₂)_0.8(Al₂ O₃)_0.2/Pt MIM structure. An EOT of 1.76 nm with a leakage current density of 51.5 mA/cm² at 1 V gate voltage for the film deposited in N₂ were obtained. Two different pre-treatments of Si substrates prior to depositions were also carried out and compared. The results indicate that a surface-nitrided Si substrate can lead to a lower leakage current density. The amorphous Zr-rich Zr-aluminate films fabricated by PLD have promising structure and dielectric properties required for a candidate material for high-κ gate dielectric applications.     

Optical characteristics of Si/SiO2 multilayers prepared by magnetron sputtering

Si/SiO₂ multilayers have been successfully prepared by magnetron sputtering and subsequently thermal annealed in an Ar atmosphere at a temperature of more than 500 °C. The surface of the as-deposited films is compact and smooth, and the distribution of grain size estimated to be 20 nm is uniform. For Si/SiO₂ multilayers annealed at 1100 °C, the Si sublayer sandwiched between potential barrier SiO₂ is crystalline structure by means of the analysis of Raman spectra and XRD data. The visible PL peak accompanying to a blue-shift with the decrease of Si sublayer thickness has been observed, and the intensity of this peak enhances with the increase of annealing temperature. The visible luminescence properties of Si/SiO₂ multilayers can be ascribed to quantum confinement of electron-hole pairs in quantum wells with grain size lower than 4.5 nm. In Si/SiO₂ multilayers, not only quantum confinement but also Si-SiO₂ interface states play an important role in the optical transition. The PL peak located at 779 nm is independent of the thickness of Si sublayer, so it may be ascribed to interface mediated transition. Typical Si dangling bonds defect could be a dominating obstacle to high luminescence efficiencies.     

Infrared spectroscopy and X-ray diffraction studies on the crystallographic evolution of La2O3 films upon annealing

Rare earth oxides (REOs) have lately received extensive attention in relation to the continuous scaling down of non-volatile memories (NVMs). In particular, La₂O₃ films are promising for integration into future NVMs because they are expected to crystallize above 400 °C in the hexagonal phase (h-La₂O₃) which has a higher κ value than the cubic phase (c-La₂O₃) in which most of REOs crystallize. In this work, La₂O₃ films are grown on Si by atomic layer deposition using La(C₅H₅)₃ and H₂O. Within the framework of the h-La₂O₃ formation, we systematically study the crystallographic evolution of La₂O₃ films versus annealing temperature (200-600 °C) by Fourier transform infrared spectroscopy (FTIR) and grazing incidence X-ray diffraction (GIXRD). As-grown films are chemically unstable in air since a rapid transformation into monoclinic LaO(OH) and hexagonal La(OH)₃ occurs. Vacuum annealing of sufficiently thick (>100 nm) La(OH)₃ layers induces clear changes in FTIR and GIXRD spectra: c-La₂O₃ gradually forms in the 300-500 °C range while annealing at 600 °C generates h-La₂O₃ which exhibits, as inferred from our electrical data, a desirable κ ∼ 27. A quick transformation from h-La₂O₃ into La(OH)₃ occurs due to H₂O absorption, indicating that the annealed films are chemically unstable. This study extends our recent work on the h-La₂O₃ formation.     

Self-aligned n-channel GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using HfO2 and silicon interface passivation layer: Post-metal annealing optimization

In this work, using Si interface passivation layer (IPL), we demonstrate n-MOSFET on p-type GaAs by varying physical-vapor-deposition (PVD) Si IPL thickness, S/D ion implantation condition, and different substrate doping concentration and post-metal annealing (PMA) condition. Using the optimized process, TaN/HfO₂/GaAs n-MOSFETs made on p-GaAs substrates exhibit good electrical characteristics, equivalent oxide thickness (EOT) (∼3.7 nm), frequency dispersion (∼8%) and high maximum mobility (420 cm²/V s) with high temperature PMA (950 °C, 1 min) and good inversion.     

SrO capping effect for La2O3/Ce-silicate gate dielectrics

The chemical bonding states and electrical characteristics of SrO capped La₂O₃/CeO_x gate dielectric have been examined. Angle-resolved X-ray photoelectron spectroscopy measurement has revealed that Sr atoms diffuse into silicate layer to form SrLa-silicate after annealing. Owing to the incorporation of Sr atoms into silicate layer, a transistor operation with an equivalent oxide thickness (EOT) below 0.5 nm has been demonstrated. A strongly degraded effective electron mobility of 78 cm²/V s at 1 MV/cm has been obtained, which fit well with the general trend in small EOT range below 1 nm. Although process optimization is needed to improve the performance of transistors, Sr capping technique can be useful for EOT scaling.     

Hf-O-N and HfO2 barrier layers for Hf-Ti-O gate dielectric thin films

Hf-O-N and HfO₂ thin films were evaluated as barrier layers for Hf-Ti-O metal oxide semiconductor capacitor structures. The films were processed by sequential pulsed laser deposition at 300 °C and ultra-violet ozone oxidation process at 500 °C. The as-deposited Hf-Ti-O films were polycrystalline in nature after oxidation at 500 °C and a fully crystallized (o)-HfTiO₄ phase was formed upon high temperature annealing at 900 °C. The Hf-Ti-O films deposited on Hf-O-N barrier layer exhibited a higher dielectric constant than the films deposited on the HfO₂ barrier layer. Leakage current densities lower than 5 × 10 A/cm² were achieved with both barrier layers at a sub 20 Å equivalent oxide thickness.