Application of direct-tunneling gate oxides to high-performance CMOS

The characteristics of direct-tunneling gate oxide metal-oxide semiconductor field effect transistor (MOSFET)s are described. The effect of gate leakage current on MOSFET characteristics drops off as the gate length is reduced. Extremely good DC and AC performance has been realized using ultra-thin oxides down to 1.5 nm. Improved hot-carrier reliability and high oxide breakdown voltage have also been observed.     

1200V大容量SiC MOSFET器件研制

采用平面栅MOSFET器件结构,结合优化终端场限环设计、栅极bus-bar设计、JFET注入设计以及栅氧工艺技术,基于自主碳化硅工艺加工平台,研制了1200V大容量SiC MOSFET器件.测试结果表明,器件栅极击穿电压大于55V,并且实现了较低的栅氧界面态密度.室温下,器件阈值电压为2.7V,单芯片电流输出能力达到50A,器件最大击穿电压达到1600V.在175℃下,器件阈值电压漂移量小于0.8V;栅极偏置20V下,泄漏电流小于45nA.研制器件显示出优良的电学特性,具备高温大电流SiC芯片领域的应用潜力.     

Substrate-bias effect and source-drain breakdown characteristics inbody-tied short-channel SOI MOSFET's

The substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel silicon-on-insulator metal oxide semiconductor field effect transistors (SOI MOSFET's) were investigated. Here, “substrate bias” is the body bias in the SOI MOSFET itself. It was found that the transistor body becomes fully depleted and the transistor is released from the substrate-bias effect, when the body is reverse-biased. Moreover, it was found that the source-drain breakdown voltage for reverse-bias is as high as that for zero-bias. This phenomenon was analyzed using a three-dimensional (3-D) device simulation considering the body-tied SOI MOSFET structure in which the body potential is fixed from the side of the transistor. This analysis revealed that holes which are generated in the transistor are effectively pulled out to the body electrode, and the body potential for reverse-bias remains lower than that for zero-bias, and therefore, the source-drain breakdown characteristics does not deteriorate for reverse-bias. Further, the influence of this effect upon circuit operation was investigated. The body-tied configuration of SOI devices is very effective in exploiting merits of SOI and in suppressing the floating body-effect, and is revealed to be one of the most promising candidates for random logic circuits such as gate arrays and application specific integrated circuits     

Modelling of gate-induced drain leakage in relation to technological parameters and temperature

The junction breakdown of a MOS transistor with thin gate oxide, imposed undesirable problems. This phenomenon is attributed, particularly, to band-to-band tunnelling occurring in the gate-to-drain overlap region. This is the source of a gate-induced drain leakage (gidl) current I_gidl, limiting therefore the further MOSFET scaling. In this paper we ara interested in the modelling of this current. The model is used to investigate the influence of the technological parameters and the temperature on I_gidl current characteristics.     

A new protection circuit for high-voltage current saturation of LEST

A new protection circuit for high-voltage current saturation of a lateral emitter switched thyristor (LEST) is proposed. We fabricated this circuit by employing a widely used insulated gate bipolar transistor compatible process. A high-voltage current saturation exceeding 200 V was measured in the EST with the proposed protection circuit, while the current saturation of the conventional LEST is limited to 17 V by the breakdown of the lateral MOSFET.     

A high power MOSFET with a vertical drain electrode and a meshed gate structure

A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel width per unit area. The p-channel device with an offset gate structure was fabricated from an n on p/SUP +/ epitaxial wafer by using polysilicon gate and ion implantation processes. The device can be operated stably at ambient temperatures up to 180/spl deg/C. While the bipolar transistor is a suitable power device in the low voltage region, the MOSFET looks more promising in the high voltage region than the V-FET and the bipolar transistor.     

Effect of oxide breakdown on RS latches

In this work, the influence of the oxide breakdown on RS latches performance has been analysed. The NAND and NOR RS latch topologies have been compared in terms of noise margin and switching times for different broken down transistors. Moreover, the influence of the additional current path due to BD and of the variation of the MOSFET parameters on the circuit functionality have been separately evaluated. The results show that RS latches do not lose functionality after BD. However, reductions on noise margin and variations on switching times are observed, which depend on the damaged transistor. The performance degradation of the circuit is mainly due to the additional post-BD gate current whereas the variation of the BD MOSFET parameters has only a small influence.     

A new vertical double diffused MOSFET—The self-aligned terraced-gate MOSFET

A new power MOSFET structure with a Self-aligned Terraced Gate (STGMOSFET) is demonstrated. The unique gate structure of the STGMOSFET reduces the parasitic gate capacitances, resulting in improved high-frequency performance. The STGMOSFET structure was used to design a 3.5 mm × 3.5 mm transistor. This chip had an on-resistance of 2.3 Ω and a 500-V source-drain breakdown voltage. It exhibited excellent high-frequency performance with a cut-off frequency of 100 MHz, and rise and fall times of 5 and 20 nS, respectively.     

Influence of dielectric breakdown on MOSFET drain current

Breakdown of gate dielectric is one of the most dangerous threats for reliability of MOSFET devices in operating conditions. Not only the gate leakage resulting from breakdown is a problem for power consumption issues, but the "on" drain current can be strongly affected. In this paper, we show that in recent technologies, featuring ultrathin gate dielectrics, the corruption of drain current due to breakdown can be modeled as the effect of a portion of channel being damaged by the opening of the breakdown spot. Devices featuring 2.2- and 3.5-nm-thick gate oxide and various channel widths are stressed by using a specialized setup, and the degradation of transistor parameters is statistically studied. The analysis shows that the radius of the damaged region responsible for drain current degradation can be estimated between 1.4 and 1.8 /spl mu/m.     

MOSFET Performance Scaling—Part II: Future Directions

The analytical MOSFET intrinsic delay introduced in Part I of this paper is used to examine the tradeoffs between key device elements required in order for the performance scaling trend to continue in future high-performance CMOS generations. A scaling scenario based on contacted source/drain gate pitch is presented and used to examine the prospects of MOSFET performance in the future nodes. It is shown that, from 32-nm node onwards, MOSFET performance will counterscale, mainly due to increase in the parasitic gate capacitance as a result of proximity of the gate and source/drain electrodes. As a case study, the dependence of the transistor performance on various device parameters at the 32-nm node is analyzed. Reducing the fringing capacitance is shown to be the most effective approach to meet the required transistor delay.     

Contributions of the gate current and channel current variation to the post-breakdown MOSFET performance

A new approach to the modelling of the post-breakdown (BD) performance of MOSFETs for circuit simulation is presented, which separately considers the additional post-BD gate current and the variation of the MOSFET channel current. The post-BD gate current is modelled using an improved equivalent circuit whereas the BSIM4 model is used to describe the MOSFET channel current. This approach has allowed to analyse the contributions of both currents on the post-BD I_D-V_D characteristics. The results show that the gate current increase and the variation of the channel current are determining factors of the MOSFET performance degradation after BD.     

The impact of postbreakdown gate leakage on MOSFET RF performances

When the gate-oxide of a MOSFET breaks down, a leakage path is created between channel and gate. In this work, we demonstrate that a simple leakage current increase model can predict the impact of gate-oxide breakdown on MOSFET performance from dc to microwave frequency. We show that severe reduction in RF performance due to input/output mismatch and a gain reduction can result from gate-oxide breakdown     

Dual MOS gate controlled thyristor (DMGCT) structure withshort-circuit withstand capability superior to IGBT

A dual MOS gate controlled thyristor (DMGCT) structure is analyzed with experimental data and shown to have superior performance over insulated-gate bipolar transistor (IGBT) for power switching applications. The DMGCT device structure consists of a thyristor structure with the thyristor current constrained to flow via the channel region of a MOSFET. Although this increases the on-state voltage drop in the thyristor current path by a small amount due to the voltage drop across the low-voltage series MOSFET, this structure allows control of the thyristor current by the gate voltage applied to the MOSFET even after latch-up of the thyristor. This configuration allows uniform turn-off in the device with no current crowding. The DMGCT does not have any parasitic thyristor structure. In contrast to the IGBT, the saturation current of the DMGCT can be controlled independently of the on-state voltage drop     

具有栅介质电场屏蔽作用的新型GaN纵向槽栅MOSFET器件设计

基于氮化镓(GaN)等宽禁带(WBG)半导体的金氧半场效应晶体管(MOSFET)器件在关态耐压下,栅介质中存在与宽禁带半导体临界击穿电场相当的大电场,致使栅介质在长期可靠性方面受到挑战。为了避免在GaN器件中使用尚不成熟的p型离子注入技术,提出了一种基于选择区域外延技术制备的新型GaN纵向槽栅MOSFET,可通过降低关态栅介质电场来提高栅介质可靠性。提出了关态下的耗尽区结电容空间电荷竞争模型,定性解释了栅介质电场p型屏蔽结构的结构参数对栅介质电场的影响规律及机理,并通过权衡器件性能与可靠性的关系,得到击穿电压为1 200 V、栅介质电场仅0.8 MV/cm的具有栅介质长期可靠性的新型GaN纵向槽栅MOSFET。     

Nondestructive determination of MOSFET gate breakdown voltage

A method is presented which allows the gate breakdown of a MOSFET to be nondestructively determined. The method applies a linear ramp voltage across the gate, allowing the leakage component to be easily separated from the capacitive currents. In this manner, the leakage component can be measured before it becomes large enough to cause a destructive dielectric breakdown in the gate oxide.     

Advantage of further scaling in gate dielectrics below 0.5 nm of equivalent oxide thickness with La2O3 gate dielectrics

N-type metal-oxide-semiconductor field-effect transistor (MOSFET) with an equivalent oxide thickness (EOT) of 0.37 nm has been demonstrated with La₂O₃ as a gate dielectric for the first time. Despite the existence of parasitic capacitances at gate electrode and inversion layer in the channel, a sufficient drain current increment in both linear and saturation regions have been observed, while scaling the gate oxide from 0.48 to 0.37 nm in EOT. Therefore, continuous scaling of EOT below 0.5 nm is still effective for further improvement in device performance.     

An analytical avalanche breakdown model for double gate MOSFET

An analytical model of avalanche breakdown for double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is presented. First of all, the effective mobility (μ_eff) model is defined to replace the constant mobility model. The channel length modulation (CLM) effect is modeled by solving the Poisson’s equation. The avalanche multiplication factor (M) is calculated using the length of saturation region (ΔL). It is shown that the avalanche breakdown characteristics calculated from the analytical model agree well with commercially available 2D numerical simulation results. Based on the results, the reliability of the DG MOSFET can be estimated using the proposed analytical model.     

Gate-oxide breakdown accelerated by large drain current inn-channel MOSFET's

A study of the time-dependent dielectric breakdown (TDDB) of thin gate oxides in small n-channel MOSFETs operated beyond punchthrough is discussed. Catastrophic gate-oxide breakdown is accelerated when holes generated by the large drain current are injected into the gate oxide. More specifically, the gate-oxide breakdown in a MOSFET (gate length=1.0 μm, gate width-15 μm) occurs in ~100 s at an applied gate oxide field of ~5.2 MV/cm during the high drain current stress, while it occurs in ~100 s at an applied gate oxide field of ~10.7 MV/cm during a conventional time-dependent dielectric breakdown (TDDB) test. The results indicate that the gate oxide lifetime is much shorter in MOSFETs when there is hot-hole injection than that expected using the conventional TDDB method     

In search of "Forever," continued transistor scaling one new material at a time

This work looks at past, present, and future material changes for the metal-oxide-semiconductor field-effect transistor (MOSFET). It is shown that conventional planar bulk MOSFET channel length scaling, which has driven the industry for the last 40 years, is slowing. To continue Moore's law, new materials and structures are required. The first major material change to extend Moore's law is the use of SiGe at the 90-nm technology generation to incorporate significant levels of strain into the Si channel for 20%-50% mobility enhancement. For the next several logic technologies, MOSFETs will improve though higher levels of uniaxial process stress. After that, new materials that address MOSFET poly-Si gate depletion, gate thickness scaling, and alternate device structures (FinFET, tri-gate, or carbon nanotube) are possible technology directions. Which of these options are implemented depends on the magnitude of the performance benefit versus manufacturing complexity and cost. Finally, for future material changes targeted toward enhanced transistor performance, there are three key points: 1) performance enhancement options need to be scalable to future technology nodes; 2) new transistor features or structures that are not additive with current enhancement concepts may not be viable; and 3) improving external resistance appears more important than new channel materials (like carbon nanotubes) since the ratio of external to channel resistance is approaching /spl sim/1 in nanoscale planar MOSFETs.     

A multiple-terminal gate charging model

A gate charging model considering charging effect at all terminals of a MOSFET is reported in this letter. The model indicates two distinct charging mechanisms existing in P MOSFETs with a protecting device at their gates during plasma processing. The "normal-mode" charging mechanism exists when antenna size at the gate is higher than that at other terminals combined. In contrast, the "reverse-mode" charging mechanism exists in the case of antenna size at the gate lower than that at other terminals combined. The normal-mode mechanism will dominate the charging event when there is no protecting device at the transistor gate or the protecting device provides very low leakage current. On the other hand, the reverse-mode mechanism becomes dominant if the protecting device provides very high leakage current. The normal-mode charging mechanism is limited by the N-well junction leakage while in the reverse-mode mechanism, it is limited by the leakage of the protecting device. The model also suggests that larger N-well junction gives rise to higher charging damage in the normal-mode mechanism while it is opposite in the reverse-mode mechanism. These were confirmed by experimental data. The model points out that a zero charging damage can be achieved at certain combinations of the gate, source, drain and N-well antenna ratio. The knowledge of these transistor terminal antenna-ratio combinations will maximize the effective usage of the charging protection devices in circuit design. The reverse-mode charging mechanism suggests that the use of a high-leakage device at the transistor gate for charging protection may cause an opposite effect when the transistor terminal antenna ratios run into a condition that triggers this mechanism. This implies that PMOS transistors with gate intentionally pinned at ground or low potential in circuits may be prone to charging damage depending on the connectivity of their source, drain, and NW.