一种基于BSIM-CMG的FinFET变容管模型

提出了一种适用于FinFET变容管的建模方法.在BSIM-CMG的基础上,模型采用衬底模型和外围寄生模型来表征变容管的射频寄生效应.提出了具体的参数提取方法,将测试的S参数导入到安捷伦IC-CAP建模软件提取参数,测试结构引入高频寄生采用(open+ short)去嵌方法进行去嵌.通过调节模型参数拟合测试曲线得到FinFET变容管模型.该模型可精确表述FinFET变容管全工作区域特性,解决传统MOS变容管模型无法准确描述三维FinFET器件变容特性的问题.模型和模型参数提取方法采用20个硅鳍、16个栅指、158 nm栅长、578 nm栅宽的FinFET变容管进行建模验证,模型仿真和测试所得C-V,R-V和S参数特性吻合良好.     

A new small-signal modeling approach applied to GaN devices

A new small-signal modeling approach applied to GaN-based devices is presented. In this approach, a new method for extracting the parasitic elements of the GaN device is developed. This method is based on two steps, which are: 1) using cold S-parameter measurements, high-quality starting values for the extrinsic parameters that would place the extraction close to the global minimum of the objective function for the distributed equivalent circuit model are generated and 2) the optimal model parameter values are searched through optimization using the starting values already obtained. The bias-dependent intrinsic parameter extraction procedure is improved for optimal extraction. The validity of the developed modeling approach and the proposed small-signal model is verified by comparing the simulated wide-band small-signal S-parameter, over a wide bias range, with measured data of a 0.5-/spl mu/m GaN high electron-mobility transistor with a 2/spl times/50 /spl mu/m gatewidth.     

Determination and Validation of New Nonlinear FinFET Model Based on Lookup Tables

The Fin field effect transistor (FinFET) is a multiple gate structure, which is recently emerging as a leading structure to continue the scaling of CMOS technology into the nanometer regime. This promising multiple gate structure has not only the advantage of reducing short channel effects but also of being compatible with the conventional planar CMOS technology. To our knowledge, this is the first letter addressing the nonlinear FinFET model validated by large signal network analyzer measurements. Here, we present a nonlinear FinFET model which is based on lookup tables. The accuracy of the developed model is completely and successfully verified through the comparison with nonlinear FinFET measurements     

A PSP-Based Small-Signal MOSFET Model for Both Quasi-Static and Nonquasi-Static Operations

In this paper, a small-signal MOSFET model is described, which takes the local effects of both velocity saturation and transverse mobility reduction into account. The model is based on the PSP model and is valid for both quasi-static and nonquasi-static (NQS) operations. Recently, it has been found that, in the presence of velocity saturation, the low-frequency capacitances cannot be determined from the Ward-Dutton charge-partitioning scheme. By use of the small-signal model developed in this paper, it is demonstrated that, in the presence of velocity saturation, no terminal drain and source charges exist, from which the capacitances can be derived. The small-signal model enables the determination of the correct capacitive behavior in the presence of velocity saturation. Furthermore, it is demonstrated how the small-signal model can be used to determine the number of collocation points needed in the large-signal NQS PSP model. Finally, inclusion of the local variation of mobility reduction due to the vertical electrical fields provides insight into the approach commonly applied in compact modeling, where these fields are replaced by global ones depending on the terminal voltages only.     

Modeling of single-stage converters with high power factor and fastregulation

This paper presents an approach to systematically model single-stage DC/DC converters operated in discontinuous conduction mode (DCM) based on the graft scheme. With the graft scheme, the active switches which are with a common node and operating in unison can be integrated to form a single stage converter (SSC). The small-signal models of the SSC can, therefore, be derived by combining those of its originally separate converters. Using the proposed approach can help yield highly related dynamic models of the converters in a family and, in addition, physical insights between the converters can be readily identified. Moreover, the expressions of the small-signal models for the SSCs operated in DCM can be extended to those in continuous-conduction-mode operation. These have made the proposed modeling method valuable and viable. Experimental measurements have demonstrated that the small-signal model of an SSC derived with the proposed approach is relatively accurate     

Gate Oxide Short Defect Model in FinFETs

FinFET technology is one of the most promising candidates in replacing planar MOSFET beyond the 22 nm technology node. However, the complexity of FinFET manufacturing process has caused challenges in reliable device testing. Gate oxide short (GOS) is one of the dominant defects that has significant impact on circuit reliability. In this paper, we present a GOS defect model for FinFETs by introducing the defect as a pinhole in the gate oxide of a triangular fin shape structure. The pinholes are represented by small cuboid cuts of various sizes on the fin top and sidewalls along the channel. The 3D Sentaurus TCAD simulation results in the development of an analytical GOS defect model that can be used in circuit-level fault modeling, which leads to generating more realistic test patterns.     

基于能量守恒平均模型的开关变换器建模

文中介绍了一种常用的开关变换器建模方法——能量守恒平均法,依据能量守恒平均原理,建立连续模式下Buck变换器的直流和小信号模型,并给出开环传递函数。仿真分析表明,该模型能够准确描述变换器的频域特性,验证了理论推导的有效性。     

A physical based model to predict performance degradation of FinFET accounting for interface state distribution effect due to hot carrier injection

A physical based model for predicting the performance degradation of the FinFET is developed accounting for the interface state distribution effect due to hot carrier injection (HCI). The non-uniform distribution of interface state along the FinFET channel is first extracted by a forward gated-diode method and then reproduced by an empirical model. From this, a physical-based device model, which accounts for the interface state distribution effect, is developed to predict the performance degradation of FinFET. The result shows that the developed model not only matches well with the experimental data of FinFET in all operation regions, but also predicts the asymmetric degradation of saturation drain current in forward and reverse operation mode. Finally, the impact of HCI to a 6-T SRAM cell is simulated using HSPICE.     

Modeling and control of a synchronous generator with an active DCload

The design and analysis of a system consisting of a variable-speed synchronous generator that supplies an active DC load (inverter) through a three-phase diode rectifier requires adequate modeling in both time- and frequency-domains. As an example, the system's control-loops are difficult to design without an accurate small-signal model; at the same time, the system protection design requires large-signal transient modeling. A particularity of the described system is strong nonideal operation of the diode rectifier, a consequence of the large value of the generator's synchronous impedance. This nonideal behavior influences both steady-state and transient performance. This paper presents an average model of the system that accounts, in a detailed manner for the dynamics of the power source and the load, and for the effects of the nonideal operation of the diode rectifier. The model is nonlinear, but time-continuous, and can be used for large- and small-signal analysis. The developed model was verified on a 105 kW generator-set with inverter output, whose DC-link voltage control-loop design was successfully carried out based on the average model. It is shown that a high bandwidth is needed for this control-loop in order to achieve the proper impedance matching between the power source and the active electronic load     

RF electro-thermal modeling of LDMOSFETs for power-amplifier design

A new approach for the electro-thermal modeling of LDMOSFETs for power-amplifier design that bypasses pulsed-IVs and pulsed-RF measurements is presented in this paper. The existence of low-frequency dispersion in LDMOSFETs is demonstrated by comparing pulsed IVs with iso-thermal IVs. The modeling technique uses iso-thermal IV and microwave measurements to obtain the temperature dependence of small-signal parameters. Optimized tensor-product B-splines, which distribute knots to minimize fitting errors, are used to represent the small-signal parameters and extract the large-signal model as a function of voltages and temperature. The model is implemented on ADS and is verified by simulating and measuring the power harmonics and IMD large-signal performance of a power amplifier. The impact on the model of temperature-dependent drain and gate charge is investigated. The presented model is found to compare well and, in some cases, exceed the existing MET model for LDMOSFETs     

Millimeter-wave FET modeling using on-wafer measurements and EMsimulation

Electron device modeling is a challenging task at millimeter-wave frequencies. In particular, conventional approaches based on lumped equivalent circuits become inappropriate to describe complex distributed and coupling effects, which may strongly affect the transistor performance. In this paper, an empirical distributed FET model is adopted that can be identified on the basis of conventional S-parameter measurements and electromagnetic simulations of the device layout. The consistency of the proposed approach is confirmed by robust scaling properties, which enable millimeter-wave small-signal S-parameters to be predicted as a function of the device periphery and number of gate fingers. Moreover, it is shown how the model identified on the basis of standard S-parameter measurements up to 50 GHz can be efficiently exploited in order to obtain reasonably accurate small-signal prediction up to 110 GHz. Extensive experimental validation is presented for 0.2-μm pseudomorphic high electron-mobility transistors devices     

Modeling of the high-power-factor discontinuous boost rectifiers

This paper presents a modeling approach to obtain a small-signal model for a single-switch single-phase and three-phase discontinuous boost high-power-factor rectifiers. Such converters present nonlinear characteristics, and an approximation of them is used to derive the models. The most important result obtained is that the small-signal output impedance is not equal to the load impedance. The analysis is validated by experimental results     

Parasitics Realization in State-Space Average-Value Modeling of PWM DC–DC Converters Using an Equal Area Method

Average-value modeling of pulsewidth-modulation dc-dc converters is often based on the assumption of piecewise-linear waveforms of the circuit variables, whereas considering parasitics introduces waveform nonlinearity and complicates the model derivation. This paper presents a new approach that considers averaging with nonlinear waveforms using the equivalent area method, and proposes a state-space averaged model that is fairly accurate and seamlessly functional in both continuous and discontinuous conduction modes. The resulting average-value model is applicable for large-signal transient studies as well as for linearization and subsequent small-signal analysis. The proposed model is validated with a hardware prototype and a detailed simulation, and is shown to be an improvement over previously established models in the time and frequency domains.     

一种基于数值模型的4H-SiC MESFET大信号建模方法

提出了一种基于数值模型的4H-SiC MESFET大信号建模方法.该方法基于4H-SiC MESFET的物理参数和结构参数,采用MEDICI的小信号正弦稳态分析法和高频小信号等效电路,模拟得到电流和电容的非线性特性,通过大信号等效电路,分析了建立4H-SiC MESFET大信号模型的途径.模拟与实验测试值的比较表明这种方法是可行的,可用于预先评估器件大信号工作时的非线性特性,指导4H-SiC MESFET的器件设计.     

A nonquasi-static table-based small-signal model of heterojunction bipolar transistor

A nonquasi-static table-based (NQS-TB) small-signal model, which has been used successfully in modeling FETs, is applied to a heterojunction bipolar transistor (HBT). The capacitive couplings associated with base cause the conventional model to be invalid at high frequencies. To take these effects into account, a new model is proposed that is compatible with a small-signal T-model topology. We demonstrate good agreement between the measured and simulated S-parameters over the range of 1-40 GHz.     

基于25 nm FinFET结构的SRAM单粒子效应研究

对基于25 nm FinFET结构的SRAM单粒子效应进行研究。使用Synopsys Sentaurus TCAD仿真软件进行器件工艺校准,并对独立3D FinFET器件以及包含FinFET器件和HSpice模型的混合电路(如6管SRAM单元)进行单粒子瞬态仿真。通过改变重粒子入射条件,分析影响瞬态电流峰值、脉宽、漏极翻转阈值等参数的因素。研究发现,混合模型中,FinFET结构器件的漏极翻转阈值为0.023 MeV·cm²/mg,对未来基于FinFET结构的器件及电路结构的加固提出了更高的要求。     

Four-Port Network Parameters Extraction Method for Partially Depleted SOI with Body-Contact Structure

This work presents a model parameter extraction method based on four-port network for RF SOI MOSFET modeling. The gate, drain, source and body terminals are served as four separate ports. Four-port measurement simplifies the determination of small-signal equivalent circuit model elements such as parameters related to the body terminal which become clear in the equivalent circuit analysis. The extraction method of the RF SOI MOSFET extrinsic parasitic elements was also presented. The accuracy of the model extraction was verified by measurement and simulation from 100 MHz to 20 GHz.     

A new approach to model nonquasi-static (NQS) effects for MOSFETs. Part II: Small-signal analysis

We present a new approach to model nonquasi-static (NQS) effects in a MOSFET in a small-signal situation. The model derived here is based on the large-signal NQS model previously proposed. The derivation of the small-signal model is presented. The small-signal parameters obtained with this model prove to be accurate up to very high frequencies. An excellent match between the new model and device simulation results has been observed even when the frequency is many times larger than the cutoff frequency.