Interface state densities, low frequency noise and electron mobility in surface channel In0.53Ga0.47As n-MOSFETs with a ZrO2 gate dielectric

This paper reports on an investigation of interface state densities, low frequency noise and electron mobility in surface channel In_0.53Ga_0.47As n-MOSFETs with a ZrO₂ gate dielectric. Interface state density values of D_it ∼ 5 × 10¹² cm⁻² eV⁻¹ were extracted using sub-threshold slope analysis and charge pumping technique. The same order of magnitude of trap density was found from low frequency noise measurements. A peak effective electron mobility of 1200 cm²/Vs has been achieved. For these surface channel In_0.53Ga_0.47As n-MOSFETs, it was found that η parameter, an empirical parameter used to calculate the effective electric field, was ∼0.55, and is to be comparable to the standard value found in Si device.     

Investigation of graded InxGa1−xP buffer by Raman scattering method

The compositional changes of In_xGa_1−xP graded buffer inserted between GaP substrate and subsequently grown In_0.36Ga_0.64P homojunction LED structure were investigated by Raman spectroscopy. The indium content of In_xGa_1−xP interlayers was increased in eight steps with thickness of 300 nm and constant compositional change Δx_In between the steps. The properties of In_xGa_1−xP graded buffer along the structure cross-section have been studied by Raman back scattering method and the changes in GaP LO and TO phonons were investigated. Raman shift of 13 cm⁻¹ in GaP-like LO₁ phonon was measured on beveled [100]surface for compositional change of In_xGa_1−xP layer in the range of 0<x_In<0.32. The measurements on the cleaved edge of the sample in [011] direction revealed a strong TO phonon at 366 cm⁻¹ and weak LO phonon peak at 405 cm⁻¹ in GaP substrate. By reaching the graded In_xGa_1−xP region the intensity of TO phonon decreases and appearance of considerable TO₁ phonon shift up to 350 cm⁻¹ for In content x_In=0.16 was observed. For upper graded layers with x_In from 0.16 to 0.24 the position of GaP-like TO₁ was constant and can be ascribed to relaxation of lattice mismatched thin In_xGa_1−xP graded upper layers in the structure.     

Effect of RuO2 electrode on laser-MBE prepared HfO2 gate dielectrics

In this paper, we report our recent study of the effect of RuO₂ as an alternative top electrode for pMOS devices to overcome the serious problems of polysilicon (poly-Si) gate depletion, high gate resistance and dopant penetration in the trend of down to 50 nm devices and beyond. The conductive oxide RuO₂, prepared by RF sputtering, was investigated as the gate electrode on the Laser MBE (LMBE) fabricated HfO₂ for pMOS devices. Structural, dielectric and electric properties were investigated. RuO₂/HfO₂/n-Si capacitors showed negligible flatband voltage shift (<10 mV), very strong breakdown strength (>10 MV cm⁻¹). Compared to the SiO₂ dielectric with the same EOT value, RuO₂/HfO₂/n-Si capacitors exhibited at least 4 orders of leakage current density reduction. The work function value of the RuO₂ top electrode was calculated to be about 5.0 eV by two methods, and the effective fixed oxide charge density was determined to be 3.3 × 10¹² cm⁻². All the results above indicate that RuO₂ is a promising alternative gate electrode for LMBE grown HfO₂ gate dielectrics.     

Comparative studies on electronic transport due to the reduced dimensionality at the heterojunctions of GaAs/A1xGa(1−x)As and GaxIn(1−x)As/InP systems at low temperatures

Comparative studies on ac/dc mobility due to the reduced dimensionality of spatially confined low dimensional systems, at the heterojunctions of GaAs/A1_xGa_(1−x)As and Ga_xIn_(1−x)As/InP forming quasi-two dimensional (Q2D) and quasi-one dimensional (Q1D) systems have been made. The effect of various low temperature nonphonon scattering mechanisms such as ionized impurity, alloy disorder scattering and surface roughness scattering mechanisms; and phonon scattering mechanisms such as acoustic phonon via deformation potential and piezoelectric scattering mechanisms on the systems has been studied. It is found that the surface roughness scattering mechanism dominates in Q2D system whereas acoustic phonon scattering mechanism dominates in Q1D system due to which the nature and magnitude of the temperature dependent dc/ac mobility curves shows significant variation. Whereas, it is observed that the confinement does not change the nature of the frequency dependent real and imaginary parts of ac mobility curves. However, the mobility is found to be enhanced with effective mass and also due to the confinement, i.e. the mobility for Q1D system is higher than that for Q2D system.     

High-mobility pentacene phototransistor with nanostructured SiO2 gate dielectric synthesized by sol-gel method

We have fabricated a pentacene based phototransistor by employing a modified nanostructured SiO₂ gate dielectric. The photosensing properties of the pentacene thin film transistor fabricated on n-Si substrate with nanostructured SiO₂ as gate dielectric have been investigated. The photocurrent of the transistor increases with an increase in illumination intensity. This suggests that the pentacene thin film transistor behaves as a phototransistor with p-channel characteristics. The photosensitivity and responsivity values of the transistor are 630.4 and 0.10 A/W, respectively at the off state under AM 1.5 light illumination. The field effect mobility of the pentacene phototransistor was also found to be 2.96 cm²/Vs. The nanostructured surface of the gate possibly is the cause of the high-mobility value of the phototransistor due to light scattering from the increased surface area.     

Pentacene thin-film transistors with sol-gel derived amorphous Ba0.6Sr0.4TiO3 gate dielectric

An amorphous Ba_0.6Sr_0.4TiO₃ (BST) film with the thickness of 200 nm was deposited on indium-tin-oxide (ITO)-coated glass substrate through sol-gel route and post-annealing at 500 °C. The dielectric constant of the BST film was determined to be 20.6 at 100 kHz by measuring the Ag/BST/ITO parallel plate capacitor, and no dielectric tunability was observed with the bias voltage varying from −5 to 5 V. The BST film shows a dense and uniform microstructure as well as a smooth surface with the root-mean-square (RMS) roughness of about 1.4 nm. The leakage current density was found to be 3.5 × 10⁻⁸ A/cm² at an applied voltage of −5 V. The transmittance of the BST/ITO/glass structure is more than 70% in the visible region. Pentacene based transistor using the as-prepared BST film as gate insulator exhibits a low threshold voltage of −1.3 V, the saturation field-effect mobility of 0.68 cm²/Vs, and the current on/off ratio of 3.6 × 10⁵. The results indicate that the sol-gel derived BST film is a promising high-k gate dielectric for large-area transparent organic transistor arrays on glass substrate.     

Silicon and selenium implantation and activation in In0.53Ga0.47As under low thermal budget conditions

Si and Se implantations have been systematically investigated in In_0.53Ga_0.47As. Different implant doses and various activation anneals with temperatures up to 700 °C have been examined. Raising Si implant dose from 1 × 10¹⁴ to 1 × 10¹⁵ cm⁻² was found to increase the active doping concentration by about a factor of two. As confirmed by Transmission Electron Microscopy (TEM) and electrical measurements, the rest of the implanted Si ions remain as defects in the crystal and degrade the mobility. It was also confirmed from Secondary Ion Mass Spectrometry (SIMS) that the Si diffusivity in InGaAs is negligible up to 700 °C implant activation anneal making Si a suitable option for the formation of shallow junctions in InGaAs. The activation efficiency, sheet resistance, carrier density and mobility data of 25 keV Se and Si implanted InGaAs layers are also presented under various activation anneal temperatures.     

Improving electrical characteristics of W/HfO2/In0.53Ga0.47As gate stacks by altering deposition techniques

The effects of controlling InGaAs substrate temperature during electron beam deposition of HfO₂ on electrical characteristics of W/HfO₂/n-In_0.53Ga_0.47As capacitors are investigated. It is found that by depositing a thin HfO₂ layer at the interface when substrate temperature is raised to 300 °C, frequency dispersion at depletion and accumulation conditions is reduced and interface state density is lowered regardless of the HfO₂ thickness. Cross-sectional transmission electron microscopy images have revealed that the formation of mesoscopic voids in the InGaAs substrate near the interface is suppressed with HfO₂deposition at 300 °C at the interface. A band diagram with an additional bulk trap energy level has been proposed to explain the frequency dispersion and conductance peaks at accumulation condition.     

Enhancement of low temperature electron mobility due to an electric field in an InGaAs/InAlAs double quantum well structure

The effect of external electric field F on multisubband electron mobility μ in an In_0.53Ga_0.47As/In_0.52Al₄₈As double quantum well structure is analyzed. We consider scatterings due to ionized impurities, interface roughness and alloy disorder to analyze μ. The variation of scattering mechanisms as a function of F for different structure parameters shows interesting results through intersubband interactions. For small well widths, the mobility is governed by interface roughness scattering. When two subbands are occupied, the effect of impurity scattering gets enhanced through intersubband interactions. Our results of enhancement in mobility as a function of F, can be utilized for low temperature devices.     

Investigation of atomic vapour deposited TiN/HfO2/SiO2 gate stacks for MOSFET devices

HfO₂ films were grown by atomic vapour deposition (AVD) on SiO₂/Si (1 0 0) substrates. The positive shift of the flat band voltage of the HfO₂ based metal-oxide-silicon (MOS) devices indicates the presence of negative fixed charges with a density of 5 × 10¹² cm⁻². The interface trap charge density of HfO₂/SiO₂ stacks can be reduced to 3 × 10¹¹ eV⁻¹ cm⁻² near mid gap, by forming gas annealing. The extracted work function of 4.7 eV preferred the use of TiN as metal gate for PMOS transistors. TiN/HfO₂/SiO₂ gate stacks were integrated into gate-last-formed MOSFET structures. The extracted maximum effective mobility of HfO₂ based PMOS transistors is 56 cm²/Vs.     

Structural and electrical characteristics of RF-sputtered HfO2 high-k based MOS capacitors

The HfO₂ high-k thin films have been deposited on p-type (1 0 0) silicon wafer using RF magnetron sputtering technique. The XRD, AFM and Ellipsometric characterizations have been performed for crystal structure, surface morphology and thickness measurements respectively. The monoclinic structured, smooth surface HfO₂ thin films with 9.45 nm thickness have been used for Al/HfO₂/p-Si metal-oxide-semiconductor (MOS) structures fabrication. The fabricated Al/HfO2/Si structure have been used for extracting electrical properties viz dielectric constant, EOT, barrier height, doping concentration and interface trap density through capacitance voltage and current-voltage measurements. The dielectric constant, EOT, barrier height, effective charge carriers, interface trap density and leakage current density are determined are 22.47, 1.64 nm, 1.28 eV, 0.93 × 10¹⁰, 9.25 × 10¹¹ cm⁻² eV⁻¹ and 9.12 × 10⁻⁶ A/cm² respectively for annealed HfO₂ thin films.     

Enhanced gate induced drain leakage current in HfO2 MOSFETs

The substrate current of high-κ dielectric MOSFETs has been studied using dc sweep and transient (down to 100 μs per I-V curve) electrical measurements. These measurements reveal trap-assisted substrate current components in addition to the traditional bell-shaped impact ionization current. By separating the transversal and lateral electric field contributions, the gate induced drain leakage (GIDL) is shown to dominate the substrate current at low gate biases. At high gate biases, tunneling of valence band electrons from the bulk to the gate dominates. The results show that the GIDL current is the result of band-to-band tunneling assisted by traps located at the HfO₂/SiO₂ interface and transition layer, and not the result of oxide charging.     

Self-aligned n-channel GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using HfO2 and silicon interface passivation layer: Post-metal annealing optimization

In this work, using Si interface passivation layer (IPL), we demonstrate n-MOSFET on p-type GaAs by varying physical-vapor-deposition (PVD) Si IPL thickness, S/D ion implantation condition, and different substrate doping concentration and post-metal annealing (PMA) condition. Using the optimized process, TaN/HfO₂/GaAs n-MOSFETs made on p-GaAs substrates exhibit good electrical characteristics, equivalent oxide thickness (EOT) (∼3.7 nm), frequency dispersion (∼8%) and high maximum mobility (420 cm²/V s) with high temperature PMA (950 °C, 1 min) and good inversion.     

A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

Annealing effects on electrical characteristics and reliability of MOS device with HfO₂ or Ti/HfO₂ high-k dielectric are studied in this work. For the sample with Ti/HfO₂ higher-k dielectric after a post-metallization annealing (PMA) at 600 °C, its equivalent oxide thickness value is 7.6 Å and the leakage density is about 4.5 × 10⁻² A/cm². As the PMA is above 700 °C, the electrical characteristics of MOS device would be severely degraded.     

Persistent photoconductivity and electron mobility in In0.52Al0.48As/In0.53Ga0.47As/In0.52Al0.48As/InP quantum-well structures

The influence of the width of the quantum well L and doping on the band structure, scattering, and electron mobility in nanoheterostructures with an isomorphic In_0.52Al_0.48As/In_0.53Ga_0.47As/In_0.52Al_0.48As quantum well grown on an InP substrate are investigated. The quantum and transport mobilities of electrons in the dimensionally quantized subbands are determined using Shubnikov-de Haas effect measurements. These mobilities are also calculated for the case of ionized-impurity scattering taking into account intersub-band electron transitions. It is shown that ionized-impurity scattering is the dominant mechanism of electron scattering. At temperatures T < 170 K, persistent photoconductivity is observed, which is explained by the spatial separation of photoexcited charge carriers.     

Composition and electrical characteristics of Al2O3-HfO2-HfTiO nanolaminates on Si

A dielectric constant of 27 was demonstrated in the as deposited state of a 5 nm thick, seven layer nanolaminate stack comprising Al₂O₃, HfO₂ and HfTiO. It reduces to an effective dielectric constant (k_eff) of ∼14 due to a ∼0.8 nm interfacial layer. This results in a quantum mechanical effective oxide thickness (EOT) of ∼1.15 nm. After annealing at 950 °C in an oxygen atmosphere k_eff reduces to ∼10 and EOT increases to 1.91 nm. A small leakage current density of about 8 × 10⁻⁷ and 1 × 10⁻⁴ A/cm², respectively at electric field 2 and 5 MV/cm and a breakdown electric field of about 11.5 MV/cm was achieved after annealing at 950 °C.     

High-mobility pentacene thin-film transistor by using LaxTa(1−x)Oy as gate dielectric

Pentacene organic thin-film transistors (OTFTs) using La_xTa_(1−x)O_y as gate dielectric with different La contents (x = 0.227, 0.562, 0.764, 0.883) have been fabricated and compared with those using Ta oxide or La oxide. The OTFT with La_0.764Ta_0.236O_y can achieve a carrier mobility of 1.21 cm² V⁻¹s⁻¹s, which is about 40 times and two times higher than those of the devices using Ta oxide and La oxide, respectively. As supported by XPS, AFM and noise measurement, the reasons lie in that La incorporation can suppress the formation of oxygen vacancies in Ta oxide, and Ta content can alleviate the hygroscopicity of La oxide, resulting in more passivated and smoother dielectric surface and thus larger pentacene grains, which lead to higher carrier mobility.     

Optimization of sub-0.1-μm offset Γ-shaped gate MHEMTs for millimeter-wave applications

We examine the effects of device scaling in both vertical and lateral dimensions for the metamorphic high electron mobility transistors (MHEMTs) on the DC and millimeter-wave electrical performances by using a hydrodynamic transport model. The well-calibrated hydrodynamic simulation for the sub-0.1-μm offset Γ-gate In_0.53Ga_0.47As/In_0.52Al_0.48As MHEMTs shows a reasonable agreement with the electrical characteristics measured from the fabricated 0.1 μm devices. We have calibrated all the parameters using the measurement data with various physical considerations to take into account the sophisticated carrier transport physics in sub-0.1-μm devices. Being simulated with these calibrated parameters, the optimum device performance is obtained at a source-drain spacing of 2 μm, a gate length of 0.05 μm, a barrier thickness of 10 nm and a channel thickness of 12 nm.     

A quantum mechanical mobility model for scaled NMOS transistors with ultra-thin high-K dielectrics and metal gate electrodes

A quantum mechanical model of electron mobility for scaled NMOS transistors with ultra-thin SiO₂/HfO₂ dielectrics (effective oxide thickness is less than 1 nm) and metal gate electrode is presented in this paper. The inversion layer carrier density is calculated quantum mechanically due to the consideration of high transverse electric field created in the transistor channel. The mobility model includes: (1) Coulomb scattering effect arising from the scattering centers at the semiconductor–dielectric interface, fixed charges in the high-K film and bulk impurities, and (2) surface roughness effect associated with the semiconductor–dielectric interface. The model predicts the electron mobility in MOS transistors will increase with continuous dielectric layer scaling and a fixed volume trap density assumption in high-K film. The Coulomb scattering mobility dependence on the interface trap density, fixed charges in the high-K film, interfacial oxide layer thickness and high-K film thickness is demonstrated in the paper.