A tool for the automatic generation and analysis of regular analog layout modules

This paper describes the characteristics of a new CAD tool that enables the creation of layout libraries of selected analog modules. This Analog Modules Generator (AMG) automatically creates multiple layout versions of two commonly used analog structures: the differential pair and arrays of series-connected or stacked devices, for the subsequent generation of layout libraries. Based on the number of devices and rows defined by the user for the layout implementation, the tool validates all possible implementations, which are later saved in a database. Additionally, an extraction process can be optionally executed over all the layout views saved in the database. The AMG generates several reports with all the characteristics of the implemented layouts, including area and parasitic components, facilitating further statistical processing. We describe the features and capabilities of the proposed AMG tool, and several test cases are presented. Results show that suitable layout implementations can be achieved by layout and circuit designers in a very reduced amount of time.     

Performance-driven circuit and layout co-optimization for deep-submicron analog circuits

The deep sub-micron (DSM) process nodes are increasingly marred by layout-dependent effects. The principal reason preventing layout synthesis during circuit design is the cost of edition, verification and extraction of the intermediate solutions repeatedly. This paper proposes a circuit and layout co-optimization scheme through a novel parasitic model-building scheme that exchanges information between the two flows. A placement-based parasitic estimation method to provide parasitic estimations to schematic optimization tools while retaining their efficiency. Extracted parasitics and simulated performance data are imparted into parasitic macro-devices and performance sensitivities. As proved by experimental results, the flexibility of the parasitic models bridges the efficiency and accuracy void between schematic and physical design optimization to ensure rapid DSM design closure.     

ALGA: Automated layout generator for analog CMOS circuits

A computer-aided design (CAD) system called ALGA for an analog circuit layout is presented. The main contribution of this paper is to construct a weight graph that represents the topological connectivity of a given analog circuit. By using the weight graph, some efficient techniques can be designed to avoid devices mismatch and place all devices according to the device size constraints. Moreover, an algorithm is presented to perform the device placement step and propose an effective approach to reduce noise coupling in the routing step. A design method has been implemented in several Complementary Metal Oxide Semiconductor (CMOS) analog circuits. It is seen that the proposed system can generate good analog circuit design.     

Reliability optimization of analog integrated circuits considering the trade-off between lifetime and area

The reliability of analog integrated circuits becomes a major concern for the semiconductor industry as technology continuously scales. Among the many contributing factors, manufacturing process induced parameter variations and lifetime operational-condition-dependent transistor aging are two major hurdles limiting the reliability of analog circuits. Process variations mainly influence the parametric yield value of the fresh circuits, while transistor aging due to physical effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), will cause another yield loss during circuit lifetime. In the past decades, the two issues were mainly studied separately by various communities, but analog designers nowadays need an accurate yet efficient method to analyze and optimize their circuits during the design phase, to ensure a more robust design tolerant of such joint effects.This paper proposes an efficient method for sizing of analog circuits for reliability. It is based on the analysis and optimization of the fresh worst-case distance value for each circuit performance, which can be used to characterize the robustness of circuits considering process variations and aging effects in terms of x-sigma. The fresh and aged sizing rules as well as the maximum area constraints are checked during the optimization. The trade-off between the circuit lifetime and the price we pay in terms of layout area is studied in detail. According to the result of this trade-off analysis, a longer circuit lifetime requires more total area to be spent in layout, and designers can ensure the circuit robustness with certain layout area consumption.     

Design principles for low-voltage low-power analog integrated circuits

In this paper it is argued that there are good reasons to choose current as the information-carrying quantity in the case of low-voltage low-power design constraints. This paper focuses on the influence of the transfer quality on that choice. To obtain power-efficient transfer quality, indirect feedback is shown to be a good alternative to traditional feedback techniques.     

模拟集成电路模块版图的生成系统

介绍了模拟集成电路模块版图的开发系统.系统用高效的过程化版图描述语言构造模拟模块,编译产生与工艺及应用无关的模块版图生成器.系统的网络识别和模块内布线功能自动完成模块网络的完全连通,基于优选的电气特性驱动版图生成,提高设计可靠性.该系统已辅助设计出多个高性能集成运算放大器、模拟开关等芯片版图.     

Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits

The integration of chips in the third dimension has been explored to address various physical and system level limitations currently undermining chip performance. In this paper, we present a comprehensive analysis of the electrical properties of through silicon vias and microconnects with an emphasis on single via characteristics as well as inter-TSV capacitive and inductive coupling in the presence of either a neighboring ground tap or a grounded substrate back plane. We also analyze the impact of technology scaling on TSV electrical parasitics, and investigate the power and delay trend in 3-D interstratum IO drivers with those of global wire in 2-D circuits over various technology nodes. We estimate the global wire length necessary to produce an equivalent 3-D IO delay, a metric useful in early stage design tools for 3D floorplanning that considers the electrical characteristics of 3D connections with TSVs and microconnects.     

A manufacturing process for analog and digital gallium arsenide integrated circuits

A process for manufacturing small-to-medium scale GaAs integrated circuits is described. Integrated FET's, diodes, resistors, thin-film capacitors, and inductors are used for monolithic integration of digital and analog circuits. Direct implantation of Si into > 10⁵Ω.cm resistivity substrates produces n-layers with ± 10-percent sheet resistance variation. A planar fabrication process featuring retained anneal cap (SiO2), proton isolation, recessed Mo-Au gates, silicon nitride passivation, and a dual-level metal system with polyimide intermetal dielectric is described. Automated on-wafer testing at frequencies up to 4 GHz is introduced, and a calculator-controlled frequency domain test system described. Circuit yields for six different circuit designs are reported, and process defect densities are inferred.     

数模混合集成电路版图设计的涨缩技术

文章介绍了在数模混合版图设计中,如何把版图不同模块的涨缩需求,用一种完善的自动化程序技术方案来实现,并且可以批处理所有需要涨缩的版图数据。     

Exploiting bounds optimization for the semi-formal verification of analog circuits

This paper proposes a semi-formal methodology for modeling and verification of analog circuits behavioral properties using multivariate optimization techniques. Analog circuit differential models are automatically extracted and their qualitative behavior is computed for interval-valued parameters, inputs and initial conditions. The method has the advantage of guaranteeing the rough enclosure of any possible dynamical behavior of analog circuits. The circuit behavioral properties are then verified on the generated transient response bounds. Experimental results show that the resulting state variable envelopes can be effectively employed for a sound verification of analog circuit properties, in an acceptable run-time.     

器件参数宏模型的精确建立及其在模拟集成电路性能建模与优化中的应用

Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presented to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical performance expressions, operating point driven （OPD） metamodels of MOSFETs are introduced to capture the circuit＇s characteristics precisely. In the algorithm of metamodel construction, radial basis functions are adopted to interpolate the scattered multivariate data obtained from a well tailored data sampling scheme designed for MOSFETs. The OPD metamodels can be used to automatically bias the circuit at a specific DC operating point. Analytical-based performance expressions composed by the OPD metamodels show obvious improvement for most small-signal performances compared with simulation-based models. Both operating-point variables and transistor dimensions can be optimized in our nesting-loop optimization formulation to maximize design flexibility. The method is successfully applied to a low-voltage low-power amplifier.     

Accurate metamodels of device parameters and their applications in performance modeling and optimization of analog integrated circuits

Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presnted to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical performance expressions, operating point driven (OPD) metamodels of MOSFETs are introduced to capture the circuit's characteristics precisely. In the algorithm of metamodel construction, radial basis functions are adopted to interpolate the scattered multivariate data obtained from a well tailored data sampling scheme designed for MOSFETs.The OPD metamodels can be used to automatically bias the circuit at a specific DC operating point. Analytical-based performance expressions composed by the OPD metamodels show obvious improvement for most small-signal performances compared with simulation-based models. Both operating-point variables and transistor dimensions can be optimized in our nesting-loop optimization formulation to maximize design flexibility. The method is successfully applied to a low-voltage low-power amplifier.     

Current-mode CMOS integrated circuits for analog computation and signal processing: A tutorial

This paper presents an overview of design techniques for a broad range of current-mode analog integrated circuits implemented in CMOS technology at a tutorial level. Primarily, emphasis is placed on circuit configurations, first-order analysis, and approximate design equations for analog integrated circuits operating in current domain for signal computation and processing applications.     

Automatic generation of test infrastructures for analog integrated circuits by controllability and observability co-optimization

This paper presents a method to address the automatic testing of analog ICs for catastrophic defects. Based on Design-for-Testability building blocks offering extra controllability and extra observability, a test infrastructure is generated for a targeted circuit. The selection of the extra blocks and their insertion into the circuit is done automatically by a workflow based on DC simulations and optimization algorithms. Adopting a defect-oriented methodology, this approach maximizes the fault coverage while minimizing the silicon area overhead and test time. The proposed method is applied to two industrial circuits in order to generate optimal test infrastructures combining controllability and observability. These case studies show that, with a silicon area overhead of less than 10%, a fault coverage of 94.1% can be reached.     

Automated topology synthesis of analog and RF integrated circuits: A survey

The puzzle of automatically synthesizing analog and radio frequency (RF) circuit topology has not yet been offered with an industrially-acceptable solution although endeavors still continue to seek a conquest in this area. This survey provides a comprehensive study of the techniques utilized for this purpose. The existing methods are analyzed from four different viewpoints, namely, structural view, conceptual view, implementation view, and application view. Different schemes are perused with their advantages and drawbacks discussed in the context of balanced performance between configuration-space coverage and search efficiency. Some prospective trends are pointed out to shed light on the upcoming research activities.     

On the optimal design of switched-capacitor filter circuits for analog and mixed-signal integrated circuit realization

This contribution describes developments in the use of numerical optimization techniques as part of a package whose function is to generate silicon-level layout for general analog functional modules from high-level specifications. The investigation is using switched-capacitor filters as a case study that is representative, in terms of its associated physical layout problems, of many classes of analog circuits.     

A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards

Progress in analog circuit testing has been hindered by the lack of structured design-for-testability methodologies. With the increasing complexity of analog/mixed-signal circuits, test program development time is now a major obstacle in achieving shorttime-to-market, while production testing cost is a prominent factor in total production cost. TheAnalog Autonomous Test is a structured design-for-testability scheme for analog circuits. Originally developed for testing analog circuits at chip level, AAT extends naturally to cover testing of mixedsignal integrated circuits mounted on printed circuit boards. With the addition of an analog test bus to PCBs, testability for analog components (bothcore circuits andglue circuits) can be improved, in a manner similar to that achieved for digital boards by the IEEE 1149.1 boundary scan scheme. Details on the implementation of thisAnalog Autonomous Test Bus, both at chip level and board level, are presented here. Its limitations and potential applications are also discussed.     

A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards

Progress in analog circuit testing has been hindered by the lack of structured design-for-testability methodologies. With the increasing complexity of analog/mixed-signal circuits, test program development time is now a major obstacle in achieving shorttime-to-market, while production testing cost is a prominent factor in total production cost. TheAnalog Autonomous Test is a structured design-for-testability scheme for analog circuits. Originally developed for testing analog circuits at chip level, AAT extends naturally to cover testing of mixedsignal integrated circuits mounted on printed circuit boards. With the addition of an analog test bus to PCBs, testability for analog components (bothcore circuits andglue circuits) can be improved, in a manner similar to that achieved for digital boards by the IEEE 1149.1 boundary scan scheme. Details on the implementation of thisAnalog Autonomous Test Bus, both at chip level and board level, are presented here. Its limitations and potential applications are also discussed.