Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing

Modern advances in reconfigurable technologies are allowing analog circuit designers to benefit from the computational flexibility provided by large-scale field-programmable analog arrays. With the component density of these devices, small analog circuits, as well as larger analog systems, can be synthesized and tested in a shorter time and at a lower cost, compared with the full design cycle. However, automated development platforms and computer-aided design tools for these devices are far fewer than the physical synthesis tools for their digital counterparts. One of the major reasons for this is the considerably higher impact of interconnect parasitics on circuit functionality in the analog domain; therefore, performance optimization must be recognized as an indispensable step of the analog physical synthesis flow. Our goal in this brief is to present a physical synthesis framework with an optimization core and an integrated simulation environment for verification of the synthesis results. Although SPICE has been used as the simulation tool for our experiments, there is no dependency on a particular circuit simulator. Our synthesis tool currently accepts SPICE netlists as input and gives priority to user-specified metrics when optimizing the synthesized circuit performance. Experimental results demonstrate the effectiveness of our approach.     

Tools for the computer-aided design of multigigahertzsuperconducting digital circuits

The realization of large integrated circuits depends upon the application of computer-aided design (CAD) tools. This paper summarizes the results of a survey of CAD tools targeting superconducting digital electronics. Five categories of tools: circuit simulators, circuit optimizers, layout tools, inductance estimators, and logic simulators are discussed in detail. Within each category, a comparison of several currently available CAD tools is presented, and a tool which has been adapted for use or developed at the University of Rochester is discussed in greater detail. In addition, tools for timing analysis as well as integrated design environments that permit the effective data interchange among various tools and support libraries of design models are discussed. Future tools for timing optimization, automated logic synthesis, and automated layout synthesis are shown to be necessary for the design of superconducting circuits at the very large scale of integration (VLSI) level of integration. Trends regarding changes in the requirements for effective CAD tools are discussed, and expected improvements to existing tools and features of new tools currently under development are presented     

ARIADNE: A constraint-based approach to computer-aided synthesis and modeling of Analog integrated circuits

The ARIADNE approach to computer-aided synthesis and modeling of analog circuits is presented. It is a mathematical approach based on the use of equations. Equations are regarded as constraints on a circuit's design space and analog circuit design is modeled as a constraint satisfaction problem. To generate and efficiently satisfy constraints, advanced computational techniques such as constraint propagation, interval propagation, symbolic simulation, and qualitative simulation are applied. These techniques cover design problems such as topology construction, modeling, nominal analysis, tolerance analysis, sizing and optimization of analog circuits. The advantage of this approach is the clear separation of design knowledge from design procedures. Design knowledge is modeled in declarative equation-based models (DEBMs). Design procedures are implemented into general applicable CAD tools. The ARIADNE approach closely matches the reasoning style applied by experienced designers. The integration of synthesis and modeling into one frame and the clear separation of design knowledge from design procedures eases the process of extending the synthesis system with new circuit topologies, turning it into an open design system. This system can be used by both inexperienced and experienced designers in either interactive or automated mode.     

New advances of high-level synthesis for efficient and reliable hardware design

The spectacular CMOS technology scaling will continue to evolve and dominate the semiconductor industry. This will lead to tens of billions of transistors integrated on a single chip by the year 2020. However, one significant problem is that the design productivity for complex designs has been lagging behind. In addition to several proposed techniques for dealing with the widening productivity gap, e.g., IP reuse and integration, virtual platform modeling, formal verification and others, high-level synthesis (HLS) has been touted as an important solution as it can significantly reduce the number of man-hours required for a design by raising the level of design abstraction. However, existing HLS solutions have limitations, and studies show that the design quality of HLS can be inferior compared to that of manual RTL design. In this paper, we will present a set of new techniques developed recently to drastically improve HLS solutions, which not only improve the traditional design metrics such as circuit performance and energy efficiency but also emerging metrics such as hardware security and robustness. We will also discuss how HLS can collaborate with other techniques to provide a holistic design methodology that can enable the delivery of high-quality designs with much less design cost and much faster time-to-market.     

Causal reasoning mining approach to analog circuit verification

Functional errors in analog portion of mixed signal circuits become more severe and improvements in verification methods are increasingly important. Current verification methods fall into two categories, simulation-based verification and formal verification (Barke et al. [1]), focusing on verifying analog circuit function/performance. This paper proposes a novel approach verifying analog circuit design using causal reasoning. Causal reasoning is the inductive reasoning process to create a new design. The flow begins with mining the causal reasoning steps (design plan) that produced the circuit, including starting ideas, design step sequence, and their justifications (Jiao et al., 2015 [2]). Then, topological features corresponding to the starting ideas and design step sequence are verified individually by replacing the related devices with ideal behavior model. Performance is evaluated through Cadence Spectre simulation. Comparison with new circuit performance reveals incorrect functional issues and/or performance potentials for improvement. They are negative causes of certain starting ideas or design steps, which might have been omitted during the design process. The paper discusses three operational amplifier designs realized in 0.2-μm CMOS technology to illustrate the verification approach.     

Novel low-voltage ultra-low-power DVCC based on floating-gate folded cascode OTA

In this paper a novel low-voltage ultra-low-power differential voltage current conveyor (DVCC) based on folded cascode operational transconductance amplifier OTA with only one differential pairs floating-gate MOS transistor (FG-MOST) is presented. The main features of the proposed conveyor are: design simplicity; rail-to-rail input voltage swing capability at a low supply voltage of ±0.5 V; and ultra-low-power consumption of mere 10 μW. Thanks to these features, the proposed circuit could be successfully employed in a wide range of low-voltage ultra-low-power analog signal processing applications. Implementation of new multifunction frequency filter based on the proposed FG-DVCC is presented in this paper to take the advantages of the properties of the proposed circuit. PSpice simulation results using 0.18 μm CMOS technology are included as well to validate the functionality of the proposed circuit.     

Expediting analog design retargeting by design knowledge re-use and circuit synthesis: a practical example on a Delta-Sigma modulator

In the past decade or two, due to constant and rapid technology changes, analog design re-use or design retargeting to newer technologies has been brought to the table in order to expedite the design process and improve time-to-market. If properly conducted, analog design retargeting could significantly cut down design cycle compared to designs starting from the scratch. In this article, we present an empirical and general method for efficient analog design retargeting by design knowledge re-use and circuit synthesis (CS). The method first identifies circuit blocks that compose the source system and extracts the performance parameter specifications of each circuit block. Then, for each circuit block, it scales the values of design variables (DV) from the source design to derive an initial design in the target technology. Depending on the performance of this initial target design, a design space is defined for synthesis. Subsequently, each circuit block is automatically synthesised using state-of-art analog synthesis tools based on a combination of global and local optimisation techniques to achieve comparable performance specifications to those extracted from the source system. Finally, the overall system is composed of those synthesised circuit blocks in the target technology. We illustrate the method using a practical example of a complex Delta-Sigma modulator (DSM) circuit.     

A novel high-throughput method for table look-up based analog design automation

Analog circuit synthesis ofen requires repeated evaluations of circuit under design to reach the final design goals. Circuit simulations using SPICE can provide accurate assessment of circuit performance. Spice simulations are costly and incur significant overhead. A faster transistor-level evaluation is needed to provide higher throughput for synthesis applications. Further, miniaturization of FET’s has added physical effects into SPICE models, which complicated their equations with every generation. That complication has forced analog synthesis tool developers and circuit designers alike to perform circuit evaluations using SPICE.Analog circuit design tools largely failed in their declared goal, to take over circuit optimization tasks from human designers mainly due to over simplications using custom-developed equations for evaluating circuit performance. Since it is more and more difficult to accurately capture transistor behavior with each new generation of silicon technology, a more practical approach to analog design automation is to keep human engineers at the center of the design flow by providing them with as much needed decision-supporting data as quickly as possible. Mapping the trade-off landscape of a topology with respect to design specifications, for example, can save designers trial and error time. This approach to analog design automation requires less accuracy from the simulation sign-off tools, such as SPICE. However, it demands much faster response for circuit performance evaluations with sufficient accuracy.In this paper, a new solution to both calculation overheads and model complexity is proposed. The proposed fast evaluation method uses a novel look-up table (LUT) algorithm to extract circuit information from complex physics-based transistor models used by SPICE. The model makes use of contemporary memory space, by replacing equations with look-up tables in addition to advanced interpolation methods. The achieved improvement is over 100× throughput and complete decoupling from physical phenomena compared to SPICE run-time, in exchange for few gigabytes of data per device. Examples are shown for the effectiveness of replacing SPICE with our model in a transistor sizing flow, while keeping 99% of the samples inside the 5% error range on 180 nm and 40 nm CMOS processes. The proposed solution is not intended to replace sign-off quality tools, such as SPICE. Rather, it is intended to be used as a fast performance evaluator in analog design automation flows.     

Review: Machine learning techniques in analog/RF integrated circuit design,synthesis, layout,and test

Rapid developments in semiconductor technology have substantially increased the computational capability of computers. As a result of this and recent developments in theory, machine learning (ML) techniques have become attractive in many new applications. This trend has also inspired researchers working on integrated circuit (IC) design and optimization. ML-based design approaches have gained importance to challenge/aid conventional design methods since they can be employed at different design levels, from modeling to test, to learn any nonlinear input-output relationship of any analog and radio frequency (RF) device or circuit; thus, providing fast and accurate responses to the task that they have learned. Furthermore, employment of ML techniques in analog/RF electronic design automation (EDA) tools boosts the performance of such tools. In this paper, we summarize the recent research and present a comprehensive review on ML techniques for analog/RF circuit modeling, design, synthesis, layout, and test.     

Automated design of switched-current filters

This paper describes the automated design and synthesis of switched-current (SI) filters using SCADS, a flexible CAD system integrated in a major VLSI design suite. With this system, the nonspecialist can produce high performance analog filters suitable for mixed signal CMOS IC's fabricated using only standard digital processes. To achieve high levels of performance on silicon, filter designs are realized using an enhanced differential circuit technique (S²I) in its integrators and sample-and-hold cells. The design system is described in terms of the embedded circuits, its integrated tool set, the filter design flow and the engineering procedures for ensuring reliable circuit operation. Examples of high performance video frequency filters are presented, each generated automatically by SCADS within one day. Fabricated in a 0.8 μm standard CMOS process, they demonstrate state-of-the-art performance     

Behavioral simulation for analog system design verification

Synthesis of analog circuits is an emergent field, with efforts focused at the cell level. With the growing trend of mixed ASIC designs that contain significant portions of analog sections, compatible design methodologies in the analog domain are necessary to complement those in the digital domain. The synthesis process requires an associated verification process to ensure that the designs meet performance specifications at the onset. In this paper we present a behavioral simulation methodology for analog system design verification and design space exploration. The verification task integrates with analog system-level synthesis for an integrated synthesis-verification process that avoids expensive post synthesis simulation by invoking external simulators. Thus rapid redesign at the architectural level can be undertaken for design parameter variation and during optimization. The verification suite is composed of a repertoire of analysis modes that include time and frequency domain analysis, sensitivity analysis and distortion analysis. Besides verification of design specifications, these analysis modes are also used to generate metrics for comparison of various architectural choices that could realize a given set of specifications. The implementation is in the form of a behavioral simulator, ARCHSIM     

Statistical computer-aided design for microwave circuits

A useful methodology for microwave circuit design is presented. A statistical technique known as Design of Experiments is used in conjunction with computer-aided design (CAD) tools to obtain simple mathematical expressions for circuit responses. The response models can then be used to quantify response trade-offs, optimize designs, and minimize circuit variations. The use of this methodology puts the designer's intelligence back into design optimization while making “designing for circuit manufacturability” a more systematic and straightforward process. The method improves the design process, circuit performance, and manufacturability. Two design examples are presented in context to the new design methodology     

Analog integrated filter compilation

A review of the progress in automated design of analog integrated filters is presented. Such tools are ahead of other analog circuit automation in terms of the acceptance by designers and practical applicability. A survey of the present-day commercial and academic systems is made and the range of facilities available is compared. The problems faced in the design of this type of software are typical of the problems of analog design systems in general; lack of openness for introduction of new design knowledge, difficulties of dealing simultaneously with expert and novice users, poor integration in design environments, and user-interface problems. The structure of a typical system is studied and the computer methods used within are discussed with regard to such issues as speed, flexibility, and ease-of-use. Some future directions for analog filter compilers are proposed.     

Computer-aided design of analog and mixed-signal integratedcircuits

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved     

State of the art in the analog CMOS circuit design

This paper is not intended to cover CMOS analog circuit design exhaustively. Yet, it describes how much CMOS technology has been involved in analog circuit design despite the general opinion that CMOS is only suited for digital design. After some developments in the CMOS technology have been discussed, the analog building block scene is covered. The analog building blocks can roughly be divided into two subgroups: the switched-capacitor and the non-switched-capacitor building blocks. Following this subdivision different approaches are briefly looked at. Several tables conclude this review and indicate that new analog developments in CMOS circuit design are still to be expected. Next, the CAD tool development for analog CMOS is discussed, showing that there is still a lot to be done in the field of automated analog design. In conclusion, some ideas concerning analog CAD or, concerning CAD in a more general sense are described.     

A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits

Applying symbolic techniques for analog circuit analysis is a traditional research subject, which has lasted for over half a century. The past decade has witnessed a significant advancement of the symbolic techniques developed specifically for large analog integrated circuits. The key methodology introduced is a data structure called binary decision diagram (BDD) which was established originally for logic design and verification. The application of the BDD technique for analog circuit analysis has the following features: (1) It is a compact data structure so that data redundancy in symbolic analysis can be eliminated. (2) It provides a mechanism for implicit enumeration method so that exhaustive enumeration commonly performed in symbolic analysis can be avoided. (3) Numerical evaluation on a BDD can be made extremely efficient, making it an excellent means for repetitive analysis. More advanced features are yet to be explored. This survey brings together the significant research results published in the past decade and provides a tutorial overview on the basic principles of applying BDD to analog circuit analysis. Some new directions that are potentially valuable for developing future analog design automation tools are discussed and a design example is given to illustrate the application of symbolic techniques.     

Toward a unified and automated design methodology for multi-domain dynamic systems using bond graphs and genetic programming

This paper suggests a unified and automated design methodology for synthesizing designs for multi-domain systems, such as mechatronic systems. A multi-domain dynamic system includes a mixture of electrical, mechanical, hydraulic, pneumatic, and/or thermal components, making it difficult use a single design tool to design a system to meet specified performance goals. The multi-domain design approach is not only efficient for mixed-domain problems, but is also useful for addressing separate single-domain design problems with a single tool. Bond graphs (BGs) are domain independent, allow free composition, and are efficient for classification and analysis of models, allowing rapid determination of various types of acceptability or feasibility of candidate designs. This can sharply reduce the time needed for analysis of designs that are infeasible or otherwise unattractive. Genetic programming is well recognized as a powerful tool for open-ended search. The combination of these two powerful methods is therefore an appropriate target for a better system for synthesis of complex multi-domain systems. The approach described here will evolve new designs (represented as BGs) with ever-improving performance, in an iterative loop of synthesis, analysis, and feedback to the synthesis process. The suggested design methodology has been applied here to three design examples. The first is a domain-independent eigenvalue placement design problem that is tested for some sample target sets of eigenvalues. The second is in the electrical domain––design of analog filters to achieve specified performance over a given frequency range. The third is in the electromechanical domain––redesign of a printer drive system to obtain desirable steady-state position of a rotational load.