Design of 3.1–10.6 GHz ultra-wideband CMOS low noise amplifier with current reuse technique

A new low complexity ultra-wideband 3.1–10.6 GHz low noise amplifier (LNA), designed in a chartered 0.18 μm RFCMOS technology, is presented in this paper. The ultra-wideband LNA only consists of two simple amplifiers with an inter-stage inductor connected. The first stage utilizing a resistive current reuse and dual inductive degeneration techniques is used to attain a wideband input matching and low noise figure. A common source amplifier with inductive peaking technique as the second stage achieves high flat gain and wide the −3 dB bandwidth of the overall amplifier simultaneously. The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB, a high reverse isolation of −45 dB and a good input/output return losses are better than −10 dB in the frequency range of 3.1–10.6 GHz. An excellent noise figure (NF) of 2.8–4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V. An input-referred third-order intercept point (IIP3) is −7.1 dBm at 6 GHz. The chip area including testing pads is only 0.8 mm × 0.9 mm.     

Design and analysis of a flat gain and linear low noise amplifier using modified current reused structure with feedforward structure

In this paper, a Low Noise Amplifier (LNA) with the current reused topology is proposed for wideband applications. To increase input impedance matching common source with inductive degeneration and RC shunt feedback structure is used. To extend the bandwidth, inductive series peaking technique is utilized. In the next stage, two parallel structure is hired to have a high voltage gain with low power consumption in addition to improve linearity. Also, by using the self-forward-body-bias (SFBB) technique, supply voltage is reduced and as a result power consumption is decreased further. The proposed LNA exhibits the high and flat gain of 14.7–15.4 ​dB, input return loss of less than −11 ​dB and noise figure range of 2.3–4.4 ​dB from 1 ​GHz up to 8 ​GHz. It consumes 5.4 ​mW from a 1.2 ​V power supply. The achieved IIP3 range for the proposed LNA is 0 ​dBm up to +2.7 ​dBm. The proposed LNA occupies 0.45 ​mm² in 0.18-μm CMOS technology.     

低功耗宽带CMOS低噪声放大器

本文实现了一款低功耗的宽带低噪声放大器(LNA)。该低噪放由输入级、中间级和输出级组成。由于每一级都采用了电流复用技术,显著地降低了功耗。输入级通过电阻、电容负反馈和并联电感,实现了良好的输入匹配。引入电感抵消了电容产生的虚部阻抗并且抵消了电容产生的极点。与电阻负反馈放大器相比,本文提出的结构提高了增益。中间级通过并联电感引入零点,采用低Q值拓展带宽。输出级是源级跟随器,提供了良好的输出匹配。经0.18 μm TSMC CMOS工艺仿真验证,在3 V的电源电压下,功耗仅为4.89 mW。另外在1~4.5 GHz频带范围内,电压增益(S21)为14.8±0.4 dB,噪声系数(NF)介于3.1~4.2 dB之间,输入、输出反射系数(S11、S22)均小于-10 dB。在4GHz时,输入三阶交调点(IIP3)达到-11dBm。     

A SiGe LC-ladder low noise amplifier with base resistance match,gain and noise flatness for UWB applications

This study presents a 3.1–10.6 GHz ultra-wideband low noise amplifier (UWB LNA) in 0.18 µm SiGe HBT technology. To achieve a good input match, parasitic base resistance in a bipolar transistor and an LC-ladder filter are included into calculations with the common-emitter topology using shunt–shunt capacitive feedback. Both high and flat power gain (S₂₁) and low and flat noise figure (NF) are achieved by adjusting the pole and zero in amplifying stage and quality factors of the fourth-order input network. Design equations for performances such as gain, noise figure and linearity IIP3 are derived especially on gain flatness and noise flatness. LNA dissipates 33 mW power and achieves S₂₁ of 20.65+0.7 dB, NF of 2.79+0.2 dB over the band of 3.1–10.6 GHz. The simulated input third-order intermodulation point (IIP3) is −17 dBm at 10 GHz.     

Sub-mA single ended CMOS low noise amplifier with 2.41 dB noise figure

This paper presents a single ended low noise amplifier (LNA) using 0.18 μm CMOS process packed and tested on a printed circuit board. The LNA is powered at 1.0 V supply and drains 0.95 mA only. The LNA provides a forward gain of 11.91 dB with a noise figure of only 2.41 dB operating in the 0.9 GHz band. The measured value of IIP3 is 0.7 dBm and of P1dB is −12 dBm. Zhang Liang is currently with Cyrips, Singapore. Ram Singh Rana was born in Delhi (India). Having primary education in Bijepur, Dwarahat(India), he received the B.Tech. (hons.) degree in Computer Engineering from G.B. Pant University, Pantnagar, India in 1988 and the Ph.D degree from the Indian Institute of Techonology (IIT), Delhi, India in 1996. He worked for his Ph.D in the Centre for Applied Research in Electronics, IIT Delhi in close interaction with the Semiconductor Complex Limited, Mohali, India. He was with ESPL, Mohali(India) in 1988 for a very short period and then served IIT Delhi as Senior Research Associate (88-90) and Senior Scientific Officer (90-95) where his main contributions were on CMOS analog IC design in subthreshold operation. He was a Lecturer in the Kumaon Engg. College, Dwarahat (India) before serving the IIT Roorkee (Formerly Univ. of Roorkee) in 1998 as assistant Professor. In 1999, he was a Manager (Engineering), Semiconductor Product Sector of the Motorola, Noida, India. Since joining the Institute of Microelectronics, Singapore in 2000, he worked mostly on RFICs, Fractional-N PLLs, ADCs. During 2001-2004, he worked there as IC Design Research and Training Program Manager. Currently, he is serving the institute as Senior Research Engineer in CMOS IC design (below 1V) for biomedical and bio-sensors. His current interests include design and consultancy for CMOS ICs/systems for the biomedical and high speed communication applications. Dr. Rana received Young Teacher Career Award from the All India Council for Technical Education in 1997. He was an Adjunct Asstt. Professor with the National University of Singapore (NUS), Singapore in 2004. He is sole inventor of two US granted patents and has filed several other patents. He has authored/co-authored about 40 publications. He has been reviewer for several IEEE journals and conference papers. Dr Rana is a senior member of IEEE and a member of Graduate Program in BioEngineering, NUS Singapore. He has chaired /co-chaired sessions in many international conferences. Zhang Liang was born in China in June 1978. He received the Bachelor degree and the Master degree in Electrical Engineering from the Xi’an JiaoTong University, Xi’an, China, in 2000 and 2003 respectively. Since 2003, he has been a postgraduate student in the Electrical and Computer Engineering department, National University of Singapore(NUS), Singapore and has successfully completed M.Engg degree program of the NUS. He is currently working on RFICs as a design engineer in Cyrips, Singapore. His design and research interests include integrated circuit design for communications. He has authored/co-authored several publications of international standard. Hari K Garg obtained his BTech degree in EE from IITDelhi in 1981. Subsequently, he obtained his MEng & PhD degrees from Concordia University in 1983 & 1985, and MBA from Syracuse University in 1985. He was a faculty member at Syracuse University from 1985 till 1995. He has been with the National University of Singapore since 1995 till present with the exception of 1998-1999 when he was with Philips. Hari’s research interests are in the area of digital signal/image processing, wireless communications, coding theory and digital watermarking. He has published extensively on these and related topics. He is also founder of several companies in the space of mobile telephony. In his spare time, Hari enjoys singing and a good game of Squash.     

A CMOS low noise amplifier with integrated front-side micromachined inductor

The paper presents the design and characterization of a low noise amplifier (LNA) in a 0.18 μm CMOS process with a novel micromachined integrated stacked inductor. The inductor is released from the silicon substrate by a low-cost CMOS compatible dry front-side micromachining process that enables higher inductor quality factor and self-resonance frequency. The post-processed micromachined inductor is used in the matching network of a single stage cascode 4 GHz LNA to improve its RF performance. This study compares performance of the fabricated LNA prior to and after post-processing of the inductor. The measurement results show a 0.5 dB improvement in the minimum noise figure and a 1 dB increase in gain, while good input matching is maintained. These results show that the novel low-cost CMOS compatible front-side dry micromachining process reported here significantly improves performance and is very promising for System-On-Chip (SOC) applications.     

一种新型900MHz CMOS低噪声放大器的设计

对两种低噪声放大器(LNA)的构架进行了比较,详细推导了共源LNA的噪声系数与输入晶体管栅宽的关系及优化方法,设计了一种采用0.6 μ m标准CMOS工艺,工作于900MHz的新型差分低噪声放大器.在900MHz时,噪声系数为1.5 dB的情况下可提供22.5 dB的功率增益,-3dB带宽为1 50MHz,S11达到-38dB,消耗的电流为5mA.     

Design of low power CMOS ultra wide band low noise amplifier using noise canceling technique

This paper presents a design of a low power CMOS ultra-wideband (UWB) low noise amplifier (LNA) using a noise canceling technique with the TSMC 0.18 μm RF CMOS process. The proposed UWB LNA employs a current-reused structure to decrease the total power consumption instead of using a cascade stage. This structure spends the same DC current for operating two transistors simultaneously. The stagger-tuning technique, which was reported to achieve gain flatness in the required frequency, was adopted to have low and high resonance frequency points over the entire bandwidth from 3.1 to 10.6 GHz. The resonance points were set in 3 GHz and 10 GHz to provide enough gain flatness and return loss. In addition, the noise canceling technique was used to cancel the dominant noise source, which is generated by the first transistor. The simulation results show a flat gain (S₂₁>10 dB) with a good input impedance matching less than –10 dB and a minimum noise figure of 2.9 dB over the entire band. The proposed UWB LNA consumed 15.2 mW from a 1.8 V power supply.     

A low noise amplifier with automatically Q-tuned notch filter

A low noise amplifier with automatically Q-tuned notch filter is proposed. The automatic Q tuning is achieved by an analog-digital mixed circuit, in which the successive approximation register algorithm is used to search for the appropriate current value through the resonator so that the losses of the resonator are perfectly cancelled to get a deep notch.     

CMOS planar spiral inductor modeling and low noise amplifier design

During this study, various narrowband single-ended inductive source degenerated Low Noise Amplifiers (LNAs) for GSM and S-band low earth orbit (LEO) space applications have been designed, simulated and compared using Mietec CMOS 0.7 μm process and the Cadence/BSIM3v3. To get more realistic results, parasitic effects due to layout have been calculated and added to the simulations. Also, considering the inductive source degenerative topology, most of the attention is given on the modeling of planar spiral inductor by lumped element circuits. Moreover to decrease the substrate effects, the inductors have been surrounded by grounded guard rings and have patterned ground shield (PGS) under them. The simulation results of LNA including the parasitic effects indicate a forward gain of 9 dB with noise figure of 4.5 dB while drawing 18 mW from+3 V supply at 2210 MHz. The area occupied is 1.8 mm×1.6 mm with pads, 1.3 mm×1.2 mm without pads.     

程控增益低噪声宽带直流放大器的设计

介绍了程控增益低噪声宽带直流放大器的设计原理及流程。采用低噪声增益可程控集成运算放大器AD603和高频三极管2N2219和2N2905等器件设计了程控增益低噪声宽带直流放大器,实现了输入电压有效值小于10mV,输出信号有效值最大可达10V,通频带为0～8MHz,增益可在0～50dB之间5dB的步进进行控制,最高增益达到53dB,且宽带内增益起伏远小于1dB的两级宽带直流低噪声放大器的设计。     

运用级间并联电感的级联CMOS低噪声放大器的优化设计

本文介绍了一种运用级间并联电感优化CMOS低噪声放大器的设计方法。传统的级联低噪声放大器可以从两级级联放大器的角度出发,视为共源级和共栅级的级联,由于共栅极的极好的隔离性,两级放大器可以分别设计。理论分析表明：在共源极和共栅极间引入级间匹配网络,即并联一个电感加强两极间的耦合,可以有效的改善低噪放的功率增益和噪声性能。文章最后用一个工作于5GHz的低噪放的设计实例,验证了理论分析的正确性。     

A highly linear CMOS low noise amplifier for K-band applications

This paper describes a highly linear low noise amplifier (LNA) for K-band applications in a 0.18 µm RF CMOS technology. The core of the circuit is a two-stage LNA consisting of a common-source and a cascode stage. By adopting an improved post-linearisation technique at the common-source transistor of the second stage, more than 5 dB improvement in IIP3 is achieved with a minor effect on noise figure and input matching. The circuit level analysis and simulation results are presented to demonstrate the effectiveness of the proposed technique.     

A 2.4-GHz low power dual gain low noise amplifier for ZigBee

e figure (NF) is 2.3-3 dB in the whole 2.45-GHz ISM band. The measured 1-dB compression point, IIP3 and IIP2 is -9, 1 and 33 dBm, respectively. The DGLNA consumes 2 mA of current from a 1.8 V power supply.     

用于ZigBee的2.4GHz低功耗双增益低噪声放大器

This paper presents a fully differential dual gain low noise amplifier（DGLNA） for low power 2.45-GHz ZigBee/IEEE 802.15.4 applications.The effect of input parasitics on the inductively degenerated cascode LNA is analyzed.Circuit design details within the guidelines of the analysis are presented.The chip was implemented in SMIC 0.18-μm 1P6M RF/mixed signal CMOS process.The DGLNA achieves a maximum gain of 8 dB and a minimum gain of 1 dB with good input return loss.In high gain mode, the measured noise figure（NF） is 2.3-3 dB in the whole 2.45-GHz ISM band.The measured 1-dB compression point, IIP3 and IIP2 is-9, 1 and 33 dBm, respectively.The DGLNA consumes 2 mA of current from a 1.8 V power supply.     

一种用于数字电视调谐器的宽带CMOS无电感噪声抵消低噪声放大器

A wideband inductorless low noise amplifier for digital TV tuner applications is presented. The proposed LNA scheme uses a composite NMOS/PMOS cross-coupled transistor pair to provide partial cancellation of noise generated by the input transistors. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed LNA achieves 12.2-15.2 dB voltage gain from 300 to 900 MHz, the noise figure is below 3.1 dB and has a minimum value of 2.3 dB, and the best input-referred 1-dB compression point(IP1dB) is - 17 dBm at 900 MHz. The core consumes 7 mA current with a supply voltage of 1.8 V and occupies an area of 0.5×0.35 mm2.     

一种宽带低噪声放大器的设计

随着无线通信的迅猛发展,提高了对射频技术的要求。本文就射频前端的低噪声放大器设计进行研究和分析,并且进行了流片生产和测试。首先进行了基础理路的研究分析,通过仿真电路满足性能,最后再通过流片测试得到结论。本文中对其带宽以及噪声系数进行了测试并且与预期效果很接近。通过本文设计得到了带宽为近1.5GHz,其增益的大小为23.2dB。