InP and Si metal-oxide semiconductor structures fabricated using oxygen plasma assisted wafer bonding

In this paper, InP metal-oxide-semiconductor (MOS) structures are fabricated by transferring thermally grown SiO₂ to InP from oxidized Si wafers using oxygen plasma assisted wafer bonding followed by annealing at either 125°C or at 400°C. Well-defined accumulation and inversion regions in recorded capacitance-voltage (C-V) curves were obtained. The long-term stability was comparable to what has been previously reported. The structures exhibited high breakdown fields, equivalent to thermally grown SiO₂-Si MOS structures. The transferring process was also used to fabricate bonded Si MOS structures.     

Surface integrity and removal mechanism of silicon wafers in chemo-mechanical grinding using a newly developed soft abrasive grinding wheel

A new soft abrasive grinding wheel (SAGW) used in chemo-mechanical grinding (CMG) was developed for machining silicon wafers. The wheel consisted of magnesia (MgO) soft abrasives, calcium carbonate (CaCO₃) additives and magnesium oxychloride bond. Surface topography, roughness and subsurface damage of the silicon wafers ground using the new SAGW were comprehensively investigated. The results showed that the grinding with the new SAGW produced a surface roughness of about 0.5 nm in R_a and a subsurface damage layer of about 10 nm in thickness, which is comparable to that produced by chemo-mechanical polishing. This study also revealed that the chemical reactions between MgO abrasive, CaCO₃ additives and silicon material did occur during grinding, thereby generating a soft reactant layer on the ground surface. The reactant layer was easily removed during the grinding process.     

Improving the quality of sub-1.5-nm-thick oxynitride gate dielectric for FETs with narrow channel and shallow-trench isolation using radical oxygen and nitrogen

We have demonstrated that oxynitridation using radical-oxygen (radical-O) and radical-nitrogen (radical-N) improves reverse narrow channel effects (RNCE) and reliability in sub-1.5-nm-thick gate-SiO/sub 2/ FETs with narrow channel and shallow-trench isolation (STI), suitable for high-density SRAM and logic devices. The STI formation followed by oxidation for the gate-dielectric causes various orientations of the Si surface, and thus, thermal oxidation forms the partial thin SiO/sub 2/ and causes RNCE and reliability degradation. Oxidation using radical-O forms uniform SiO/sub 2/ on Si[100] and Si[111] surfaces and suppresses RNCE in a sub-1.5 nm-thick gate-SiO/sub 2/ FET with STI. Nitrifying the SiO/sub 2/ using radical-N increases the physical thickness while maintaining the oxide equivalent thickness on both Si[111] and Si[100] surfaces, thus producing a low-leakage and highly reliable sub-1.5 nm-thick gate-SiON.