Development of different copper seed layers with respect to the copper electroplating process

Two types of copper seed layers deposited by MOCVD and long throw sputtering (LTS) onto a tantalum barrier layer were used for electroplating (EP) of copper in the forward pulsed mode. MOCVD and PVD copper seed layers were compared with respect to step coverage, electrical resistivity, texture and adhesion behaviour. The different properties induce different electroplating fill attributes, including grain size and adhesion behaviour. MOCVD Cu seed layers show high step coverage, but do not adhere to the Ta barrier after the Cu EP. LTS Cu reveal strong (111) texture and excellent adhesion before and after Cu EP. Therefore, a CMP process could only be performed on patterned wafers with PVD/EP copper to obtain electrical data. The fabricated Cu lines show a high yield with respect to opens and shorts and standard deviations of the line resistance across the wafer.     

New plating bath for electroless copper deposition on sputtered barrier layers

A new copper plating bath for electroless deposition directly on conductive copper-diffusion barrier layers has been developed. This plating bath can be operated at temperatures between 20 and 50°C and has good stability. High temperature processing allows for increased deposition rates and decreased specific resistivity values for the deposited copper films. Electroless Cu films deposited from this bath showed a conformal step coverage in high aspect ratio trenches and, therefore, are promising as seed layers for copper electroplating. The effect of the bath composition, activation procedure and processing temperature on the plating rate and morphology of the deposited copper has been studied and is presented here.     

Seed layer enhancement by electrochemical deposition: The copper seed solution for beyond 45 nm

With the downscaling of feature dimensions, each layer of the metallization stack has to become thinner and thinner to comply with the geometrical constraints. In particular, seed layer thickness will have to be drastically reduced for the 45 nm node and beyond. As PVD is a non-conformal technique, discontinuous seeding of the sidewalls of narrow features can be expected. In this study, a seed layer enhancement (SLE) process is evaluated for 300 mm processing, as a possible solution for copper seeding for the 45 nm node and below. We demonstrate the extendibility of this process to the fabrication of 300 mm wafers. We confirm the excellent morphological properties of the deposit, which is extremely conformal, thus continuous inside the features. This process is successfully integrated in the existing metallization sequence, without any modification of the subsequent steps, including electroplating. This demonstration is supported by electrical results, showing that a 10 nm thick PVD liner, which leads to severe degradation of line and via resistance, is efficiently repaired with only 20 nm SLE. All electrical performances (line and via resistance, dispersion and yield) are fully recovered with implementation of the SLE step.     

Fabrication of potential NiMoP diffusion barrier/seed layers for Cu interconnects via electroless deposition

Potential NiMoP barrier/seed layers for Cu interconnects have been successfully formed by electroless deposition on SiO₂. Four different wet processes were attempted to activate the surface before electroless deposition. Material properties including the crystal structure, deposition rate, composition, and electrical resistivity of NiMoP layers were investigated by atomic force microscopy (AFM), scanning electron microscopy (SEM), Auger electron spectroscopy, x-ray diffraction (XRD), four-point probe, and surface profilometry (Alpha-step). In this study, different compositions of NiMoP films have been obtained. Ni₈₉Mo₂P₉ with nanocrystalline structure has the highest resistivity due to enriched P content, while Ni₈₈Mo₉P₃ has the lowest value among the compositions considered in this study. The seed layer and the barrier layer functions of NiMoP were verified by direct Cu electrodeposition and secondary ion mass spectroscopy (SIMS).     

Sub-100 nm ALD-assisted nanoimprint lithography for realizing vertical organic transistors with high ON/OFF ratio and high output current

We introduced a conformal atomic-layer-deposited aluminum oxide layer to cover the imprint mold to reduce the feature size and to strengthen the mold durability. A nano-hole array pattern with diameter down to 85 nm was successfully transferred to sample substrate to fabricate a vertical organic transistor. The Imprint vertical organic transistor exhibited high output current density as 4.35 cm²/V s and high ON/OFF current ratio as 11,000 at a low operation voltage as 1.5 V.     

Investigations regarding Through Silicon Via filling for 3D integration by Periodic Pulse Reverse plating with and without additives

In this contribution we show experimental investigations regarding Periodic Pulse Reverse (PPR) plating for the filling of Through Silicon Vias that are aimed for the use in 3D integration applications. The purpose of this method is to prevent the use of plating additives that induce high process complexity in terms of process control and high process costs due to the high consumption of those additives. We therefore compare the effect of PPR plating without additives to that effect of PPR plating with additives. In first results with non-optimized PPR plating we already show the large gain in step coverage during TSV filling compared to standard DC plating.     

High-performance enhancement-mode AlGaN/GaN MOS-HEMTs with fluorinated stack gate dielectrics and thin barrier layer

We present high-performance enhancement-mode AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) by a fluorinated gate dielectric technique. A nanolaminate of an Al₂O₃/La_xAl_1-xO₃/Al₂O₃ stack (x≈0.33) grown by atomic layer deposition is employed to avoid fluorine ions implantation into the scaled barrier layer. Fabricated enhancement-mode MOS-HEMTs exhibit an excellent performance as compared to those with the conventional dielectric-last technique, delivering a large maximum drain current of 916 mA/mm and simultaneously a high peak transconductance of 342 mS/mm. The balanced DC characteristics indicate that advanced gate stack dielectrics combined with buffered fluorine ions implantation have a great potential for high speed GaN E/D-mode integrated circuit applications.     

Highly-impermeable Al2O3/HfO2 moisture barrier films grown by low-temperature plasma-enhanced atomic layer deposition

Polymer substrates are essential components of flexible electronic applications such as OTFTs, OPVs, and OLEDs. However, high water vapor permeability of polymer films can significantly reduce the lifetime of flexible electronic devices. In this study, we examined the water vapor permeation barrier properties of Al₂O₃/HfO₂ mixed oxide films on polymer substrates. Al₂O₃/HfO₂ films deposited by plasma-enhanced atomic layer deposition were transparent, chemically stable in water and densely amorphous. At 60 °C and 90% relative humidity (RH) accelerated condition, 50-nm-thick Al₂O₃/HfO₂ had water vapor transmission rate (WVTR) = 1.44 × 10⁻⁴ g m⁻² d⁻¹, whereas single layers of Al₂O₃ had WVTR = 3.26 × 10⁻⁴ g m⁻² d⁻¹ and of HfO₂ had WVTR = 6.75 × 10⁻² g m⁻² d⁻¹. At 25 °C and 40% RH, 50-nm-thick Al₂O₃/HfO₂ film had WVTR = 2.63 × 10⁻⁶ g m⁻² d⁻¹, which is comparable to WVTR of conventional glass encapsulation.     

GaAs-based metal-oxide semiconductor field-effect transistors with Al2O3 gate dielectrics grown by atomic layer deposition

We demonstrate GaAs-based, metal-oxide-semiconductor field-effect transistors (MOSFETs) with excellent performance using an Al₂O₃ gate dielectric, deposited by atomic layer deposition (ALD). This achievement is very significant because Al₂O₃ possesses highly desirable physical and electrical properties as a gate dielectric. These MOSFET devices exhibit extremely low gate-leakage current, high transconductance, and high dielectric breakdown strength. A short-circuit, current-gain, cutoff frequency (f_T) of 14 GHz and a maximum oscillation frequency (f_max) of 25.2 GHz have been achieved from a 0.65-μm gate-length device. The interface trap density (D_it) of Al₂O₃/GaAs is evaluated by the hysteresis of drain-source current, I_ds, versus gate-source bias, V_gs, and the frequency dispersion of transconductance, g_m.     

An electro-enhanced metalorganic chemical vapor deposition technique for producing thin copper films with (hfac)Cu(COD) as a precursor

A novel electro-enhanced metalorganic chemical vapor deposition (EEMOCVD) technique for producing copper (Cu) thin films on TaN/Si substrates with hexafluoroacetylacetonate-copper(I)-1,5-cyclo-octadine, (hfac)Cu^I(COD), as a precursor was investigated in this paper. This novel technique features supplying a direct current (DC) to TaN/Si substrates while the deposition of Cu thin films is in progress. Experiments on EEMOCVD yielded fortuitously positive results: (1) the deposited Cu films were superior in quality and (2) the growth rate of Cu film deposition increased. The above results are more desirable than those achieved through the conventional MOCVD (CMOCVD) technique. The proposed EEMOCVD technique hence proves to be more effective in forming smooth and continuous thin copper films.     

Drain current enhancement and negligible current collapse in GaN MOSFETs with atomic-layer-deposited HfO2 as a gate dielectric

Accumulation-type GaN metal-oxide-semiconductor field-effect-transistors (MOSFET’s) with atomic-layer-deposited HfO₂ gate dielectrics have been fabricated; a 4 μm gate-length device with a gate dielectric of 14.8 nm in thickness (an equivalent SiO₂ thickness of 3.8 nm) gave a drain current of 230 mA/mm and a broad maximum transconductance of 31 mS/mm. Owing to a low interfacial density of states (D_it) at the HfO₂/GaN interface, more than two third of the drain currents come from accumulation, in contrast to those of Schottky-gate GaN devices. The device also showed negligible current collapse in a wide range of bias voltages, again due to the low D_it, which effectively passivate the surface states located in the gate-drain access region. Moreover, the device demonstrated a larger forward gate bias of +6 V with a much lower gate leakage current.     

Charge trapping memory devices employing multi-layered Ge/Si nanocrystals for storage fabricated with ALD and PLD methods

The Ge/Si nanocrystals on ultra thin high-k tunnel oxide Al2O3 were fabricated to form the charge trapping memory prototype with asymmetric tunnel barriers through combining the advanced atomic layer deposition (ALD) and pulse laser deposition (PLD)techniques. Charge storage characteristics in such memory structure have been investigated using capacitance-voltage (C-V) and capacitance-time (C-t) measurements. The results prove that both the two-layered and three-layered memory structures behave relatively qualified for the multi-level cell storage. The results also demonstrate that compared to electrons, holes reach a longer retention time even with an ultra thin tunnel oxide owing to the high band offset at the valence band between Ge and Si.     

High‐speed atmospheric atomic layer deposition of ultra thin amorphous TiO2 blocking layers at 100 °C for inverted bulk heterojunction solar cells

Ultrafast, spatial atmospheric atomic layer deposition, which does not involve vacuum steps and is compatible with roll‐to‐roll processing, is used to grow high quality TiO₂ blocking layers for organic solar cells. Dense, uniform thin TiO₂ films are grown at temperatures as low as 100 °C in only 37 s (~20 nm/min growth rate). Incorporation of these films in P3HT‐PCBM‐based solar cells shows performances comparable with cells made using TiO₂ films deposited with much longer processing times and/or higher temperatures. Copyright © 2013 John Wiley & Sons, Ltd.     

High‐efficiency copper indium gallium diselenide (CIGS) solar cells with indium sulfide buffer layers deposited by atomic layer chemical vapor deposition (ALCVD)

This paper presents optimization studies on the formation of indium sulfide buffer layers for high‐efficiency copper indium gallium diselenide (CIGS) thin‐film solar cells with atomic layer chemical vapour deposition (ALCVD) from separate pulses of indium acetylacetonate and hydrogen sulfide. A parametric study of the effect of deposition temperature between 160° and 260°C and thickness (15–30 nm) shows an optimal value at about 220°C for a layer thickness of 30 nm, leading to an efficiency of 16·4%. Analysis of the device shows that indium sulfide layers are characterised by an improvement of the blue response of the cells compared with a standard CdS‐processed cell, due to a high apparent band gap (2·7–2·8 eV), higher open‐circuit voltages (up to 665 mV) and fill factor (78%). This denotes high interface quality. Atomic diffusion processes of sodium and copper in the buffer layer are demonstrated. Copyright © 2003 John Wiley & Sons, Ltd.     

The Zn(S,O,OH)/ZnMgO buffer in thin film Cu(In,Ga)(S,Se)2‐based solar cells part I: Fast chemical bath deposition of Zn(S,O,OH) buffer layers for industrial application on Co‐evaporated Cu(In,Ga)Se2 and electrodeposited CuIn(S,Se)2 solar cells

This paper is focused on the basic study and optimization of short time (<10 min) Chemical Bath Deposition (CBD) of Zn(S,O,OH) buffer layers in co‐evaporated Cu(In,Ga)Se₂ (CIGSe) and electrodeposited CuIn(S,Se)₂ ((ED)‐CIS) solar cells for industrial applications. First, the influence of the deposition temperature is studied from theoretical solution chemistry considerations by constructing solubility diagrams of ZnS, ZnO, and Zn(OH)₂ as a function of temperature. In order to reduce the deposition time under 10 min, experimental growth deposition studies are then carried out by the in situ quartz crystal microgravimetry (QCM) technique. An optimized process is performed and compared to the classical Zn(S,O,OH) deposition. The morphology and composition of Zn(S,O,OH) films are determined using SEM and XPS techniques. The optimized process is tested on electrodeposited‐CIS and co‐evaporated‐CIGSe absorbers and cells are completed with (Zn,Mg)O/ZnO:Al windows layers. Efficiencies similar or even better than CBD CdS/i‐ZnO reference buffer layers are obtained (15·7% for CIGSe and 8·1% for (ED)‐CIS). Copyright © 2009 John Wiley & Sons, Ltd.