Trench transistor DRAM cell

A new one-transistor DRAM cell with both the transistor and the capacitor fabricated on the trench sidewalls is described. With the signal stored on the polysilicon node surrounded by oxide, the cell is expected to have a high alpha particle immunity. The cell occupies only 9 µm²using 1-µm design rules. This cell size is sufficiently small to enable a 4-Mbit DRAM of reasonable chip size with these design rules, and possesses further scalability for 16-Mbit DRAM's.     

A speed-enhanced DRAM array architecture with embedded ECC

An array architecture with countermeasures for the smaller signal charge caused by scaling down is proposed. Based on a new access model, the combination of a hierarchical data bus configuration and multipurpose register (MPR) provides high-speed array access. The MPR also includes practical array-embedded error checking and correcting (ECC) with little area penalty and no access overhead in the page mode. The array architecture is applied to a scaled-down 16-Mb DRAM and has achieved high performance     

A 29-ns 64-Mb DRAM with hierarchical array architecture

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers are distributed in the array. To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted. A hierarchical I/O scheme with semidirect sensing switch is introduced for high speed data transfer in the I/O paths. By combining these proposed circuit techniques and 0.25-μm CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71×1.20 μm ², and the chip size is 15.91×9.06 mm². A typical access time under 3.3 V power supply voltage is 29 ns     

New three-dimensional memory array architecture for futureultrahigh-density DRAM

In this paper, a three-dimensional (3-D) memory array architecture is proposed. This new architecture is realized by stacking several cells in series vertically on each cell located in a two-dimensional array matrix. Therefore, this memory array architecture has a conventional horizontal row and column address and new vertical row address. The total bit-line capacitance of this proposed architecture's DRAM is suppressed to 37% of normal DRAM when one bit-line has 1-Kbit cells and the same design rules are used. Moreover, an array area of 1-Mbit DRAM using the proposed architecture is reduced to 11.5% of normal DRAM using the same design rules. This proposed architecture's DRAM can realize small bit-line capacitance and small array area simultaneously. Therefore, this proposed 3-D memory array architecture is suitable for future ultrahigh-density DRAM     

Leakage mechanisms in the trench transistor DRAM cell

The authors discuss a band-to-band tunneling mechanism in the trench transistor cell (TTC), which is used in Texas Instruments' 4-Mbit DRAM. This effect should be operative in the class of trench cells in which the charge is stored inside the trench and the substrate forms a capacitor plate. This effect does not compromise the functionality of the cell; in fact, it has the potential of improving the long-term reliability of the cell by preventing electrical overstress of the trench capacitor oxide     

A block-oriented RAM with half-sized DRAM cell and quasi-foldeddata-line architecture

The authors describe a block-oriented random-access memory (BORAM) based on a series-connected cell concept and a quasi-folded data-line architecture. The series-connected cell concept allows a nearly half-sized DRAM cell even when using the same fabrication process as for conventional DRAMs. The low-noise quasi-folded data-line architecture allows the data-line capacitance to be one eighth the conventional value at the minimum, or the number of cells per amplifier to be 64 times the conventional number at the maximum. In addition, this architecture provides a more relaxed layout for the READ/WRITE circuits. The operation of four series-connected cells is observed successfully through a test device which includes a voltage-to-current conversion circuit, a current-mirror amplifier, and a 0.76-μm² crown-shaped stack-capacitor (STC) cell     

A new DRAM cell with a transistor on a lateral epitaxial siliconlayer (TOLE cell)

A new dynamic RAM (DRAM) cell structure and its fabrication technology are proposed. The proposed DRAM cell consists of a transistor on a lateral epitaxial silicon layer (TOLE) and a stacked capacitor formed in a trench. It can achieve high immunity to alpha-particle-induced noise and a low parasitic bit-line capacitance. The TOLE structure is produced by a silicon-on-insulator fabrication technology newly developed by combining epitaxial lateral overgrowth and preferential polishing. Reasonable electrical characteristics for the TOLE and high immunity against alpha-particle disturbance for the TOLE cell were confirmed     

Partial SOI type isolation for improvement of DRAM cell transistor characteristics

A new DRAM cell transistor using an isotropic etching under the storage node is proposed, and it is shown that the structure gives improvement both in the short-channel effect and in the body-bias control. The asymmetrical characteristics of the structure are analyzed by experiments and simulation, and the feasibility of utilizing the asymmetric characteristics is reported.     

A low-impedance open-bitline array for multigigabit DRAM

The noise-generating mechanisms inherent in the open-bitline DRAM array using the 6F² (F: feature size) memory cells and techniques for reducing the noise are described. The sources of differential noise coupled to the paired bitlines laid out in two arrays are the p-well, cell plate, and the group of nonselected wordlines. It was found, by simulation and by experiment with a 0.13-μm 256-Mb test chip, that the level of noise is dramatically reduced by using a low-impedance array with careful layout featuring low-resistivity materials, tight bridging between pairs of adjacent arrays, and a small array, achieving a comparable level of noise to that seen in the twisted and folded-bitline array. On basis of these results, it turns out that the open-bitline array has a strong chance of revival in the multigigabit generation, as long as these noise reduction techniques are applied     

High-speed DRAM architecture development

This paper is an overview of the high-speed DRAM architecture developments. We discuss developments on density growth, interface technology, memory-core architecture, and DRAM+ASIC technology. We can find the developments of density as 2× growth instead of 4× by each generation. Interface technologies will have a tendency to use the terminated bus structure for higher data rate. Memory-core architecture developments are the trials for actual bandwidth improvements. DRAM+ASIC technologies seem to require universal interface solutions. We tried to show that no single solution is able to cover the wide diversity of future system requirements     

A scalable ATM switching system architecture

The architecture of an asynchronous transfer mode (ATM) switching system for prototype applications is presented. The general concept to upgrade the existing ISDN switch with an ATM module is introduced, and the building blocks of this ATM module are described in detail. Switching of ATM cells is performed in a single application-specific integrated circuit (ASIC). ASICs can be cascaded to form large switching modules. Peripheral modules interface the ATM switch to external transmission systems and perform all ATM-related functions, including means for redundancy of the switching network. The redundancy scheme tolerates single failures without affecting the user information. A switching network architecture is shown to be capable of fulfilling varying demands in terms of the number of ports for ATM switches and cross connects, concentrators, and multiplexers     

一种可重构阵列结构及其任务调度算法

提出了一种可以利用计算时间覆盖配置时间和数据传输时间的可重构阵列结构,并且针对该可重构阵列结构提出了一种表调度算法进行任务调度.在SOCDesigner平台上进行了软硬件协同仿真,对于IDCT,FFT,4×4矩阵乘法新可重构阵列相比原来的可重构阵列有平均约10%的速度提升.     

A capacitorless double-gate DRAM cell

A capacitorless double-gate DRAM (DG-DRAM) cell is proposed in this study. Its dual gates and thin body reduce off state leakage and. disturb problems. Dopant fluctuations, which can be particularly important in high-density arrays, are avoided by using a thin, lightly doped body. The cell's large body coefficient ((dV_T)/(dV_BD) transforms small gains of body potential into increased drain current. MEDICI simulations for 85°C show that a DG-DRAM cell may sustain a measurable change in drain current several hundred milliseconds after programming. These characteristics suggest that a thin body, double-gate cell is an interesting candidate for high density DRAM technologies     

A million transistor systolic array graphics engine

Pixel processing is the most fundamental performance bottleneck in high-end three-dimensional graphics systems. This paper presents the design of a specialized custom VLSI graphics chip that was implemented with one million transistors and is capable of processing pixels at extremely rapid rates close to one nanosecond. This was made possible by utilizing a large number of identical pipelined pixel processors that operate in a purely systolic fashion. The chip has been designed at the IBM Research Division's Thomas J. Watson Research Center.     

一种循环流水阵列架构

描述了一种基于循环流水计算的阵列架构（PLAA）,该阵列架构能够工作在基于AHB协议的总线接口上,通过与ARM处理器指令通信,达到辅助主处理器进行大规模密集计算的目的。描述了这一处理器的结构,并着重介绍了二维DCT算法在PLAA中的映射与实现。仿真结果显示,PIAA能达到7倍以上于通用处理器的性能,并在实现复杂度、运行效率与通用性中达到一个权衡。     

A distributed scheduling architecture for scalable packet switches

The continuous growth in the demand for diversified quality-of-service (QoS) guarantees in broadband networks introduces new challenges in the design of packet switches that scale to large switching capacities. Packet scheduling is the most critical function involved in the provision of individual bandwidth and delay guarantees to the switched flows. Most of the scheduling techniques proposed so far assume the presence in the switch of a single contention point, residing in front of the outgoing links. Such an assumption is not consistent with the highly distributed nature of many popular architectures for scalable switches, which typically have multiple contention points, located in both ingress and egress port cards, as well as in the switching fabric. We define a distributed multilayered scheduler (DMS) to provide differentiated QoS guarantees to individual end-to-end flows in packet switches with multiple contention points. Our scheduling architecture is simple to implement, since it keeps per-flow scheduling confined within the port cards, and is suitable to support guaranteed and best-effort traffic in a wide range of QoS frameworks in both IP and ATM networks     

A scalable pipelined architecture for fast buffer SRAMs

The design of synchronous buffer SRAMs for packet switching and signal processing applications is described. Called scalable cellular RAM (SCRAM), the approach configures memory blocks in a 2-D array with fully pipelined address and data distribution. The memory is scalable in that the access frequency is determined by the access time of a single block and is independent of the number of blocks. An experimental 0.5 μm CMOS 256 Kb SCRAM chip is described that operates at 240 MHz. Simulation results show that larger arrays are feasible using the suggested power reduction and redundancy techniques     

A new scalable VLSI architecture for Reed-Solomon decoders

A very-large-scale integration architecture for Reed-Solomon (RS) decoding is presented that is scalable with respect to the throughput rate. This architecture enables given system specifications to be matched efficiently independent of a particular technology. The scalability is achieved by applying a systematic time-sharing technique. Based on this technique, new regular, multiplexed architectures have been derived for solving the key equation and performing finite field divisions. In addition to the flexibility, this approach leads to a small silicon area in comparison with several decoder implementations published in the past. The efficiency of the proposed architecture results from a fine granular pipeline scheme throughout each of the RS decoder components and a small overhead for the control circuitry. Implementation examples show that due to the pipeline strategy, data rates up to 1.28 Gbit/s are reached in a 0.5 μm CMOS technology     

2.4F2 memory cell technology with stacked-surroundinggate transistor (S-SGT) DRAM

This paper proposes 2.4F² memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM. One unit of the S-SGT DRAM is formed by stacking several SGT-type cells in series vertically. The SGT-type cell itself arranges gate, source, drain and plate on a silicon pillar vertically. Both gate and plate electrode surround the silicon pillar. Subsequently applied trench etching and sidewall spacer formation during S-SGT DRAM formation causes a step-like silicon pillar structure. Due to these steps, gate, plate and diffusion layer in one S-SGT DRAM unit are fabricated vertically by a self-aligned process. The cell size dependence of the self-aligned-type S-SGT DRAM was analyzed with regard to the above step widths and the number of cells in one unit. As a result, the cell design for minimizing the cell size of this device has been formulated. By using the proposed cell design, it is demonstrated by process simulation that the S-SGT DRAM in 0.5 μm design rule can achieve a cell size of 2.4F², which is half of the cell size of a conventional SGT DRAM cell (4.8F²). Therefore, the S-SGT DRAM is a promising candidate for future ultra high density DRAMs     

A ferroelectric DRAM cell for high-density NVRAMs

The operation of a ferroelectric DRAM (dynamic random access memory) cell for nonvolatile RAM (NVRAM) applications is described. Because polarization reversal only occurs during nonvolatile store/recall operations and not during read/write operations, ferroelectric fatigue is not a serious endurance problem. For a 3-V power supply, the worst-case effective silicon dioxide thickness of the unoptimized lead zirconate titanate film studied is less than 17 Å. The resistivity and endurance properties of ferroelectric films can be optimized by modifying the composition of the film. This cell can be the basis of a very-high-density NVRAM with practically no read/write cycle limit and at least 10¹⁰ nonvolatile store/recall cycles