Fabrication and characterization of directly-assembled ZnO nanowire field effect transistors with polymer gate dielectrics

We report the fabrication and electrical characterization of ZnO nanowire field effect transistors (FETs). Dielectrophoresis technique was used to directly align ZnO nanowires between lithographically prepatterned source and drain electrodes, and spin-coated polyvinylphenol (PVP) polymer thin layer was used as a gate dielectric layer in "top-gate" FET device configuration. The electrical characteristics of the top-gate ZnO nanowire FETs were found to be comparable to the conventional "bottom-gate" nanowire FETs with a SiO2 gate dielectric layer, suggesting the directly-assembled nanowire FET with a polymer gate dielectric layer is a useful device structure of nanowire FETs.     

Modeling novel double-in-plane gate electric-double-layer thin-film and nanoscale transistors

A novel double-in-plane gate oxide-based electric-double-layer (EDL) transistor structure applicable to thin-film transistors (TFTs) and nanoscale transistors (nanoFETs) is proposed. An equivalent circuit model is provided to illustrate the operation mechanism. The double-in-plane gate structure can simplify device fabrication effectively and provide unique tunability of threshold. Specifically, the gate bias modulates the threshold voltage of TFT and nanoFET and effectively controls the transistor subthreshold swing and leakage current. Moreover, the EDL gate dielectric can lead to a high gate dielectric capacitance (>1 μF/cm(2)). These simulation results provide basic understanding needed to use and control EDL TFTs and nanoFETs in a novel manner.     

Reduction of hysteresis in HgSe nanoparticle-based thin-film transistors using blocking oxide layers on plastics

In this study, the hysteresis mechanism is investigated for bottom-gate HgSe nanoparticle (NP)-based thin-film transistors (TFTs) using cross-linked poly vinyl alcohol (PVA) as the gate dielectric on plastics. The hysteresis loop with the clockwise direction is observed and the width of the hysteresis is reduced at long delay times. These phenomena indicate that the origin of the hysteresis is the injection of electrons from the gate electrode to the trap site located in the PVA layer. The widths of the hysteresis curves taken from the TFTs are not reduced even though the annealing treatment for the PVA gate dielectric is performed under N2, O2, and in a vacuum at 120 degrees C for 1 hour. The electron injection from the gate electrode is effectively prevented by inserting Al2O3 of 10 nm utilized as the blocking layer between gate electrode and PVA layer. The hysteresis window is remarkably reduced from about 8 V in HgSe NP-based TFTs without blocking layer to nearly 0 V in the TFTs with blocking layer of Al2O3.     

UV–Ozone Interfacial Modification in Organic Transistors for High‐Sensitivity NO2 Detection

A new type of nitrogen dioxide (NO₂) gas sensor based on copper phthalocyanine (CuPc) thin film transistors (TFTs) with a simple, low‐cost UV–ozone (UVO)‐treated polymeric gate dielectric is reported here. The NO₂ sensitivity of these TFTs with the dielectric surface UVO treatment is ≈400× greater for [NO₂] = 30 ppm than for those without UVO treatment. Importantly, the sensitivity is ≈50× greater for [NO₂] = 1 ppm with the UVO‐treated TFTs, and a limit of detection of ≈400 ppb is achieved with this sensing platform. The morphology, microstructure, and chemical composition of the gate dielectric and CuPc films are analyzed by atomic force microscopy, grazing incident X‐ray diffraction, X‐ray photoelectron spectroscopy, and Fourier transform infrared spectroscopy, revealing that the enhanced sensing performance originates from UVO‐derived hydroxylated species on the dielectric surface and not from chemical reactions between NO₂ and the dielectric/semiconductor components. This work demonstrates that dielectric/semiconductor interface engineering is essential for readily manufacturable high‐performance TFT‐based gas sensors.     

High-performance metal-induced lateral-crystallization polysilicon thin-film transistors with multiple nanowire channels and multiple gates

In this study, pattern-dependent nickel (Ni) metal-induced lateral-crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with ten nanowire channels and multigate structure were fabricated and characterized. Experimental results reveal that applying ten nanowire channels improves the performance of an Ni-MILC poly-Si TFT, which thus has a higher ON current, a lower leakage current, and a lower threshold voltage (V/sub th/) than single-channel TFTs. Furthermore, the experimental results reveal that combining the multigate structure and ten nanowire channels further enhances the entire performance of Ni-MILC TFTs, which thus have a low leakage current, a high ON/OFF ratio, a low V/sub th/, a steep subthreshold swing, and kink-free output characteristics. The multigate structure with ten-nanowire-channel Ni-MILC TFTs has a few poly-Si grain boundary defects, a low lateral electrical field, and a gate-channel shortening effect, all of which are associated with such high-performance characteristics.     

Moisture-induced hysteresis of pentacene thin film transistors with cross-linked poly(4-vinylphenol) gate dielectrics

The time variable electrical characteristics of pentacene thin-film transistors (TFTs) with poly(4-vinylphenol) gate dielectrics were investigated under various relative humidity conditions and the effect of moisture on the hysteresis behavior of the pentacene TFTs was studied. One possible cause of the hysteresis behavior is the presence of inherent hydroxyl groups in bulk or surface of the polymeric dielectric, which make the gate dielectric polar, but the hysteresis behavior of the pentacene TFTs was found to depend strongly on the relative humidity and to increase with an increase of the moisture in the surrounding atmosphere. With a time-scalable investigation, it was also found that the adsorption of moisture onto the pentacene layer is the main reason for the hysteresis even with the -OH rich polymeric dielectric. The hysteresis behavior was found to be significantly reduced by suppression of moisture or other moisture-induced impurities, such as the encapsulation of the devices with glass.     

High-performance transparent inorganic-organic hybrid thin-film n-type transistors

High-performance thin-film transistors (TFTs) that can be fabricated at low temperature and are mechanically flexible, optically transparent and compatible with diverse substrate materials are of great current interest. To function at low biases to minimize power consumption, such devices must also contain a high-mobility semiconductor and/or a high-capacitance gate dielectric. Here we report transparent inorganic-organic hybrid n-type TFTs fabricated at room temperature by combining In2O3 thin films grown by ion-assisted deposition, with nanoscale organic dielectrics self-assembled in a solution-phase process. Such TFTs combine the advantages of a high-mobility transparent inorganic semiconductor with an ultrathin high-capacitance/low-leakage organic gate dielectric. The resulting, completely transparent TFTs exhibit excellent operating characteristics near 1.0 V with large field-effect mobilities of >120 cm2 V(-1) s(-1), drain-source current on/off modulation ratio (I(on)/I(off)) approximately 10(5), near-zero threshold voltages and sub-threshold gate voltage swings of 90 mV per decade. The results suggest new strategies for achieving 'invisible' optoelectronics.     

Measuring the capacitance of individual semiconductor nanowires for carrier mobility assessment

Capacitance-voltage characteristics of individual germanium nanowire field effect transistors were directly measured and used to assess carrier mobility in nanowires for the first time, thereby removing uncertainties in calculated mobility due to device geometries, surface and interface states, and gate dielectric constants and thicknesses. Direct experimental evidence showed that surround-gated nanowire transistors exhibit higher capacitance and better electrostatic gate control than top-gated devices, and are the most promising structure for future high performance nanoelectronics.     

The influence of fabrication process on top-gate thin-film transistors

Amorphous indium zinc oxide (a-IZO) thin-film transistors (TFTs) with bottom- and top-gate structures were fabricated at room temperature by direct current (DC) magnetron sputter in this research. High dielectric constant (κ) hafnium oxide (HfO₂) films and a-IZO were deposited for the gate insulator and the semiconducting channel under a mixture of ambient argon and oxygen gas, respectively. The bottom-gate TFTs showed good TFT characteristics, but the top-gate TFTs did not display the same characteristics as the bottom-gate TFTs despite undergoing the same process of sputtering with identical conditions. The electrical characteristics of the top-gate a-IZO TFTs exhibited strong relationships with sputtering power as gate dielectric layer deposition in this study. The ion bombardment and incorporation of sputtering ions damaged the interface between the active layer and the gate insulator in top-gate TFTs. Hence, the sputtering power was reduced to decrease damage while depositing HfO₂ films. When using 50 W DC magnetron sputtering, the top-gate a-IZO TFTs showed the following results: a saturation mobility of 5.62 cm²/V-s; an on/off current ratio of 1 × 10⁵; a sub-threshold swing (SS) of 0.64 V/decade; and a threshold voltage (V_th) of 2.86 V.     

Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs

In this paper, electrical characteristics of small nanowire fin field-effect transistor (FinFET) are investigated by using a three-dimensional quantum correction simulation. Taking several important electrical characteristics as evaluation criteria, two different nanowire FinFETs, the surrounding-gate and omega-shaped-gate devices, are examined and compared with respect to different ratios of the gate coverage. By calculating the ratio of the on/off current, the turn-on resistance, subthreshold swing, drain-induced channel barrier height lowering, and gate capacitance, it is found that the difference of the electrical characteristics between the surrounding-gate (i.e., the omega-shaped-gate device with 100% coverage) and the omega-shaped-gate nanowire FinFET with 70% coverage is insignificant. The examination presented here is useful in the fabrication of small omega-shaped-gate nanowire FinFETs. It clarifies the main difference between the surrounding-gate and omega-shaped-gate nanowire FinFETs and exhibits a valuable result that the omega-shaped-gate device with 70% coverage plays an optimal candidate of the nanodevice structure when we consider both the device performance and manufacturability.     

Nanometer-scale oxide thin film transistor with potential for high-density image sensor applications

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al?O?/SiO?) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.     

Influence of radial stress on the performance of gate-all-around Ge(110) NW FETs with HfO2 dielectric

In this work, a simulation method from strained valence band structures to strained mobility calculation to consider a radial stress at the boundary of HfO2 gate dielectric surrounding Ge(110) nanowire is developed. The simulation implements the radial stress to strain distribution calculation via finite element method and then to valence band calculation. The radial stress at the boundary of gate dielectric pushes the valence subbands downwards in contrast with lattice mismatch strain effects between Ge NW and gate dielectric. The impact of the radial stress on the hole effective masses and density of states of HfO2 gate dielectric surrounding Ge(110) nanowire are also investigated. The potential distribution and holes density distribution are calculated by solving the 2D Poisson equation and Schr?dinger equation self-consistently in NW cross section. Hole mobility is obtained by modified Kubo-Greenwood formula. Based on strained valence band structures, the hole density distribution in cross-sectional Ge(110) NW reduces with larger radial stress value. The phonon scattering-limited hole mobility in NW significantly increases as the radial stress increases.     

Thin-film transistors deposited by hot-wire chemical vapor deposition

In the past few years hot-wire chemical vapor deposition (HWCVD) has become a popular technique for the deposition of silicon-based thin-film transistors (TFTs). Several groups have been using hot-wire deposited amorphous and microcrystalline silicon as the active layers in TFTs. In such devices either thermal SiO₂ or plasma-deposited silicon nitride was the gate insulator. Recently ‘All-Hot-Wire TFTs’ have been realized, with also the silicon nitride deposited by HWCVD. This paper reviews the characteristics of hot-wire TFTs with amorphous and microcrystalline silicon using plasma- or hot-wire deposited silicon nitride as the gate insulator. It has been shown that hot-wire TFTs have a higher stability upon gate-bias stress as compared to their plasma-deposited counterparts. We present an overview of the stability of hot-wire TFTs deposited at a range of substrate temperatures. The higher stability of hot-wire TFTs that have been deposited at temperatures of 400–500 °C is ascribed to an enhanced structural order, i.e. a higher degree of medium-range order of the silicon network.     

Low voltage ZnO thin-film transistors with Ti-substituted BZN gate insulator for flexible electronics

We report the fabrication of ZnO based thin-film transistors (TFTs) with high-k gate insulator of Ti-substituted Bi_1.5ZnNb_1.5O₇ (BZN) films. (Bi_1.5Zn_0.5)(Zn_0.4Nb_1.43Ti_0.3O₇) film deposited on Pt/Ti/SiO₂/Si substrate by pulsed laser deposition at room temperature exhibits high dielectric constant of 73 at 100 kHz, while BZN film shows much lower dielectric constant of 50, respectively. The increasing dielectric constant with increasing Ti substitution can be attributed to the presence of a highly polarizable TiO₆ octahedra and its strong correlation with the NbO₆ octahedra. All room temperature processed ZnO based TFTs using Ti-substituted BZN gate insulator exhibited filed effect mobility of 0.75 cm²/Vs and low voltage device performance less than 2.5 V.     

PMMA–SiO2 hybrid films as gate dielectric for ZnO based thin-film transistors

In this paper we report a low temperature sol–gel deposition process of PMMA–SiO₂ hybrid films, with variable dielectric properties depending on the composition of the precursor solution, for applications to gate dielectric layers in field-effect thin film transistors (FE-TFT). The hybrid layers were processed by a modified sol–gel route using as precursors Tetraethyl orthosilicate (TEOS) and Methyl methacrylate (MMA), and 3-(Trimethoxysilyl)propyl methacrylate (TMSPM) as the coupling agent. Three types of hybrid films were processed with molar ratios of the precursors in the initial solution 1.0: 0.25, 0.50, 0.75: 1.0 for TEOS: TMSPM: MMA, respectively. The hybrid films were deposited by spin coating of the hybrid precursor solutions onto p-type Si (100) substrates and heat-treated at 90 °C for 24 h. The chemical bonding in the hybrid films was analyzed by Fourier Transform Infrared Spectroscopy to confirm their hybrid nature. The refractive index of the hybrid films as a function of the TMSPM coupling agent concentration, were determined from a simultaneous analysis of optical reflectance and spectroscopic ellipsometry experimental data. The PMMA–SiO₂ hybrid films were studied as dielectric films using metal-insulator-metal structures. Capacitance–Voltage (C–V) and current–voltage (I–V) electrical methods were used to extract the dielectric properties of the different hybrid layers. The three types of hybrid films were tested as gate dielectric layers in thin film transistors with structure ZnO/PMMA–SiO₂/p-Si with a common bottom gate and patterned Al source/drain contacts, with different channel lengths. We analyzed the output electrical responses of the ZnO-based TFTs to determine their performance parameters as a function of channel length and hybrid gate dielectric layer.     

Top-gate ZnO nanowire transistors and integrated circuits with ultrathin self-assembled monolayer gate dielectric

A novel approach for the fabrication of transistors and circuits based on individual single-crystalline ZnO nanowires synthesized by a low-temperature hydrothermal method is reported. The gate dielectric of these transistors is a self-assembled monolayer that has a thickness of 2 nm and efficiently isolates the ZnO nanowire from the top-gate electrodes. Inverters fabricated on a single ZnO nanowire operate with frequencies up to 1 MHz. Compared with metal-semiconductor field-effect transistors, in which the isolation of the gate electrode from the carrier channel relies solely on the depletion layer in the semiconductor, the self-assembled monolayer dielectric leads to a reduction of the gate current by more than 3 orders of magnitude.     

Characteristics of SiO2/Si3N4/SiO2 stacked-gate dielectrics obtained via atomic-layer deposition

An interpoly-stacked dielectric film with a SiO2/Si3N4/SiO2/Si (ONO) structure was prepared via the atomic-layer deposition method. The multilayer structure of the ONO film with triple interfaces was investigated via medium-energy ion scattering (MEIS). A few defects in the interface layer of the ONO structure were detected. From the X-ray photoelectron spectroscopy (XPS) results, it was presumed that the interface layer with defects in the MEIS result is due to the formation of an oxynitride layer on the unstable and rougher Si3N4 layer via. By measuring the I-V characteristics, the leakage current density and breakdown field of the ONO film were determined to be 3.4 x 10(-9) A/cm2 and 10.86 MV/cm, respectively. By estimation the C-V curve, the flat band (V(FB)) of the ONO film shifted to a negative voltage (-1.14 V), the dielectric constant (K(ONO)) of the ONO film was 5.79, and the effective interface-trapped charge density of the ONO film was about 4.96 x 10(11)/cm2.     

Graphene gate electrode for MOS structure-based electronic devices

We demonstrate that the use of a monolayer graphene as a gate electrode on top of a high-κ gate dielectric eliminates mechanical-stress-induced-gate dielectric degradation, resulting in a quantum leap of gate dielectric reliability. The high work function of hole-doped graphene also helps reduce the quantum mechanical tunneling current from the gate electrode. This concept is applied to nonvolatile Flash memory devices, whose performance is critically affected by the quality of the gate dielectric. Charge-trap flash (CTF) memory with a graphene gate electrode shows superior data retention and program/erase performance that current CTF devices cannot achieve. The findings of this study can lead to new applications of graphene, not only for Flash memory devices but also for other high-performance and mass-producible electronic devices based on MOS structure which is the mainstream of the electronic device industry.     

Improved Morphology and Performance of Solution‐Processed Metal‐Oxide Thin‐Film Transistors Due to a Polymer Based Interface Modifier

The influence of a polymer interface modifier on the performance of solution‐processed indium‐based metal‐oxide (MO) thin‐film transistors (TFTs) is investigated. We use the polymer ethoxylated polyethylenimine (PEIE). Compared to a reference sample this modification enhances the mobility by a factor of four, clearly reduces the contact and the sheet resistance, and decreases the charge carrier activation energy by about 20%. The improved electrical performance originates from both a reduced contact and a reduced sheet resistance of the TFTs. The molecular dipole of PEIE reduces the work function of the electrodes. Adversely the dipole enhances the off current and the trap density at the semiconductor/dielectric interface for bottom‐contact transistors with small channel length. The substrate becomes highly polar with a PEIE‐treatment. Accordingly, topographical studies of bottom‐contact TFTs show a very similar MO film morphology on the electrodes and in the channel for modified TFTs, whereas in the untreated samples the film has a higher roughness on the electrodes than in the channel. TFTs in top‐contact configuration with the polymer interface layer at the dielectric/semiconductor interface also show higher mobility compared to the reference MOTFTs which displays that the improved performance is due to the improved morphology of the MO film.     

Low-voltage-driven pentacene thin-film transistors with cross-linked poly(4-vinylphenol)/high-k Bi55b3O15 hybrid dielectric for phototransistor

This paper describes the fabrication of pentacene thin-film transistors (TFTs) with an organic/inorganic hybrid gate dielectric, consisting of cross-linked poly(4-vinylphenol) (PVP) and Bi5Nb3O15. A 300-nm-thick Bi5Nb3O15 dielectric film, grown at room temperature, exhibits a high dielectric constant (high-k) value of 40 but has an undesirable interface with organic semiconductors (OSC). To form better interfaces with OSC, a cross-linked PVP dielectric was stacked on the Bi5Nb3O15 dielectric. It is shown that, with the introduction of a hybrid dielectric, our devices not only can be operated at a low voltage (- -5 V) but also have improved electrical characteristics and photoresponse, including a field-effect mobility of 0.72 cm2/V x s, current sub-threshold slopes of 0.29 V/decade, and a photoresponse of 4.84 at a gate bias V(G) = 0 V under 100 mW/cm2 AM 1.5 illumination.