基于时间域读出的大动态范围CMOS图像传感器

设计了一款基于时间域读出的大动态范围CMOS图像传感器。传感器基于一种新型的结构,其可在时间域下探测高输入光强,在模拟域下探测低输入光强。该设计在传统电容反馈式跨阻放大器(CTIA)的基础上,新增了时间域测量电路,在不改变原有积分过程的同时可实现连续的大动态范围。基于0.35μm,5V-CMOS工艺进行了256×1线列CMOS图像传感器流片,光电二极管面积为22.5μm×22.5μm,并对器件的光电特性进行了后仿真验证。仿真测试结果表明,基于时间域读出的图像传感器可实现96dB的大动态范围,且时间域和模拟域的两路输出信号可同步输出,功耗为7.98mW。     

微光CMOS图像传感器读出电路研究

高性能的信号读出电路是微光CMOS图像传感器的重要组成部分,如何降低读出电路噪声,提高读出电路输出信号的信噪比成为读出电路设计的重点。本文设计了一种高增益低噪声的电容反馈跨阻放大器CTIA（Capacitive Trans impedanceAmplifier）与相关双采样电路CDS （Correlated Double Sampling）相结合的微光探测器读出电路。在CTIA电路中,采用T网络电容实现fF级的积分电容,并通过增益开关控制,来达到对微弱光信号的高增益低噪声读出。采用CSMC公司的0.5μm标准CMOS工艺库对电路进行流片,测试结果表明：在光电流信号为20~300 pA范围内,积分时间为20μs,该电路功能良好,信噪比（SNR）达到10,能应用于微光CMOS图像传感器。     

高光谱成像用高帧频CMOS图像传感器北大核心

针对高帧频、全局曝光和光谱平坦等成像应用需求,设计了一款高光谱成像用CMOS图像传感器。其光敏元采用PN型光电二极管,读出电路采用5T像素结构。采用列读出电路以及高速多通道模拟信号并行读出的设计方案来获得低像素固定图像噪声(FPN)和非均匀性抑制。芯片采用ASMC 0.35μm三层金属两层多晶硅标准CMOS工艺流片,为了抑制光电二极管的光谱干涉效应,后续进行了光谱平坦化VAE特殊工艺,并对器件的光电性能进行了测试评估。电路测试结果符合理论设计预期,成像效果良好,像素具备积分可调和全局快门功能,最终实现的像素规模为512×256,像元尺寸为30μm×30μm,最大满阱电子为400 ke^(-),FPN小于0.2%,动态范围为72 dB,帧频为450 f/s,相邻10 nm波段范围内量子效率相差小于10%,可满足高光谱成像系统对CMOS成像器件的要求。     

一种0.8V 2.4μA CMOS全差分放大器

基于0.25μm标准CMOS工艺,采用0.8V开关电容共模反馈电路技术和PMOS衬底驱动技术提出了一种新型0.8V 2.4μA全差分放大器.在0.8V单电源电压下,全差分放大器的直流开环增益为63.8dB,相位裕度为60度,单位增益带宽为7.4MHz,输出电压范围为18～791mV,其中新型模拟开关的输入/输出电压范围为0～800mV,整个放大器的电源电流为2.4μA,版图面积为410×360μm2.     

多分辨率高速线列CMOS图像传感器设计

设计并验证了一款可选分辨率、高速1 024线列CMOS图像传感器。为了优化列总线读出速率,芯片采用总线分割技术以减小总线寄生电容,有效提升了信号读出速率。传感器具有4种可选择分辨率功能,使其具有更高的帧频。设计的芯片采用0.5μm标准CMOS工艺成功流片,验证了设计的正确性。测试结果表明：满阱容量为4.76 Me^-/像素,动态范围为75 dB;在128分辨率下,帧频能达到36 000 frames/s。     

一种15ns的1兆位CMOS SRAM

我们研制了一种256k字×4位结构体1兆位CMOS静态存贮器，它的制造是采用0．8μm双层多晶、双层铝、双阱CMOS工艺技术。其单元尺寸小：5．2μm×8．5μm，芯片尺寸为6．15mm×15.21mm。通过采用新的电路技术，得到了15ns的快速存取时间。该技术为。一个PMOS负载译码器，一个三级动态增益控制读出放大器，并结合补偿技术及反馈电容技术。电路的动态电流较低，在20MHz时为50mA，静态电流也低，对TTL为15mA，而CMOS则为2μA。     

低照度CMOS图像传感器设计与实现

设计了一种基于电容反馈跨阻放大器型（Capacitive Trans-impedance Amplifier,CTIA）像元电路与双采样（Delta Double Sampling,DDS）的低照度CMOS图像传感器系统。采用CTIA像元电路提供稳定的光电二极管偏置电压以及高注入效率,完成在低照度情况下对微弱信号的读取;同时采用数字DDS结构,通过在片外实现像元积分信号与复位信号的量化结果在数字域的减法,达到抑制CMOS图像传感器中固定图案噪声的目的,进一步提高低照度CIS的成像质量。基于0.35 m标准CMOS工艺对此基于CTIA像元电路的CMOS图像传感器芯片进行流片,像元阵列为256256,像元尺寸为16 m16 m。测试结果表明该低照度CMOS图像传感器系统可探测到0.05 lx光照条件下的信号。     

1024×1024全帧CCD器件

采用2μm设计规则,在2μm工艺线上,成功研制了1 024×1 024全帧CCD器件。该1 024×1 024全帧CCD器件的有效像元数为1 024×1 024,像元尺寸为11μm×11μm,有效光敏面积为11.3mm×11.3mm,光响应波长范围为400～1 100nm。成像区域横向分为2个区,纵向分为2个区,可由1路、2路和4路输出,有9种读出模式。该器件具有2×2的像元合并功能,能作为512×512（像元尺寸为22μm×22μm）和规格的器件使用。该器件数据速率为4×40M,数据速率高。器件采用MPP工作模式,暗电流低;采用薄栅氧化,具有100krad（Si）抗辐照能力;适合在高温、辐照环境和微光环境下成像应用。     

GaN紫外焦平面CTIA结构读出电路小面积设计及仿真

随着GaN紫外焦平面的发展,焦平面的阵列规模越来越大,单元探测器的面积越来越小,对GaN紫外焦平面的读出电路进行设计,实现读出电路单元面积为37μm×37μm,阵列规模为8×8元.本设计采用电容反馈互阻抗放大器(CITA)结构作为输入级,列共用方式的采样保持电路,源级跟随器作为输出级,用移位寄存器来控制行、列选通并控制电路工作的时序.本文的整个电路设计基于Cadence设计平台,对电路进行了Spectre仿真,面阵的工作状况良好,保持良好的线性.     

一种6T像素全局曝光CMOS图像传感器

提出了一种基于6T像素结构的全局曝光CMOS图像传感器。通过采用PPD结构的6T像素、高复位电平和低阈值器件,提高了动态范围,并优化设计了像素单元的版图,使之获得较高的填充系数;模拟读出电路部分,通过采用双采样、增益放大和减小列级固定模式噪声(FPN)处理,以及对列选控制电路进行优化,减小了对全局PGA的运放设计要求。芯片的工作频率为20MHz,动态范围为66dB,实现了全局曝光方式CMOS图像传感器的设计。     

CMOS有源像素传感器特性分析与优化设计

设计了一个三管有源像素和其用开关电容放大器实现的双采样读出电路.该电路被嵌入一64×64像素阵列CMOS图像传感器,在Chartered公司0.35μm工艺线上成功流片.在8μm×8μm像素尺寸下实现了57%的填充因子.测得可见光响应灵敏度为0.8V/(lux·s),动态范围为50dB.理论分析和实验结果表明随着工艺尺寸缩小,像素尺寸减小会使光响应灵敏度降低.在深亚微米工艺条件下,较深的n阱/p衬底结光电二极管可以提供合理的填充因子和光响应灵敏度.     

Research on Column FPN and Black Level Calibration in Large Array CMOS Image Sensor

A technical investigation, research and im-plementation is presented to correct column fixed pattern noise and black level in large array Complementary metal oxide semiconductor (CMOS) image sensor. Through making a comparison among reported solution, and give large array CMOS image sensor design and considerations, according to our previous analysis on non-ideal factor and error source of piecewise Digital to analog converter (DAC) in multi-channels, an improving accurate piecewise DAC with adaptive switch technique is developed. The research theory has verified by a high dynamic range and low column Fixed pattern noise (FPN) CMOS image sensor prototype chip, which consisting of 8320×8320 pixel array was designed and fabricated in 55nm CMOS 1P4M standard process. The chip active area is 48mm×48mm with a pixel size of 5.7μm×5.7μm. The measured results achieved a high intrinsic dynamic range of 75dB, a low FPN and black level of 0.06％, a low photo response non-uniformity of 1.5％ respectively, and an excellent raw sample image taken by the prototype sensor.     

A novel monolithic ultraviolet image sensor based on a standard CMOS process

We present a monolithic ultraviolet(UV) image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists of a CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16×16 image sensor prototype chip is implemented in a 0.18μm standard CMOS logic process.The pixel and image sensor were measured. Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/(mJ/cm~2) and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications.     

A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitor

In a CMOS image sensor featuring a lateral overflow integration capacitor in a pixel, which integrates the overflowed charges from a fully depleted photodiode during the same exposure, the sensitivity in nonsaturated signal and the linearity in saturated overflow signal have been improved by introducing a new pixel circuit and its operation. The floating diffusion capacitance of the CMOS image sensor is as small as that of a four transistors type CMOS image sensor because the lateral overflow integration capacitor is located next to the reset switch. A 1/3-inch VGA format (640/sup H//spl times/480/sup V/ pixels), 7.5/spl times/7.5 /spl mu/m/sup 2/ pixel color CMOS image sensor fabricated through 0.35-/spl mu/m two-poly three-metal CMOS process results in a 100 dB dynamic range characteristic, with improved sensitivity and linearity.     

An Improved Global Shutter Pixel with Extended Output Range and Linearity of Compensation for CMOS Image Sensor

An improved global shutter pixel structure with extended output range and linearity of compensation is proposed for CMOS image sensor. The potential switching of the sample and hold capacitor bottom plate outside the array is used to solve the problem of the serious swing limitation, which will attenuate the dynamic range of the image sensor. The non-linear problem caused by the substrate bias effect in the output process of the pixel source follower is solved by using the mirror FD point negative feedback self-establishment technology outside the array. The approach proposed in this paper has been verified in a global shutter CMOS image sensor with a scale of 1024×1024 pixels. The test results show that the output range is expanded from 0.95V to 2V, and the error introduced by the nonlinearity is sharply reduced from 280mV to 0.3mV. Most importantly, the output range expansion circuit does not increase the additional pixel area and the power consumption. The power consumption of linearity correction circuit is only 23.1μW, accounting for less than 0.01％ of the whole chip power consumption.     

一个128×128CMOS快照模式焦平面读出电路设计

本文介绍了一个工作于快照模式的CMOS焦平面读出电路新结构——DCA(Direct-injection Charge Amplifier)结构.该结构像素电路仅用4个MOS管,采用特殊的版图设计并用PMOS管做复位管,既可保证像素内存储电容足够大,又可避免复位电压的阈值损失,从而提高了读出电路的电荷处理能力.由于像素电路非常简单,且该结构能有效消除列线寄生电容C_bus的影响,因此该结构非常适用于小像素、大规模的焦平面读出电路.采用DCA结构和1.2μm双硅双铝(DPDM-Double-Poly Double-Metal)标准CMOS工艺设计了一个128×128规模焦平面读出电路试验芯片,其像素尺寸为50×50μm²,电荷处理能力达11.2pC.本文详细介绍了该读出电路的体系结构、像素电路、探测器模型和工作时序,并给出了精确的HSPICE仿真结果和试验芯片测试结果.     

New signal readout method for ultrahigh-sensitivity CMOS image sensor

We propose a new signal readout method that uses a charge-transfer circuit. Its application is to an ultrahigh-sensitivity CMOS image sensor on which an avalanche-mode photoconductive film is overlaid. The charge-transfer circuit makes it possible to obtain high signal-to-noise ratio features by transferring signal charges accumulated in each photodiode to a parasitic capacitance that is small compared with the photodiode capacitance. A 138 /spl times/ 138 passive-pixel prototype sensor that had the charge-transfer circuit in each column was fabricated and tested. The prototype's column-to-column fixed-pattern noise and random noise were, respectively, 56.7 and 58.4 dB below the saturation signal level, which demonstrated its potential as a signal readout circuit for a next-generation ultrahigh-sensitivity CMOS image sensor.     

基于相对比率的高帧频图像采集器设计与实现

为了在机器视觉应用中是实现高动态范围（high dynamic range,HDR）图像采集,提出了一种基于检测像素相对比率的新型图像采集系统。提出的图像采集器使用全差分电路检测信号比,由基于数字计数器的紧凑列并行读出电路捕捉像素的脉冲宽度调制输出。并设计了相应的光电流比检测像素方法,能独立地捕捉局部场景特征。实验结果显示提出的COMS图像传感器性能较好,当标称帧频为9600帧/秒时,提出的32×32像素阵列原型CMOS图像传感器消耗了4 mW的功率;当最大帧频为24000帧/秒时,此图像传感器消耗了6.8 mW的功率。     

新型电流镜积分红外量子阱探测器读出电路的设计分析

设计了一种偏压可调电流镜积分(Current Mirroring Integration,CMI)红外量子阱探测器焦平面CMOS读出电路。该电路适应根据偏压调节响应波段的量子阱探测器,其中探测器偏压从0.61 V到1.55V范围内可调。由于CMI的电流反馈结构,使得输入阻抗接近0,注入效率达0.99;且积分电容可放在单元电路外,从而可以在一定的单元面积下,增大积分电容,提高了电荷处理能力和动态范围;为提高读出电路的性能,电路加入撇除(Skimming)方式的暗电流抑制电路。采用特许半导体(Chartered)0.35 m标准CMOS工艺对所设计的电路(16×1阵列)进行流片,测试结果表明:在电源电压为3.3V,积分电容为1.25pF时,电荷处理能力达到1.3×107个电子;输出摆幅达到1.76V;功耗为25mW;动态范围为75dB;测试结果显示CMI可应用于高性能FPA。