A 4.2-ps ECL ring-oscillator in a 285-GHz fMAX SiGetechnology

This letter reports on the room temperature operation of a conventional SiGe bipolar ECL ring oscillator with a minimum stage delay of 4.2 ps for ~250 mV single ended voltage swing. To our knowledge, this is the lowest reported delay for a gate fabricated using transistor devices. The circuit uses 0.12 × 2 μm² emitter size SiGe n-p-n transistors with a room temperature f_T of 207 GHz and f_MAX (unilateral gain extrapolation) of 285 GHz. The ring oscillator was studied as a function of various device and circuit parameters and it was found that minimum delay is more dependent on the parasitic resistance and capacitance in the n-p-n device than on pure transit time across the device     

InAlAs/InGaAs/InP MODFET's with uniform threshold voltage obtainedby selective wet gate recess

Excellent uniformity in the threshold voltage, transconductance, and current-gain cutoff frequency of InAlAs/InGaAs/InP MODFETs has been achieved using a selective wet gate recess process. An etch rate ratio of 25 was achieved for InGaAs over InAlAs using a 1:1 citric acid:H₂O₂ solution. By using this solution for gate recessing, the authors have achieved a threshold voltage standard deviation of 15 mV and a transconductance standard deviation of 15 mS/mm for devices across a quarter of a 2-in-diameter wafer. The average threshold voltage, transconductance, and current-gain cutoff frequency of 1.0-μm gate-length devices were -234 mV, 355 mS/mm, and 32 GHz, respectively     

Highly uniform N-InAlAs/InGaAs HEMT's on a 3-in InP substrate usingphotochemical selective dry recess etching

Large-area photochemical selective dry etching has been developed for use in InGaAs/InAlAs heterojunction fabrication involving CH₃ Br gas and a low-pressure mercury lamp. The etch rate of the InGaAs layer was 17 nm/min and the etch ratio of InGaAs to InAlAs was around 25 to 1. The dry recess was performed for N-InAlAs/InGaAs HEMT's on a 3-in wafer using photochemical etching. The standard deviation of the threshold voltage across the wafer was 18 mV at a threshold voltage of -0.95 V, and the transconductance of 456 mS/mm was obtained for a 1.1-μm-long gate within a standard deviation of 14.9 mS/mm     

High-performance 0.1-μm gate enhancement-mode InAlAs/InGaAsHEMT's using two-step recessed gate technology

Novel approach for making high-performance enhancement-mode InAlAs/InGaAs HEMT's (E-HEMT's) is described for the first time. Most important issue for the fabrication of E-HEMT's is the suppression of the parasitic resistance due to side-etching around the gate periphery during gate recess etching. Two-step recessed gate technology is utilized for this purpose. The first step of the gate recess etching removes cap layers wet-chemically down to an InP recess-stopping layer and the second step removes only the recess-stopping layer by Ar plasma etching. The parasitic component for source resistance is successfully reduced to less than 0.35 Ω·mm. Etching selectivities for both steps are sufficient not to degrade uniformity of devices on the wafer. The resulting structure achieves a positive threshold voltage of 49.0 mV with high transconductance. Due to the etching selectivity, the standard deviation of the threshold voltage is as small as 13.3 mV on a 3-in wafer. A cutoff frequency of 208 GHz is obtained for the 0.1-μm gate E-HEMT's. This is therefore one of the promising devices for ultra-high-speed applications     

Threshold voltage uniformity and characterization of microwaveperformance for GaAs/AlGaAs high electron-mobility transistors grown onSi substrates

We report on DC and microwave characteristics for high electron-mobility transistors (HEMT's) grown on Si substrates by metal-organic chemical vapor deposition (MOCVD). Threshold voltage (V _th) distribution in a 3-in wafer shows standard deviation of V_th (σV_th) of 36 mV with V_th of -2.41 V for depletion mode HEMT's/Si and σV_th of 31 mV with V_th of 0.01 V for enhancement mode, respectively. The evaluation of V_th in a 1.95×1.9 mm² area shows high uniformity for as-grown HEMT's/Si with σV_th of 9 mV for V_th of -0.10 V, which is comparable to that for HEMT's/GaAs. Comparing the V_th distribution pattern in the area with that for annealed HEMT's/Si, it is indicated that the high uniformity of V_th is obtained irrelevant of a number of the dislocations existing in the GaAs/Si. From microwave characteristic evaluation for HEMT's with a middle-(10~50 Ω·cm) and a high-(2000~6000 Ω·cm) resistivity Si substrate using a new equivalent circuit model, it is demonstrated that HEMT's/Si have the disadvantage for parasitic capacitances and resistances originated not from the substrate resistivity but from a conductive layer at the Si-GaAs interface. The parasitic parameters, especially the capacitances, can be overcome by the reduction of electrode areas for bonding pads and by the insertion of a dielectric layer under the electrode, which bring high cut-off frequency (f_T) and maximum frequency of operation (f_max) of 24 GHz for a gate length of 0.8 (μm). These results indicate that HEMT's/Si are sufficiently applicable for IC's and discrete devices and have a potential to be substituted for HEMT's/GaAs     

Enhancement-mode high electron mobility transistors (E-HEMTs)lattice-matched to InP

The fabrication and characterization of high-speed enhancement-mode InAlAs/InGaAs/InP high electron mobility transistors (E-HEMTs) have been performed. The E-HEMT devices were made using a buried-Pt gate technology. Following a Pt/Ti/Pt/Au gate metal deposition, the devices were annealed in a nitrogen ambient, causing the bottom Pt layer to sink toward the channel. This penetration results in a positive shift in threshold voltage. The dc and RF performance of the devices has been investigated before and after the gate annealing process. In addition, the effect of the Pt penetration was investigated by fabricating two sets of devices, one with 25 nm of Pt as the bottom layer and the other with a 5.0 nm bottom Pt layer. E-HEMTs were fabricated with gate lengths ranging from 0.3 to 1.0 μm. A maximum extrinsic transconductance (g_mext) of 701 mS/mm and a threshold voltage (V_T) of 167 mV was measured for 0.3 μm gate length E-HEMTs. In addition, these same devices demonstrated excellent subthreshold characteristics as well as large off-state breakdown voltages of 12.5 V. A unity current-gain cutoff frequency (f _t) of 116 GHz was measured as well as a maximum frequency of oscillation (f_max) of 229 GHz for 0.3 μm gate-length E-HEMTs     

High threshold uniformity, millimeter-wavep+-GaInAs/n-AlInAs/GaInAs JHEMTs

High threshold voltage uniformity p⁺-GaInAs/n-AlInAs/GaInAs millimeter-wave junction-modulated HEMT's are reported. Devices with 0.2 μm gatelength exhibit a standard deviation in threshold voltage of 13.7 mV across a 1×1.5 in² wafer. The uniformity is achieved in devices which exhibit high DC transconductance (520 mS/mm), high unity-gain cut-off frequencies: f_T (105 GHz) and f_max (exceeding 200 GHz), and low minimum noise figure (0.45 dB) with high associated gain (14.5 dB) at 12 GHz     

Recovery of low temperature electron trapping in AlGaAs/InGaAsPM-HEMTs due to impact-ionization

The dc behavior of AlGaAs/InGaAs PM-HEMTs has been Investigated at a low temperature. Two different failure modes have been identified according to bias conditions, consisting of: (a) a dramatic collapse in the drain current I_D, and (b) a considerable shift in the threshold voltage V_T. I_D decrease is due to trapping of electrons in deep levels in the gate-drain region, while trapping under the gate is responsible for V_T shift. At high V_DS a recovery of the dc device characteristics is observed, due to impact-ionization phenomena     

双多晶硅栅SOI MOS器件的研究

采用多晶硅栅全耗尽ＣＭＯＳ／ＳＩＭＯＸ工艺成功研制出多晶硅栅器件,其中Ｎ＋栅ＮＭＯＳ管的阈值电压为０．４５Ｖ,Ｐ＋栅ＰＭＯＳ管的阈值电压为－０．２２Ｖ,在１Ｖ和５Ｖ电源电压下多晶硅栅环振电路的单级门延迟时间分别为１．７ｎｓ和３５０ｐｓ,双多晶硅栅ＳＯＩ技术将是低压集成电路的一种较好选择。     

Improvement in threshold voltage control by minimizing boronpenetration in a LV-GCMOS technology

Maintaining tight threshold voltage (V_T) control for a low-voltage CMOS process is critical due to the large impact of V_T on circuit performance at low power supply voltages. In this paper, PMOS V_T was shown to be sensitive to poly gate thickness and BF₂⁺ source/drain implant energy. This data helped identify boron penetration as a prime contributor to PMOS threshold voltage variation. SIMS measurements were used to investigate boron diffusion through the poly gate at various stages in the process flow. These SIMS profiles pointed to the low-temperature thermal cycle of the nitride spacer deposition as a key step which influenced the amount of boron penetration and thus the final device threshold voltage. Experimental evidence shows that the temperature gradient across the nitride spacer deposition furnace causes a variable amount of boron penetration resulting in a large variation in PMOS V_T. We adopted a process flow change which virtually eliminated boron penetration and significantly reduced the sensitivity of the devices to manufacturing variations. Threshold voltage variation was reduced by a factor of two     

Lateral and Vertical Scaling of $hbox{In}_{0.7} hbox{Ga}_{0.3}hbox{As}$ HEMTs for Post-Si-CMOS Logic Applications

In this paper, we have experimentally investigated the impact of lateral and vertical scaling of In_0.7Ga_0.3As high-electron-mobility transistors (HEMTs) onto their logic performance. We have found that reducing the In_0.52Al_0.48As insulator thickness results in much better electrostatic integrity and improved short-channel behavior down to a gate length of around 60 nm. Our nearly enhancement-mode 60-nm HEMTs feature V_T = -0.02 V, DIBL = 93 mV/V, S = 88 mV/V, and I_ON/I_OFF = 1.6 times10⁴, at V _DD = 0.5 V. We also estimate a gate delay of CV/I = 1.6 ps at V_DD = 0.5 V. We have benchmarked these devices against state-of-the-art Si CMOS. For the same leakage current, which includes the gate leakage current, the InGaAs HEMTs exhibit 1.2times more current drive (I_ON) than the state-of-the-art 65-nm low-power CMOS technology at V _DD = 0.5 V.     

0.3-μm gate-length enhancement mode InAlAs/InGaAs/InPhigh-electron mobility transistor

The fabrication and performance of ultra-high-speed 0.3-μm gate-length enhancement-mode high-electron-mobility transistors (E-HEMT's) are reported. By using a buried platinum-gate technology and incorporating an etch-stop layer in the heterostructure design, submicron E-HEMT devices exhibiting both high-threshold voltages and excellent threshold voltage uniformity have been achieved. The devices demonstrate a threshold voltage of +171 mV with a standard deviation of only 9 mV. In addition, a maximum DC extrinsic transconductance of 697 mS/mm is measured at room temperature. The output conductance is 22 mS/mm, which results in a maximum voltage gain (g_m/g₀ ) of 32. The devices show excellent RF performance, with a unity current-gain cutoff frequency (f_t) of 116 GHz and a maximum frequency of oscillation (f_max) of 229 GHz. To the best of the authors' knowledge, these are the highest reported frequencies for lattice-matched E-HEMT's on InP     

Self-aligned half-micrometer Silicon MASFET's with metallic amorphous Silicon gate

Ternary metallic amorphous silicon (a-Si-Ge-B), having a high barrier height feature with crystalline semiconductors is applied to the gate metal of Si MESFET's. A submicrometer gate length is successfully fabricated using a self-aligned technology and a conventional photolithography. A large transconductance above 130 mS/mm under the normally-OFF state and a small standard deviation of threshold voltage less than 11 mV are realized for a 0.5-µm gate-length device across a 4-in-diameter wafer. A minimum delay time of 114 ps/gate with an associated switching energy of 1.6 pJ and a minimum switching energy of 3.3 fJ with a delay time of 26 ns/gate are attained by a 21-stage ring oscillator with E/R direct-coupled FET logic circuits.     

High-performance GaAs MESFETs with advanced LDD structure fordigital, analog, and microwave applications

GaAs MESFETs with advanced LDD structure have been developed by using a single resist-layered dummy gate (SRD) process. The advanced LDD structure suppresses the short channel effects, and reduces source resistance, while maintaining a moderate breakdown voltage. The 0.3-μm enhancement-mode devices exhibit a transconductance of 420 mS/mm, while the breakdown voltage of the depletion-mode device (V_th=-500 mV) is larger than 6 V. The standard deviation of the threshold voltage for 0.3-μm devices is less than 30 mV across a 3-in wafer. The 0.3-μm devices exhibit an average cutoff frequency of 47.2 GHz with a standard deviation of 1.3 GHz across a 3-in wafer. The cutoff frequency of a 0.15-μm device is as high as 72 GHz. D-type flip-flop circuits for digital IC applications and preamplifier for analog IC applications fabricated with 0.3-μm gate length devices operate above 10 Gb/s. In addition, the 0.3-μm devices also show good noise performance with a noise figure of 1.1 dB with associated gain of 6.5 dB at 18 GHz. These results demonstrate that GaAs MESFETs with an advanced LDD structure are quite suitable for digital, analog, microwave, and hybrid IC applications     

High-performance dual-gate CMOS utilizing a novel self-alignedpocket implantation (SPI) technology

A self-aligned pocket implantation (SPI) technology is discussed. This technology features a localized pocket implantation using the gate and drain electrodes (TiSi₂ film) as well as self-aligned masks. The gate polysilicon is patterned by KrF excimer laser lithography. The measured minimum gate length L_g (the physical gate length) is 0.21 μm for both N- and P-MOSFETs. A newly developed photoresist was used to achieve less than quarter-micrometer patterns. This process provides high punchthrough resistance and high current driving capability even in such a short channel length. The subthreshold slope of the 0.21-μm gate length is 76 mV/dec for N-MOSFETs and 83 mV/dec for P-MOSFETs. The SPI technology maintains a low impurity concentration in the well (less than 5×10 ¹⁶ cm^-3). The drain junction capacitance is decreased by 36% for N-MOSFETs and by 41% for P-MOSFETs, compared to conventional LDD devices, which results in high-speed circuit operation. The delay time per stage of a 51-stage dual-gate CMOS ring oscillator is 50 ps with a supply voltage of 3.3 V and a gate length of 0.36 μm, and 40 ps with a supply voltage of 2.5 V and a gate length of 0.21 μm     

Application of a solution proximity annealing technique for fabrication of ion-implanted GaAs integrated circuits

A technique for capless annealing of ion-implanted GaAs, using an arsenic-saturated solution of Sn and Ga in close proximity to the wafer, has been applied to the fabrication of GaAs integrated circuits. The IC processing technology utilizes a self-aligned T-shaped refractory gate approach for the fabrication of both enhancement- and depletion-mode MESFET's. Using the solution proximity annealing technique, excellent threshold voltage uniformities (standard deviation = 26 mV) have been obtained for enhancement-mode devices using commercial substrates. This process technology has resulted in the fabrication of divide-by-16 circuits in both SDFL and DCFL logic implementations, as well as enhancement/depletion (E/D) ring oscillators (Lg= 2 µm) with propagation delays as low as 45 ps/gate and concomitant power consumptions of 2 mW/gate. This technique can also be applied, by suitable choice of the solution constituents, to capless annealing of other III-V semiconductors such as InP and GaInAs.     

Hydrogen-induced piezoelectric effects in InP HEMT's

In this letter, we have investigated hydrogen degradation of InP HEMT's with Ti/Pt/Au gates. We have found that V_T shifts negative after exposure to hydrogen, and exhibits an L_G and orientation dependence. We postulate that ΔV_T is at least in part due to the piezoelectric effect. Hydrogen exposure leads to the formation of TiH_x, producing compressive stress in the gate. This stress induces a piezoelectric charge distribution in the semiconductor that shifts the threshold voltage. We have independently confirmed TiH_x formation under our experimental conditions through Auger measurements. Separate radius-of-curvature measurements have also independently confirmed that Ti/Pt films become compressively stressed relative to their initial state after H₂ exposure     

InGaAs metal-semiconductor field-effect transistor withLangmuir-Blodgett deposited gate structure

A high-transconductance n-channel, depletion-mode InGaAs metal-semiconductor field-effect transistor (MESFET) with a Langmuir-Blodgett deposited gate fabricated on organometallic chemical vapor deposition (OMCVD)-grown InGaAs lattice matched to InP is reported. The fabrication process is similar to epitaxial GaAs FET technology and is suitable for making optoelectronic integrated circuits (OEICs) for long-wavelength fiber-optic communications systems. Devices with 1-μm gate and 6×10¹⁶ channel doping achieved 162-mS/mm extrinsic transconductance and -1.8-V pinch-off voltage. The effective saturation velocity of electrons in the channel was measured to be between 3.5 and 3.9×10⁷ cm/s. The drain current ( I_dss), 300 mA/mm at V_ds=2.5 V, is the highest current capability reported for depletion-mode InGaAs MESFET devices with low pinch-off voltages     

单片集成GaAs增强／耗尽型赝配高电子迁移率晶体管

介绍了单片集成GaAs增强／耗尽型赝配高电子迁移率晶体管（PHEMT）工艺。借助栅金属的热处理过程,形成了热稳定性良好的Pt／Ti／Pt／Au栅。AFM照片结果表明Pt金属膜表面非常平整,2nm厚度膜的粗糙度RMS仅为0．172nm。通过实验,我们还得出第一层Pt金属膜的厚度和退火后的下沉深度比大概为1：2。制作的增强型／耗尽型PHEMT的闽值电压（定义于1mA／mm）、最大跨导、最大饱和漏电流密度、电流增益截止频率分别是＋0．185／-1．22V、381．2／317．5mS／mm、275／480mA／mm、38／34GHz。增强型器件在4英寸圆片上的阈值电压标准差为19mV。     

InGaP/InGaAs doped-channel direct-coupled field-effect transistors logic with low supply voltage

InGaP/InGaAs doped-channel direct-coupled field-effect transistor logic (DCFL) with relatively low supple voltage is demonstrated by two-dimensional analysis. In the integrated enhancement/depletion-mode transistors, subband and two-dimensional electron gas (2DEG) are formed in the InGaAs strain channels, which substantially increase the channel concentration and decrease the drain-to-source saturation voltage. The integrated devices show high turn-on voltage, high transconductance, broad gate voltage swing, and excellent high frequency performance, simultaneously. Furthermore, the integrated devices exhibit large noise margins for DCFL application with low supply voltage of 1.5 V attributed from the relatively small saturation voltages of the studied integrated devices.