An STS-N byte-interleaving multiplexer/scrambler anddemultiplexer/descrambler architecture and its experimental OC-48implementation

The authors present a byte-interleaving architecture for generating higher-order signals in the synchronous optical network (SONET) digital hierarchy and report on the implementation and system performance results of an experimental 2.488 Gbit/s SONET STS-3c to STS-48 (OC-48) byte multiplexer/scrambler and STS-48 (OC-48) to STS-3c byte demultiplexer/descrambler. The proper operation of the byte multiplexer and demultiplexer has been verified in an OC-48 experiment with a bit error rate (BER) of less than 10^-14. It is shown that the byte-interleaving architecture leads to a simple and modular implementation of higher-rate interfaces (such as OC-192 at 9.95 Gbit/s) using state-of-the-art technologies     

2.5Gb/s SDH/SONET传送开销处理器芯片实现

设计了一种2.5Gb/s同步光纤网络SDH/SONET中传送开销处理器芯片.采用双向4路总线流水线结构,77.76MHz的系统时钟,即可实时处理2.5Gb/s的SDH/SONET数据.支持STM-16、4路STM-4和STM-1的再生段开销和复用段开销处理以及STS-48、4路STS-12和STS-3的段开销和线路开销处理.采用TSMC 0.13μm工艺流片,电路规模约48万门,技术指标符合ITU-T标准.     

2.5Gb/s SDH/SONET通路终结芯片设计

设计了一种2.5Gb/s同步光纤网络SDH/SONET中通路终结处理器芯片.采用双向4路总线流水线结构,77.76MHz的系统时钟,可实时处理2.5Gb/s的SDH/SONET数据,终结处理后输出TUG-3/VTG信号.包括通道告警、信号失效检测、性能监测和通道跟踪等.支持STS-48/STM-16、4路STS-12/STM-4和4路STS-3/STM-1的处理.     

A SONET/SDH overhead terminator for STS-3, STS-3C, and STM-1

A single-chip synchronous optical network/synchronous digital hierarchy (SONET/SDH) overhead terminator has been designed for use in STS-3, STS-3C, and STM-1 applications. The chip has been fabricated in a 1 μm CMOS process and contains 220000 transistors. The features supported by the chip include overhead extraction, overhead insertion, alarm detection, alarm generation, performance monitoring, pointer tracking, pointer generation, payload retiming, and payload realignment. The architecture of the IC and several of the chip's more interesting features are described     

OC-12/STS-3c/ATM interface for gigabit network applications

The implementation of an experimental OC-12/STS-3c/ATM transmission interface is described. This interface maps four streams of ATM cell data into the SONET STS-3c transmission format and multiplexes these channels onto a single OC-12 (622 Mbit/s) optical signal. The interface also performs the reverse demultiplexing functions. This application represents the first known demonstration of a 622 Mbit/s ATM workstation interface.<>     

2.5Gb/s SDH/SONET指针处理器芯片实现

提出了一种2.5Gb/s同步光纤网络SDH/SONET中指针处理器芯片实现结构.指针处理器执行指针解释、通路开销性能监测功能,产生新的与系统时钟同步的STM/STS帧.指针解释模块对输入STM/STS通道的H1/H2指针进行解释,支持48通道的指针解释和每个通道的通路开销监测.采用4路总线流水线结构,77.76MHz的系统时钟,即可实时处理2.5Gb/s的SDH/SONET数据.采用TSMC 0.13μm工艺流片,技术指标符合ITU-T标准.     

A SONET STS-3c user network interface integrated circuit

Two different design implementation techniques were used to produce a functionally complex high performance synchronous optical network (SONET) synchronous transmission signal (STS)-3c (155.52 Mb/s) user network interface (UNI) chip in cost-effective 1 μm CMOS technology. The CMOS chip functions as an STS-3c transmitter and receiver and can interface to the STS-3c line in either bit-serial or byte-parallel data format. The transmitter creates a SONET STS-3c frame structure including the necessary framing and control bytes. The receiver performs frame detection, several performance monitoring functions, and payload processor interpretation. In addition to SONET overheads, both the transmitter and receiver provide payload asynchronous transfer mode (ATM) mapping signals to the user. The user can choose between serial operation at 155.52 Mb/s or parallel operation at 19.44 Mbyte/s. Test results show that the experimental integrated circuit performs successfully at serial data rates of up to 300 Mb/s     

SDH/SONET低阶支路VT/TU映射芯片实现

设计了SDH/SONET的低阶支路VT/TU映射芯片,单片实现28通道DS1/VC-11或21通道E1/VC-12到7个VTG/TUG-2的映射及逆映射,或DS1/E1/VC的组合到VTG/TUG-2的混合映射.该芯片带有支路环回和指针处理功能,支持UPSR环形网络拓扑结构.采用TSMC 0.13 μm CMOS工艺流片成功,电路规模约23.7万门.     

A PLL-based 2.5-Gb/s GaAs clock and data regenerator IC

A GaAs IC that performs clock recovery and data retiming functions in 2.5-Gb/s fiber-optic communication systems is presented. Rather than using surface acoustic wave (SAW) filter technology, the IC employs a frequency- and phase-lock loop (FPLL) to recover a stable clock from pseudo-random non-return-to-zero (NRZ) data. The IC is mounted on a 1-in×1-in ceramic substrate along with a companion Si bipolar chip that contains a loop filter and acquisition circuitry. At the synchronous optical network (SONET) OC-48 rate of 2.488 Gb/s, the circuit meets requirements for jitter tolerance, jitter transfer, and jitter generation. The data input ambiguity is 25 mV while the recovered clock has less than 2° rms edge jitter. The circuit functions up to 4 Gb/s with a 40-mV input ambiguity and 2° RMS clock jitter. Total current consumption from a single 5.2-V supply is 250 mA     

The ATM layer chip: an ASIC for B-ISDN applications

The authors describe the architecture of an experimental research prototype application specific integrated circuit (ASIC) designed to serve as a generic building block of the future broadband integrated services digital network (B-ISDN). The chip performs common asynchronous transfer mode (ATM) layer functions such as cell assembly and cell disassembly. A new media access control (MAC) protocol developed for a broadband customer premises network is also integrated in the chip. The chip interfaces to the B-ISDN through a synchronous optical network (SONET) synchronous transmission signal-3c (STS-3c) framer chip. The ATM layer chip has been designed using 1.2 μm CMOS technology with a die area of 5.4×5.4 mm² and approximately 27000 transistors. Experimental results are described. At the user network interface, the chip can be used to implement broadband terminal adaptors and the network termination. At the broadband local exchange, the chip can be used in the implementation of ATM statistical multiplexers, ATM switch port controllers, etc     

Low-power fully integrated 10-Gb/s SONET/SDH transceiver in 0.13-/spl mu/m CMOS

Here, we present a low-power fully integrated 10-Gb/s transceiver in 0.13-/spl mu/m CMOS. This transceiver comprises full transmit and receive functions, including 1:16 multiplex and demultiplex functions, high-sensitivity limiting amplifier, on-chip 10-GHz clock synthesizer, clock-data recovery, 10-GHz data and clock drivers, and an SFI-4 compliant 16-bit LVDS interface. The transceiver exceeds all SONET/SDH (OC-192/STM-64) jitter requirements with significant margin: receiver high-frequency jitter tolerance exceeds 0.3 UI/sub pp/ and transmitter jitter generation is 30 mUI/sub pp/. All functionality and specifications (core and I/O) are achieved with power dissipation of less than 1 W.     

光通信用10Gbit/s Transponder的设计

本文分析了在高速光模块设计中介质损耗和微带结构对信号的影响,并对PCB中信号串扰模型的参数进行了计算.解决了高速光模块设计的一些关键问题,设计出满足MSA的300-pin transponder,并对模块进行了一系列性能和指标测试.测试结果表明,该模块完全满足SDH/SONET(STM-64/OC-192)以及10G Ethernet应用要求.     

PDH到622Mb/sSDH/SONET映射芯片实现

 设计了PDH到622 Mb/s SDH/SONET的映射及逆映射芯片.集成了DS1/E1/J1成帧器、DS1/DS3复接电路和E1/E3复接电路,具有622 Mb/s和155 Mb/s的高速标准接口和3通道STM-1/STS-3分插复用总线接口,支持复用段1+1保护和UPSR环形网络拓扑结构.单片实现84通道DS1/J1或63通道E1到STM-1/STS-3的映射复用功能及多通道DS3/E3/STS-1到STM-4/STS-12的映射复用功能.支持点对点应用和环形应用,交换模式支持2016通道DS0/E0的应用.4颗芯片实现336通道DS1/J1或252通道E1到STM-4/STS-12的映射复用功能.采用TSMC 0.13 μm CMOS工艺流片,芯片规模约600万门,700管脚 PGBA封装,满足光纤通信传输的要求,并成功用于光纤通信设备.     

12Gb/s 0.25μm CMOS低功耗1:4分接器

实现了一种能运用于光传输系统SONET OC-192的低功耗单级分接器,其工作速率高达12Gb/s.该电路采用了特征栅长为0.25μm的TSMC混和信号CMOS工艺.所有的电路都采用了源极耦合逻辑,在抑制共模噪声的同时达到尽可能高的工作速率.该分接器具有利用四分之一速率的正交时钟来实现单级分接的特征,减少了分接器器件,降低了功耗.通过在晶圆测试,该芯片在输入12Gb/s长度为231-1伪随机码流时,分接功能正确.芯片面积为0.9mm×0.9mm,在2.5V单电源供电的情况下的典型功耗是210mW.     

A CMOS 10-gb/s SONET transceiver

This paper presents a single-chip SONET OC-192 transceiver (transmitter and receiver) fabricated in a 90-nm mixed-signal CMOS process. The transmitter consists of a 10-GHz clock multiplier unit (CMU), 16:1 multiplexer, and 10-Gb/s output buffer. The receiver consists of a 10-Gb/s limiting input amplifier, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. Both transmit and receive phase-locked loops employ a 10-GHz on-chip LC voltage-controlled oscillator (VCO). This transceiver exceeds all SONET OC-192 specifications with ample margin. Jitter generation at 10.66-Gb/s data rate is 18 mUI/sub pp/ (unit interval, peak-to-peak) and jitter tolerance is 0.6 UI/sub pp/ at 4-MHz jitter frequency. This transceiver requires 1.2V for the core logic and 1.8 V for input/output LVDS buffers. Multiple power supply domains are implemented here to mitigate crosstalk between receiver and transmitter. The overall power dissipation of this chip is 1.65 W.     

基于SDH/SONET的IP数据传送技术分析

SDH/SONET是目前最主要的传输技术,网络应用则以IP业务为中心,IP在SDH/SONET上的传送是一个重要问题.本文讨论IP在SDH/SONET上传送的传统PoA和PoS技术的基础上,详细分析了两种新的协议--简单数据链路(SDL,Simple Data Link)协议和通用成帧规程(GFP,Generic Framing Procedure),研究了各种协议技术的优缺点.     

A Full On-Chip CMOS Clock-and-Data Recovery IC for OC-192 Applications

In this paper, a fully integrated OC-192 clock-and-data recovery (CDR) architecture in standard 0.18-mum CMOS is described. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate zero and pole and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290 mW. The measured RMS jitter of the recovered data is 0.74 ps with a bit-error rate less than 10^-12 when the input pseudorandom bit sequence (PRBS) data pattern has a pattern length of 2¹⁵ - 1 and a total horizontal eye closure of 0.54 peak-to-peak unit interval (Ul_pp) due to the added intersymbol interference distortion by passing data through 9-in FR4 printed circuit board trace. The chip exceeds SONET OC-192 jitter tolerance mask, and high-frequency jitter tolerance is over 0.31 Ul_pp by applying PRBS data with a pattern length of 2³¹ - 1.     

A fully integrated SONET OC-48 transceiver in standard CMOS

This paper presents the first fully integrated, SONET OC-48 (2.488/2.666 Gb/s) transceiver using a standard CMOS process. Careful design methodology combined with a standard CMOS technology allows performance exceeding SONET requirements with the added benefits of reduced power dissipation, higher integration levels, and simplified manufacturability as compared to other fabrication technologies. This chip, designed using a standard 0.18-μm CMOS technology, has a total power dissipation of 500 mW and an rms jitter of 1 ps     

Automatic laser shutdown implications for all optical data networks

Generalized multiprotocol label switching (GMPLS), optical packet, and burst-switched networks in which the synchronous digital hierarchy/synchronous optical network (SDH/SONET) layer is removed may be rendered nonfunctional because the current standard for triggering Automatic Power Reduction (APR) cannot distinguish between a fiber that has been de-energized and a fiber failure. If this standard is applied, without modification, the likelihood of unnecessary amplifier shutdown in optical networks is significant. These shutdown events may impact large regions of the network and render optical links inoperable. To avoid unnecessary amplifier shutdown, amendments to the current operation of APR are suggested.