Stack system of PECVD amorphous silicon and PECVD silicon oxide for silicon solar cell rear side passivation

A stack of hydrogenated amorphous silicon (a‐Si) and PECVD‐silicon oxide (SiO_x) has been used as surface passivation layer for silicon wafer surfaces. Very good surface passivation could be reached leading to a surface recombination velocity (SRV) below 10 cm/s on 1 Ω cm p‐type Si wafers. By using the passivation layer system at a solar cell's rear side and applying the laser‐fired contacts (LFC) process, pointwise local rear contacts have been formed and an energy conversion efficiency of 21·7% has been obtained on p‐type FZ substrates (0·5 Ω cm). Simulations show that the effective rear SRV is in the range of 180 cm/s for the combination of metallised and passivated areas, 120 ± 30 cm/s were calculated for the passivated areas. Rear reflectivity is comparable to thermally grown silicon dioxide (SiO₂). a‐Si rear passivation appears more stable under different bias light intensities compared to thermally grown SiO₂. Copyright © 2008 John Wiley & Sons, Ltd.     

Low‐temperature formation of local Al contacts to a‐Si:H‐passivated Si wafers

We have passivated boron‐doped, low‐resistivity crystalline silicon wafers on both sides by a layer of intrinsic, amorphous silicon (a‐Si:H). Local aluminum contacts were subsequently evaporated through a shadow mask. Annealing at 210°C in air dissolved the a‐Si:H underneath the Al layer and reduces the contact resistivity from above 1 Ω cm² to 14·9 m Ω cm². The average surface recombination velocity is 124 cm/s for the annealed samples with 6% metallization fraction. In contrast to the metallized regions, no structural change is observed in the non‐metallized regions of the annealed a‐Si:H film, which has a recombination velocity of 48 cm/s before and after annealing. Copyright © 2004 John Wiley & Sons, Ltd.     

Optimizing annealing steps for crystalline silicon solar cells with screen printed front side metallization and an oxide‐passivated rear surface with local contacts

Silicon solar cells that feature screen printed front contacts and a passivated rear surface with local contacts allow higher efficiencies compared to present industrial solar cells that exhibit a full area rear side metallization. If thermal oxidation is used for the rear surface passivation, the final annealing step in the processing sequence is crucial. On the one hand, this post‐metallization annealing (PMA) step is required for decreasing the surface recombination velocity (SRV) at the aluminum‐coated oxide‐passivated rear surface. On the other hand, PMA can negatively affect the screen printed front side metallization leading to a lower fill factor. This work separately analyzes the impact of PMA on both, the screen printed front metallization and the oxide‐passivated rear surface. Measuring dark and illuminated IV‐curves of standard industrial aluminum back surface field (Al‐BSF) silicon solar cells reveals the impact of PMA on the front metallization, while measuring the effective minority carrier lifetime of symmetric lifetime samples provides information about the rear side SRV. One‐dimensional simulations are used for predicting the cell performance according to the contributions from both, the front metallization and the rear oxide‐passivation for different PMA temperatures and durations. The simulation also includes recombination at the local rear contacts. An optimized PMA process is presented according to the simulations and is experimentally verified. The optimized process is applied to silicon solar cells with a screen printed front side metallization and an oxide‐passivated rear surface. Efficiencies up to 18.1% are achieved on 148.8 cm² Czochralski (Cz) silicon wafers. Copyright © 2009 John Wiley & Sons, Ltd.     

Experimental and simulated analysis of front versus all‐back‐contact silicon heterojunction solar cells: effect of interface and doped a‐Si:H layer defects

Front silicon heterojunction and interdigitated all‐back‐contact silicon heterojunction (IBC‐SHJ) solar cells have the potential for high efficiency and low cost because of their good surface passivation, heterojunction contacts, and low temperature fabrication processes. The performance of both heterojunction device structures depends on the interface between the crystalline silicon (c‐Si) and intrinsic amorphous silicon [(i)a‐Si:H] layer, and the defects in doped a‐Si:H emitter or base contact layers. In this paper, effective minority carrier lifetimes of c‐Si using symmetric passivation structures were measured and analyzed using an extended Shockley–Read–Hall formalism to determine the input interface parameters needed for a successful 2D simulation of fabricated baseline solar cells. Subsequently, the performance of front silicon heterojunction and IBC‐SHJ devices was simulated to determine the influence of defects at the (i)a‐Si:H/c‐Si interface and in the doped a‐Si:H layers. For the baseline device parameters, the difference between the two device configurations is caused by the emitter/base contact gap recombination and the back surface geometry of IBC‐SHJ solar cell. This work provides a guide to the optimization of both types of SHJ device performance, predicting an IBC‐SHJ solar cell efficiency of 25% for realistic material parameters. Copyright © 2013 John Wiley & Sons, Ltd.     

Fine line printed silicon solar cells exceeding 20% efficiency

Silicon solar cells with passivated rear side and laser‐fired contacts were produced on float zone material. The front side contacts are built up in two steps, seed and plate. The seed layer is printed using an aerosol jet printer and a silver ink. After firing this seed layer through the silicon nitride layer, the conductive layer is grown by light induced plating. The contact formation is studied on different emitter sheet resistances, 55 Ω/sq, 70 Ω/sq, and on 110 Ω/sq. These emitters are passivated with a PECVD silicon nitride layer which also acts as an anti‐reflection coating. Even on the 110 Ω/sq emitters it was possible to reach a fill factor of 80·1%. The electrical properties i.e., the contact resistance of the front side contacts are studied by transfer length model (TLM) measurements. On a cell area of 4 cm² and emitter sheet resistance of 110 Ω/sq, a record efficiency of 20·3% was achieved. Excellent open‐circuit voltage (V_oc) and short‐circuit current (j_sc) values of 661 mV and 38·4 mA/cm² were obtained due to the low recombination in the 110 Ω/sq emitter and at the passivated rear surface. These results show impressively that it is possible to contact emitter profiles with a very high efficiency potential using optimized printing technologies. Copyright © 2008 John Wiley & Sons, Ltd.     

Front and rear silicon‐nitride‐passivated multicrystalline silicon solar cells with an efficiency of 18.1%

A solar cell process designed to utilise low‐temperature plasma‐enhanced chemical vapour deposited (PECVD) silicon nitride (SiN_x) films as front and rear surface passivation was applied to fabricate multicrystalline silicon (mc‐Si) solar cells. Despite the simple photolithography‐free processing sequence, an independently confirmed efficiency of 18.1% (cell area 2 × 2 cm²) was achieved. This excellent efficiency can be predominantly attributed to the superior quality of the rear surface passivation scheme consisting of an SiN_x film in combination with a local aluminium back‐surface field (LBSF). Thus, it is demonstrated that low‐temperature PECVD SiN_x films are well suited to achieve excellent rear surface passivation on mc‐Si. Copyright © 2002 John Wiley & Sons, Ltd.     

SHORT COMMUNICATION: ACCELERATED PUBLICATION: Multicrystalline silicon solar cells exceeding 20% efficiency

This paper presents the first conversion efficiency above 20% for a multicrystalline silicon solar cell. The application of wet oxidation for rear surface passivation significantly reduces the process temperature and therefore prevents the degradation of minority‐carrier lifetime. The excellent optical properties of the dielectrically passivated rear surface in combination with a plasma textured front surface result in a superior light trapping and allow the use of substrates below 100 μm thickness. A simplified process scheme with laser‐fired rear contacts leads to conversion efficiencies of 20·3% for multicrystalline and 21·2% for monocrystalline silicon solar cells on small device areas (1 cm²). Copyright © 2004 John Wiley & Sons, Ltd.     

Large area tunnel oxide passivated rear contact n‐type Si solar cells with 21.2% efficiency

This paper reports on the implementation of carrier‐selective tunnel oxide passivated rear contact for high‐efficiency screen‐printed large area n‐type front junction crystalline Si solar cells. It is shown that the tunnel oxide grown in nitric acid at room temperature (25°C) and capped with n⁺ polysilicon layer provides excellent rear contact passivation with implied open‐circuit voltage iV_oc of 714 mV and saturation current density J_0b′ of 10.3 fA/cm² for the back surface field region. The durability of this passivation scheme is also investigated for a back‐end high temperature process. In combination with an ion‐implanted Al₂O₃‐passivated boron emitter and screen‐printed front metal grids, this passivated rear contact enabled 21.2% efficient front junction Si solar cells on 239 cm² commercial grade n‐type Czochralski wafers. Copyright © 2016 John Wiley & Sons, Ltd.     

20.7% efficient ion‐implanted large area n‐type front junction silicon solar cells with rear point contacts formed by laser opening and physical vapor deposition

In this work, we report on ion‐implanted, high‐efficiency n‐type silicon solar cells fabricated on large area pseudosquare Czochralski wafers. The sputtering of aluminum (Al) via physical vapor deposition (PVD) in combination with a laser‐patterned dielectric stack was used on the rear side to produce front junction cells with an implanted boron emitter and a phosphorus back surface field. Front and back surface passivation was achieved by thin thermally grown oxide during the implant anneal. Both front and back oxides were capped with SiN_x, followed by screen‐printed metal grid formation on the front side. An ultraviolet laser was used to selectively ablate the SiO₂/SiN_x passivation stack on the back to form the pattern for metal–Si contact. The laser pulse energy had to be optimized to fully open the SiO₂/SiN_x passivation layers, without inducing appreciable damage or defects on the surface of the n⁺ back surface field layer. It was also found that a low temperature annealing for less than 3 min after PVD Al provided an excellent charge collecting contact on the back. In order to obtain high fill factor of ~80%, an in situ plasma etching in an inert ambient prior to PVD was found to be essential for etching the native oxide formed in the rear vias during the front contact firing. Finally, through optimization of the size and pitch of the rear point contacts, an efficiency of 20.7% was achieved for the large area n‐type passivated emitter, rear totally diffused cell. Copyright © 2014 John Wiley & Sons, Ltd.     

19%‐efficient and 43 µm‐thick crystalline Si solar cell from layer transfer using porous silicon

We present a both‐sides‐contacted thin‐film crystalline silicon (c‐Si) solar cell with a confirmed AM1.5 efficiency of 19.1% using the porous silicon layer transfer process. The aperture area of the cell is 3.98 cm². This is the highest efficiency ever reported for transferred Si cells. The efficiency improvement over the prior state of the art (16.9%) is achieved by implementing recent developments for Si wafer cells such as surface passivation with aluminum oxide and laser ablation for contacting. The cell has a short‐circuit current density of 37.8 mA cm⁻², an open‐circuit voltage of 650 mV, and a fill factor of 77.6%. Copyright © 2011 John Wiley & Sons, Ltd.     

Evaluation of advanced p‐PERL and n‐PERT large area silicon solar cells with 20.5% energy conversion efficiencies

In this paper, we evaluate p‐type passivated emitter and rear locally diffused (p‐PERL) and n‐type passivated emitter and rear totally diffused (n‐PERT) large area silicon solar cells featuring nickel/copper/silver (Ni/Cu/Ag) plated front side contacts. By using front emitter p‐PERL and rear emitter n‐PERT, both cell structures can be produced with only a few adaptations in the entire process sequence because both feature the same front side design: homogeneous n⁺ diffused region with low surface concentration, SiO₂/SiN_x:H passivation, Ni/Cu/Ag plated contacts. Energy conversion efficiencies up to 20.5% (externally confirmed at FhG‐ISE Callab) are presented for both cell structures on large area cells together with power‐loss analysis and potential efficiency improvements based on PC1D simulations. We demonstrate that the use of a rear emitter n‐PERT cell design with Ni/Cu/Ag plated front side contacts enables to reach open‐circuit voltage values up to 676 mV on 1–2 Ω cm n‐type CZ Si. We show that rear emitter n‐PERT cells present the potential for energy conversion efficiencies above 21.5% together with a strong tolerance to wafer thickness and bulk resistivity. Copyright © 2014 John Wiley & Sons, Ltd.     

Textured silicon surface passivation by high‐rate expanding thermal plasma deposited SiN and thermal SiO2/SiN stacks for crystalline silicon solar cells

Expanding thermal plasma (ETP) deposited silicon nitride (SiN) with optical properties suited for the use as antireflection coating (ARC) on silicon solar cells has been used as passivation layer on textured monocrystalline silicon wafers. The surface passivation behavior of these high‐rate (>5 nm/s) deposited SiN films has been investigated for single layer passivation schemes and for thermal SiO₂/SiN stack systems before and after a thermal treatment that is normally used for contact‐firing. It is shown that as‐deposited ETP SiN used as a single passivation layer almost matches the performance of a thermal oxide. Furthermore, the SiN passivation behavior improves after a contact‐firing step, while the thermal oxide passivation degrades which makes ETP SiN a better alternative for single passivation layer schemes in combination with a contact‐firing step. Moreover, using the ETP SiN as a part of a thermal SiO₂/SiN stack proves to be the best alternative by realizing very low dark saturation current densities of <20 fA/cm² on textured solar‐grade FZ silicon wafers and this is further improved to <10 fA/cm² after the anneal step. Optical and electrical film characterizations have also been carried out on these SiN layers in order to study the behavior of the SiN before and after the thermal treatment. Copyright © 2008 John Wiley & Sons, Ltd.     

Diffusion‐free high efficiency silicon solar cells

Traditional POCl₃ diffusion is performed in large diffusion furnaces heated to ~850 C and takes an hour long. This may be replaced by an implant and subsequent 90‐s rapid thermal annealing step (in a firing furnace) for the fabrication of p‐type passivated emitter rear contacted silicon solar cells. Implantation has long been deemed a technology too expensive for fabrication of silicon solar cells, but if coupled with innovative process flows as that which is mentioned in this paper, implantation has a fighting chance. An SiOx/SiN_y rear side passivated p‐type wafer is implanted at the front with phosphorus. The implantation creates an inactive amorphous layer and a region of silicon full of interstitials and vacancies. The front side is then passivated using a plasma‐enhanced chemical vapor deposited SiN_xH_y. The wafer is placed in a firing furnace to achieve dopant activation. The hydrogen‐rich silicon nitride releases hydrogen that is diffused into the Si, the defect rich amorphous front side is immediately passivated by the readily available hydrogen; all the while, the amorphous silicon recrystallizes and dopants become electrically active. It is shown in this paper that the combination of this particular process flow leads to an efficient Si solar cell. Cell results on 160‐µm thick, 148.25‐cm² Cz Si wafers with the use of the proposed traditional diffusion‐free process flow are up to 18.8% with a V_oc of 638 mV, J_sc of 38.5 mA/cm², and a fill factor of 76.6%. Copyright © 2012 John Wiley & Sons, Ltd.     

High efficiency large area n‐type front junction silicon solar cells with boron emitter formed by screen printing technology

In this paper, we report on commercially viable screen printing (SP) technology to form boron emitters. A screen‐printed boron emitter and ion‐implanted phosphorus back surface field were formed simultaneously by a co‐annealing process. Front and back surfaces were passivated by chemically grown oxide capped with plasma‐enhanced chemical vapor deposition silicon nitride stack. Front and back contacts were formed by traditional SP and firing processes with silver/aluminum grid on front and local silver back contacts on the rear. This resulted in 19.6% efficient large area (239 cm²) n‐type solar cells with an open‐circuit voltage V_oc of 645 mV, short‐circuit current density J_sc of 38.6 mA/cm², and fill factor of 78.6%. This demonstrates the potential of this novel technology for production of low‐cost high‐efficiency n‐type silicon solar cells. Copyright © 2014 John Wiley & Sons, Ltd.     

Development of high‐efficiency large‐area screen‐printed solar cells on direct kerfless epitaxially grown monocrystalline Si wafer and structure

This paper demonstrates the potential of epitaxially grown Si wafers with doped layers for high‐efficiency solar cells. Boron‐doped 239 cm² 180–200 µm thick 2 Ω‐cm wafers were grown with and without 15 µm thick p⁺ layer, with a doping in the range of 10¹⁷~10¹⁸ cm⁻³. A layer transfer process involving porous Si layer to lift off epi‐Si wafers from the reusable substrate was used. The pp⁺ wafers were converted into n⁺pp⁺ passivated emitter rear totally diffused (PERT) cells by forming an oxide‐passivated POCl₃‐diffused n⁺ emitter at the front, and oxide/nitride‐passivated epitaxially grown p⁺ BSF at the entire back, with local screen‐printed contacts. To demonstrate and quantify the benefit of the epi‐grown p⁺ layer, standard passivated emitter and rear cells (PERCs) with local BSF and contacts were also fabricated on p‐type epi‐Si wafers as well on commercial‐grade Cz wafers. Sentaurus 2D device model was used to assess the impact of the epi‐grown p⁺ layer, which showed an efficiency gain of ~0.5% for this PERT structure over the traditional PERC. This was validated by the cell results, which showed an efficiency of ~20.1% for the PERC, and ~20.3% for the PERT cell using epi‐Si wafers. Experimental data showed higher FF in PERT cells, largely because of the decrease in lateral resistance on the rear side. Efficiency gain, a result of higher FF, was greater than the recombination loss in the p⁺ layer because of the lightly doped thick p⁺ epi‐grown region used in this study. Copyright © 2016 John Wiley & Sons, Ltd.     

Surface passivation of high‐efficiency silicon solar cells by atomic‐layer‐deposited Al2O3

Atomic‐layer‐deposited aluminium oxide (Al₂O₃) is applied as rear‐surface‐passivating dielectric layer to passivated emitter and rear cell (PERC)‐type crystalline silicon (c‐Si) solar cells. The excellent passivation of low‐resistivity p‐type silicon by the negative‐charge‐dielectric Al₂O₃ is confirmed on the device level by an independently confirmed energy conversion efficiency of 20·6%. The best results are obtained for a stack consisting of a 30 nm Al₂O₃ film covered by a 200 nm plasma‐enhanced‐chemical‐vapour‐deposited silicon oxide (SiO_x) layer, resulting in a rear surface recombination velocity (SRV) of 70 cm/s. Comparable results are obtained for a 130 nm single‐layer of Al₂O₃, resulting in a rear SRV of 90 cm/s. Copyright © 2008 John Wiley & Sons, Ltd.     

Passivating thin bifacial silicon solar cells for industrial production

A scheme for passivating thin multi‐crystalline silicon solar cells compatible to mass production is presented. Wafers with a thickness of 180 µm were processed into solar cells. The otherwise severe bowing has been avoided by reduced aluminium coverage on the rear surface. The process scheme includes a silicon nitride firing through step for conventional screen printed contacts, where a silicon nitride layer on the rear surface acts as surface passivation layer and enables a gain in efficiency of 0.6% [abs.]. Copyright © 2007 John Wiley & Sons, Ltd.     

17.6% efficient tricrystalline silicon solar cells with spatially uniform texture

Up to now solar cells fabricated on tricrystalline Czochralski‐grown silicon (tri‐Si) have shown relatively low short‐circuit current densities of about 31–33 mA/cm² because the three {110}‐oriented grains cannot effectively be textured by commonly used anisotropic etching solutions. In this work, we have optimised a novel chemical texturing step for tri‐Si and integrated it successfully into our solar cell process. Metal/insulator/semiconductor‐contacted phosphorus‐diffused n⁺p junction silicon solar cells with a silicon‐dioxide‐passivated rear surface and evaporated aluminium contacts were manufactured, featuring a spatially uniform surface texture over all three grains on both cell sides. Despite the simple processing sequence and cell structure, an independently confirmed record efficiency of 17.6% has been achieved. This excellent efficiency is mainly due to an increased short‐circuit current density of 37 mA/cm² obtained by substantially reduced reflection and enhanced light trapping. Copyright © 2003 John Wiley & Sons, Ltd.     

Boron‐doped hydrogenated silicon carbide alloys containing silicon nanocrystallites for highly efficient nanocrystalline silicon thin‐film solar cells

Boron‐doped hydrogenated silicon carbide alloys containing silicon nanocrystallites (p‐nc‐SiC:H) were prepared using a plasma‐enhanced chemical vapor deposition system with a mixture of CH₄, SiH₄, B₂H₆ and H₂ gases. The influence of hydrogen dilution on the material properties of the p‐nc‐SiC:H films was investigated, and their roles as window layers in hydrogenated nanocrystalline silicon (nc‐Si:H) solar cells were examined. By increasing the R_H (H₂/SiH₄) ratio from 90 to 220, the Si―C bond density in the p‐nc‐SiC:H films increased from 5.20 × 10¹⁹ to 7.07 × 10¹⁹/cm³, resulting in a significant increase of the bandgap from 2.09 to 2.23 eV in comparison with the bandgap of 1.95 eV for p‐nc‐Si:H films. For the films deposited at a high R_H ratio, the Si nanocrystallites with a size of 3–15 nm were formed in the amorphous SiC:H matrix. The Si nanocrystallites played an important role in the enhancement of vertical charge transport in the p‐nc‐SiC:H films, which was verified by conductive atomic force microscopy measurements. When the p‐nc‐SiC:H films deposited at R_H = 220 were applied in the nc‐Si:H solar cells, a high conversion efficiency of 8.26% (V_oc = 0.53 V, J_sc = 23.98 mA/cm² and FF = 0.65) was obtained compared to 6.36% (V_oc = 0.44 V, J_sc = 21.90 mA/cm² and FF = 0.66) of the solar cells with reference p‐nc‐Si:H films. Further enhancement in the cell performance was achieved using p‐nc‐SiC:H bilayers consisting of highly doped upper layers and low‐level doped bottom layers, which led to the increased conversion efficiency of 9.03%. Copyright © 2015 John Wiley & Sons, Ltd.     

Advanced PERC and PERL production cells with 20.3% record efficiency for standard commercial p‐type silicon wafers

Following intensive research and development, Suntech Power has successfully commercialised its Pluto technology with 0.5 GW annual production capacity, delivering up to 10% performance advantage over conventional screen‐printed cells. The next generation of Pluto involves the development of improved rear surface design based on the design features of passivated emitter and rear locally diffused cells. Cells with an average efficiency over 20% were fabricated on 155 cm² commercial‐grade p‐type wafers using mass‐manufacturing processes and equipment, with the highest single‐cell efficiency independently confirmed at 20.3%. This is believed to be a record efficiency for this wafer type. Further optimisation work on contact pattern and rear surface passivation suggests the potential for further efficiency increase approaching 23%. Copyright © 2012 John Wiley & Sons, Ltd.