平衡式E/F类功率放大器的设计与实现

为了解决功率放大器设计过程中存在的效率低和输入/输出端回波损耗较大的问题,设计了一种工作频率为1.5 GHz的平衡式功率放大器。通过采用3 dB定向耦合器对射频信号进行分配及合成,大大降低了输入/输出端的驻波系数,并将逆F类功率放大器的谐波控制网络引入E类功率放大器的匹配电路中。使用ADS对晶体管进行负载牵引和源牵引,得到晶体管的输入/输出阻抗,同时结合晶体管的寄生参数,在输出匹配电路中对二次谐波、三次谐波分别进行开路和短路处理,且为了进一步提高功率放大器的工作性能,在输入电路结构中抑制了二次谐波。选用GaN HEMT器件CGH40010F晶体管,利用ADS软件进行电路仿真,并采用Rogers4350b高频板材制作该功率放大器的实际测试电路板。仿真优化和实测表明：在输入功率为28 dBm时,该功率放大器的输出功率为41.54 dBm,漏极效率为76.99%,功率附加效率（power additional efficiency,PAE）达到73.59%,输入/输出端驻波系数小于2,同时具有160 MHz的高效率带宽,且最大输出功率较单管功率放大器提高了3 dB。实测结果与仿真数据有一定的误差,但仍有较好的一致性,满足设计指标要求,验证了设计方法的可行性。该设计方法具有效率高和回波损耗低的优势,提高了功率放大器的设计效率,使它在当今高效绿色节能的射频微波通信系统中具有广阔的应用前景。     

Study on the new control scheme of class-E inverter for IH-jar application with clamped voltage characteristics using pulse frequency modulation

A new control scheme of Class-E inverter for induction heating jar applications with clamped voltage characteristics using pulse frequency modulation (PFM) is introduced. To reduce the voltage stress of a switch, the proposed PFM control scheme does not need any auxiliary circuit. It can decrease the voltage stress of a switch through the modulation of switching frequency. The Class-E inverter using the proposed control scheme has the advantages of not only the same output power when it is compared with an active clamped class-E (ACCE) inverter, but also zero-voltage-switching, which are characteristics of conventional Class-E and ACCE inverter. The control principles of the proposed method are explained in detail and its validity is verified through experimental results     

A Direct Measurement Method of Frequency Responses of the Smart Power IC

Smart power ICs are widely used in universal input power supplies. This paper presents a detailed analysis and scheme design for real-time small-signal modeling method for smart power IC. First, in this method, the switching duty cycle is converted into a voltage output signal based on the operational characteristics of the power IC. The power IC's frequency response is then obtained by measuring the duty cycle output signal and the power IC's control input signal. The modeling system is referred to as sampling the duty cycle of the power IC with a zero-order hold output. Using least-square identification, the smart power IC's dynamic model and transfer function are synthesized from the measurement data. The results of the modeling experiment are discussed, and practical guidelines and error amplifier (EA) design examples are presented for both continuous and discontinuous conduction modes (CCM and DCM). The effectiveness and practicality are verified through experiments.      

基于改进型匹配网络的宽带高效率E类功放的设计

为了解决E类功放工作带宽过窄的问题,对E类功放的输入、输出匹配网络提出了一种改进方案.该方案中输出匹配网络采用微带线结构与切比雪夫低通匹配网络相结合的方法,在较宽的工作带宽内有效地抑制了谐波;并采用阻抗变换方法设计了含闭式解的宽带带通输入匹配网络,明显增强了输入匹配网络设计的灵活性.利用该方案,同时采用多谐波双向牵引技术得到功率管的最佳源阻抗和负载阻抗,基于CGH40010F功率管设计了一款应用于L波段的宽带高效率E类功放.测试结果表明,在输入功率为28dBm,漏极偏置电压VDS=28V,栅极电压VGS=-3.3V时,在整个L波段频率范围内漏极工作效率大于65%,最高达到83%,输出功率为39~41.1dBm,增益为11~13.1dB,增益平坦度为±1dB.这一结果验证了该改进方案的有效性,使得E类功放具有宽带宽、高效率的性能.     

Analysis of a class E power amplifier with series-parallel resonator

The authors propose new class E power amplifier configuration with an equivalent series-parallel resonator network. The boundary conditions for the 100% efficiency operations are analysed under the conditions that the duty ratio is 0.5 and the loaded quality factor is infinite. If the DC supply voltage and the output power are assumed the same, the load resistance R is 53.65% higher, the excess series inductance L/sub x/is 3.99% lower and the maximum frequency f/sub max/is improved by 6.47% compared with the conventional class E amplifier. The theoretical analysis is verified by numerical results and harmonic balance simulations. And a lumped element test board is built and measured at 200 MHz utilising a Lateral Double Diffused Metal Oxide Semiconductor (LDMOS) transistor MRF21010 as the switching device. An output power of 33.03 dBm, a drain efficiency of 85.6% and a gain of 16 dB are measured. The approximate transmission-line topology with harmonics suppression is also proposed.     

A novel driver with adjustable frequency and phase for traveling‐wave type ultrasonic motor

Abstract

This paper describes the design of a traveling‐wave ultrasonic motor (TWUSM) drive circuit, intended to simultaneously employ both driving frequency and phase modulation control. The operating principles and a detailed analysis of the proposed driving circuit, consisting of voltage‐controlled oscillator (VCO), voltage‐controlled phase‐shifter circuit and non‐resonant power amplifier converter, are introduced. To drive the USM effectively, a two‐phase power amplifier converter using non‐resonant output was designed to provide a balanced two‐phase voltage source. Two‐phase output driving voltages could be maintained at the same peak voltage value as the driving frequency under varying phase‐modulation processes. Detailed experimental results are provided to demonstrate the effectiveness of the proposed driving circuit.     

Low voltage surface transverse wave oscillators for the next generation CMOS technology

The design and performance of voltage controlled surface transverse wave oscillators (VCSTWO) in the lower gigahertz frequency range, operating on supply and tuning voltages in the 1.2 to 3.3 V range, and suitable for direct interfacing with the next generation CMOS circuits are presented. By applying the "boost" principle, as used in direct current (DC)-DC converters, to the design of the sustaining amplifier, the VCSTWO outputs are switched between 0 V and a positive peak value, exceeding the supply voltage Us, to provide safe CMOS-circuit switching while keeping the radio frequency (RF)/DC efficiency to a maximum for low DC power consumption. The investigated 1.0 and 2.5 GHz VCSTWO are varactor tuned feedback-loop oscillators stabilized with two-port surface transverse wave (STW) resonators. Each VCSTWO has a DC-coupled, high-impedance switched output to drive the CMOS circuit directly, and an additional sinusoidal 50 ohmz high-power reference output available for other low-noise system applications. Phase noise levels in the -103 to -115 dBc/Hz range at 1 kHz carrier offset are achieved with 1.0 GHz VCSTWO at a RF/DC efficiency in the 21 to 29% range. The 2.5 GHz prototypes demonstrate phase noise levels in the -97 to -102 dBc/Hz range at 1 kHz carrier offset, and efficiencies range between 8 and 15%.     

5.25 GHz CMOS cascode power amplifier for 802.11a wireless local area network

The authors investigate a 5.25 GHz highly integrated CMOS class-AB power amplifier for IEEE 802.11a wireless local area network. The proposed power amplifier is implemented with a two gain-stage structure which is followed by an off-chip output matching circuit. Moreover, transistor-level compensation techniques are employed to improve the linearity. The power amplifier is designed with an on-chip input matching circuit, whereas the output matching circuit translates the signal power from 50 to 20 V load resistance. The measured results indicate over 20% power-added efficiency, over 20 dBm output power and 28.6 dBm output IP3. All the specifications are based on 50 V input impedance at 2.4 V supply voltage.     

Thermal regimes of relativistic magnetron oscillators

Experiments with relativistic magnetron oscillators (RMOs) using high-current electron accelerators allowed a level of output power from several hundred megawatts to several gigawatts to be reached at an efficiency of 10–30%. The operation principle of RMOs is identical to that of classical devices, but the determination of working regimes and calculation of output characteristics require taking into account relativistic corrections. In addition, a high cathode-anode voltage and high current in RMOs lead to some specific effects related to the damage of anode units as a result of thermal shocks. RMO operation in a periodic pulsed (pulse train) regime, which is of the most practical interest, imposes stringent requirements on the working life of anode units. The principles of choice of the material and design for the anode units of RMOs are formulated. Calculations of the limiting thermal regimes of RMO operation depending on the electron beam power flux density and the off/duty ratio of heating pulses are presented. Methods of increasing the working life of anode units are proposed.     

Multiple-load series resonant inverter for induction cooking application with pulse density modulation

Multiple-load induction cooking applications are suitable used when multi-output inverters or multi-inverters are needed for multiple-load operation. Some common approaches and modifications are needed in inverter configuration for multiple-load application. This paper presents an inverter configuration with two loads by using pulse density modulation control technique. It allows the output power control of each load independently with constant switching frequency and constant duty ratio. The pulse density modulation control technique is obtained using phase on–off control between two legs of the inverter to reduce acoustic noise. The two-load three-leg inverter configuration provides reduction of the component count for extension of multiple loads. The control technique provides a wide range of output power control. In addition, it can achieve efficient and stable zero voltage switching operation in the whole load range. The proposed control scheme is simulated and experimentally verified with two-load inverter configuration.     

Suppression of amplified spontaneous emission from a four-pass dye laser amplifier

We demonstrate a new design for a four-pass dye laser amplifier that can be used to reduce amplified spontaneous emission (ASE) in the amplifier output beam. Compared with the results obtained from normal operation of the four-pass dye laser amplifier without a frequency-selective device, by using a diffraction grating in the amplifier we can reduce the ASE ratio by a factor in excess of 10 and increase output energy by ~4%. The obtained ASE ratio of the four-pass amplifier system is <1.5%.     

Analysis and implementation of an active snubber dc/dc converter with series?parallel connection in primary and secondary sides

An active snubber dc/dc converter to achieve zero voltage switching (ZVS) on power switch is presented. In the proposed converter, the primary windings of two transformers are connected in series so that the primary currents of the two transformers are equal. The secondary sides of the isolated zeta converters are connected in the parallel to share the load current and reduce the current stresses on the secondary windings of the two transformers. A boost type of active snubber is connected in parallel with the main switch to recycle the energy stored in transformer leakage and magnetizing inductors and to limit voltage stress of the main switch. During the transition interval between the active switch and the auxiliary switch, the resonance based on the resonant inductor and the output capacitor of the power switch will allow the switch to turn on at ZVS. The principle of operation, steady-state analysis and design consideration of the proposed converter are provided. Finally, experimental results for a 360 W (12 V/30 A) prototype circuit with 150 kHz switching frequency were given to demonstrate the circuit performance and verify the feasibility of the proposed converter.     

An Electronic Multiplier for Accurate Power Measurements

The time division multiplier-type wattmeter is based on a new principle of operation. An operational amplifier operates as an integrator of the sum of Ez (one of the two inputs) and either +E8, or -E8, E8 being an internal standardized voltage. A pulse-width modulation in the form of switch reversals is obtained which differs from balance condition by an amount proportional to Ex. Instantaneous multiplication provides a wattmeter with dc accuracy of ± 0.1 percent up to at least 10 kHz. The output voltage is ± 1 volt for a ± 1-volt input from Ex and Ey. To obtain the required flat frequency characteristics, a coupling transformer and an adjustable resistor are provided. A time constant of 6.8 X 10-9 seconds has been achieved. The voltage signal is readily provided by a precision ratiotran. Errors of ± 0.0001 percent in magnitude and 50 microradians in phase angle are reasonable.     

A computer-aided design procedure for flyback step-up DC-to-DC converters

A flyback step-up dc-to-dc power converter is modeled utilizing a linear magnetic core, transistor switch, diode, filter capacitance, and load resistance. Assuming constant voltage drops across the semiconductor elements when conducting, the circuit is analyzed to obtain an equation for the required number of turns, subject to the constraints of specified output voltage, operating frequency, maximum winding factor, maximum and minimum input voltage, output power, and flux density. Using an interpretive language, a program has been written to run on a minicomputer which searches a data base of magnetic core characteristics obtained from commercial core catalogs and prints a list of windable cores. In an evaluation section of the program, a core from the windable core list is selected by the designer and the losses in the various elements, along with maximum and minimum transistor current are computed. Another program is used to display on a computer graphics device the loci of maximum and minimum flux density in a selected core as functions of input voltage and output power in a perspective plot. Converter circuits derived from this computer-aided design procedure when tested in the laboratory have yielded data in close agreement with that predicted by the program.     

Cymbal压电发电换能器有限元分析

通过建立Cymbal压电发电换能器的机电耦合有限元分析模型,计算分析了换能器结构参数对输出电压和谐振频率的影响以及外接负载对Cymbal换能器输出电压和输出功率的影响。研究表明,为了降低换能器的工作频率和提高换能器的输出电压,应增大换能器的空腔底部直径和减小换能器的空腔高度;在选择金属端冒和压电陶瓷厚度等参数时,应综合考虑换能器系统的刚度和外界振动源的频率特性和加速度特性;在任意一个频率点上,Cymbal换能器均存在一个最佳的外接负载,使得换能器的输出功率最大,而这个最佳的负载阻抗就等于Cymbal换能器在这个工作频率点上的输出阻抗。文中还提出并分析了基于外加预应力的多振子级联方式Cymbal压电发电换能器系统的结构。     

An Ultra-Low Drift Amplifier Using a New Type of Series-Shunt MOSFET Chopper

A chopper amplifier of a new type is proposed for the amplification of nanovolt-order dc voltage. The chopper is built by connecting a shunt switch, which is driven at twice the chopper frequency, to the output terminals of a conventional and balanced-type series-shunt MOSFET chopper. The present chopper is free from offset voltage arising from spike voltages and has an input voltage offset temperature coefficient of less than 0.1 nV/°C for a signal source of less than 1 k?, and a long-term drift of 2 nV/18 h for signal source resistance of 6.1 ?.     

Magnetoresistive power sensor for measurement in situ of RF powerabsorbed by tissue

A new magnetoresistive sensor for use in medical RF heating and hyperthermia is presented. This sensor has dc output proportional to RF power absorbed in tissue. The operating principle of the sensor consists of multiplication of the instantaneous value of the RF current and voltage in a microstrip transmission line using a magnetoresistive element. At an operating frequency of 915 MHz in a 20% bandwidth, it has a sensitivity of 22 μV/W, insertion losses less than 0.1 dB and nonlinearity less than 3% up to 300 W. The uncertainty caused by the reflected waves with arbitrary phase is less than 3.5% up to the voltage standing wave ratio (VSWR) equals 3     

Cache Memory Design for Single Bit Architecture with Different SenseAmplifiers

Most modern microprocessors have one or two levels of on-chip caches to make things run faster, but this is not always the case. Most of the time, these caches are made of static random access memory cells. They take up a lot of space on the chip and use a lot of electricity. A lot of the time, low power is more important than several aspects. This is true for phones and tablets. Cache memory design for single bit architecture consists of six transistors static random access memory cell, a circuit of write driver, and sense amplifiers (such as voltage differential sense amplifier, current differential sense amplifier, charge transfer differential sense amplifier, voltage latch sense amplifier, and current latch sense amplifier, all of which are compared on different resistance values in terms of a number of transistors, delay in sensing and consumption of power. The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34 μW of power which shows that power is reduced up to 83%, 77.75% reduction in the case of the current differential sense amplifier, 39.62% in case of charge transfer differential sense amplifier and 50% in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture. Furthermore, power reduction techniques are applied over different blocks of cache memory architecture to optimize energy. The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078 μW of power, i.e., reduce 28% more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.     

热声发动机用声学放大器的改进研究

声学放大器是一种可显著提高热声发动机输出压力振幅和压比的装置,存在的主要问题是声功损失过大.通过理论研究,提出采用较大管径进一步提高声学放大器性能的方法,称为改进型声学放大器.实验结果表明:该声学放大器在大幅度提升输出压比的同时,没有明显降低发动机内的压比和破坏发动机内部声场,能使发动机工作在较高的品质状态.采用变负载法测量声功的实验结果也表明,改进型的声学放大器有效地解决了声功损失过大的问题.     

Analysis and design of high-efficiency variable conduction angle doherty amplifier

The Doherty amplifier was first proposed to improve the efficiency under output power back-off using the technique of load-line modulation of a `carrier? amplifier through a `peak? amplifier. By varying input bias of the peak amplifier along with load of the carrier amplifier at low drive levels, different topologies of the Doherty amplifier are distinguished. An analytical analysis that determines the optimum output performance of these topologies in terms of output power, efficiency and output power back-off ensuring a near-peak efficiency is developed. The presented comprehensive analysis considered for variation of conduction angle of the peak amplifier biased class C. New design equations of the analysed topologies are derived. A realisation at a central frequency of 1.9 GHz using GaAs field effect transistor (FET) devices of a Doherty amplifier topology is reported. In this topology the carrier operates (at low drive levels) into load impedance 5/2 times larger than its optimum. Power-added efficiency of 61.8% is measured at P/sub 1dB/ of 25.9 dB m and 33.2% is measured at 9 dB back-off from P/sub 1dB/.