Two-dimensional numerical modeling of magnetic-field sensors in CMOS technology

We present two-dimensional numerical simulations of two types of integrated silicon magnetic-field sensors realized recently in standard CMOS technology, viz. the split-drain MOSFET and the vertical Hall-effect device sensitive to magnetic fields perpendicular and parallel to the chip surface, respectively. Our results include potential, current, and surface charge distributions as well as sensitivity, linearity, and noise. Improved device geometries are suggested. Both the finite-difference method and a novel Greens function approach are used for solving the differential equations governing the carrier transport in the presence of a magnetic field.     

可调谐垂直腔面发射激光器

近年来国内外在可调谐垂直腔面发射激光器这一研究领域取得了极大的进步。叙述了可调谐垂直腔面发射激光器的结构原理和发展历程,对不同结构的优缺点作了对比介绍,展望了可调谐激光器的发展前景。这种器件在光传输、光互连及光并行信息处理等方面有着良好的应用前景。     

The vertical hall-effect device

A novel device, sensitive to the magnetic field parallel to the chip surface is described. The device has a form remeniscent of a semi circular plate placed perpendicularly to the chip plane. The operation principle is that of the conventional Hall-effect device. The unusual geometry principally does not affect sensitivity. The experimental samples are fabricated using a standard bulk CMOS technology, where the p-well deep diffusion is used to surround the active device volume. Sensitivity up to 450 V/AT is measured.     

高速率并行光发射模块的研制

介绍了有关并行光发射模块设计与制作的最新进展,制作并测试了12信道并行光发射模块,单信道传输速率大于2．5Gbit／s（最高可达3Gbit／s）,12信道并行总传输速率为30Gbit／s。模块采用波长为850nm的垂直腔面发射激光器（VCSEL）作光源,激光器与驱动电路芯片直接用Au丝连接,输出光束直接耦合进入12信道的光纤阵列中,在单信道8mA的工作电流下,可以测到最高为3Gbit／s的清晰眼图。     

用于纳米操作的硅基集成式微型 xy 定位平台

针对纳米级定位平台小型化和高定位精度的要求,基于体硅工艺研制出一种集结构、驱动和位移检测一体化的集成式微型纳米级xy定位平台.采用体硅双面深度反应离子刻蚀(DRIE)技术释放出高深宽比的静电梳齿驱动器、检测梁及定位平台结构.由于定位平台属于面内运动,为了提高面内运动位移榆测的灵敏度提出了一种利用离子注入工艺和DRIE技术相结合制作检测梁侧壁压阻的方法.并利用该侧壁压阻工艺成功地把基于侧壁压阻式的位移传感器集成到微型xy定位平台上.实验测试表明,位移传感器的灵敏度优于1.17mV/μm,线形度优于0.814%,当驱动电压取30V时,定位平台的单轴输出位移可达±10/μm,并且定位平台x方向和y方向上的位移耦合量非常小;在空气条件下测得定位平台的一阶固有频率为983Hz.     

基于垂直腔面发射激光器的高速率并行光发射模块

报道了关于并行光发射模块的设计与制作.优化设计、制作并测试了12信道并行光发射模块,单信道传输速率可达3Gbit/s.采用波长为850nm的垂直腔面发射激光器作光源,激光器与驱动电路芯片直接用金丝连接.输出光束直接耦合进入12信道的光纤阵列中.采用小型化可插拔封装结构以便在应用中实现热插拔.模块的测试结果表明,在8mA的工作电流下,测到3Gbit/s的清晰眼图.     

High power emission from red vertical cavity surface emitting laserarray

A parallel array of oxide-confined 676 nm vertical cavity surface emitting lasers (VCSELs) is demonstrated. 12 mW is emitted at 20°C from a six-element array covering a 90 μm diameter area. The individual apertures are thermally isolated, making the array scalable to higher powers. The maximum power is strongly dependent on both temperature and aperture size, with smaller apertures showing reduced thermal sensitivity     

256-channel bidirectional optical interconnect using VCSELs andphotodiodes on CMOS

Two-dimensional parallel optical interconnects (2-D-POIs) are capable of providing large connectivity between elements in computing and switching systems. Using this technology we have demonstrated a bidirectional optical interconnect between two printed circuit boards containing optoelectronic (OE) very large scale integration (VLSI) circuits. The OE-VLSI circuits were constructed using vertical cavity surface emitting lasers (VCSELs) and photodiodes (PDs) flip-chip bump-bonded to a 0.35-μm complementary metal-oxide-semiconductor (CMOS) chip. The CMOS was comprised of 256 laser driver circuits, 256 receiver circuits, and the corresponding buffering and control circuits required to operate the large transceiver array. This is the first system, to our knowledge, to send bidirectional data optically between OE-VLSI chips that have both VCSELs and photodiodes cointegrated on the same substrate     

一种3D垂直结构的光电探测器研制

提出了一种3D垂直结构光电探测器及制作方法.将光电探测器芯片的下电极焊接在基板上,上电极通过金丝连接到放大电路,使得光通过侧面进入本征工层,有效解决了重掺杂死区和金属电极的阻光问题,降低了光损失,减少了复合率,提高了响应度.结在半导体体内,减小了暗电流(表面漏电流),提高了反向击穿电压.结面积的主要部分为平行平面结,有...     

Integration of a single vertical-cavity surface emitting laser ontoa CMOS inverter chip

An InGaAs-AlGaAs vertical cavity surface emitting laser has been integrated following substrate removal onto a CMOS inverter chip. Digital modulation of the laser is shown     

Three-dimensional magnetic-field sensors

Devices sensitive to all three components of a magnetic-field vector are presented. The sensitivity to two field components in the plane of the chip is achieved by merging two one-dimensional vertical magnetotransistors positioned at a 90° angle to each other. An additional surface-collector pair makes this device also sensitive to the last field component, which is perpendicular to the plane of the chip. The sensitivity of the 3-D sensor is represented by a nondiagonal sensitivity-matrix. The smallest achieved sensitive volume is (6×10×16) μm³, which is limited by the design tolerances. The elements of the sensitivity matrix of the device are discussed along with the parameters that influence them. The influence of additional collector pairs on the sensitivity is also discussed. Several 3-D sensitive structures are presented, including magnetotransistor and resistive structures     

Enhancement of the spectral sensitivity of photodiodes for the mid-IR spectral range

A new method is used to raise the spectral sensitivity of photodiodes based on GaSb/GaInAsSb/GaAlAsSb heterostructures for the spectral range 1.1–2.4 μm. It is shown that, with a profile formed as pits on the metal-free unilluminated rear surface area of the photodiode chip, it is possible to improve the spectral sensitivity of the photodiodes at wavelengths in the range 1.8–2.4 μm. The most pronounced increase of up to 53% at the sensitivity maximum, compared with the sensitivity of conventional photodiodes with a fully metallized rear surface of the chip, is observed for photodiodes with shallow pits 30 μm in radius on their rear surface. These devices can find wide application in systems measuring the amount of water in petroleum products and the moisture content of paper, soil and grain.     

Three-dimensional IC trends

VLSI will be reaching to the limit of minimization in the 1990s, and after that, further increase of packing density or functions might depend on the vertical integration technology. Three-dimensional (3-D) integration is expected to provide several advantages, such as 1) parallel processing, 2) high-speed operation, 3) high packing density, and 4) multifunctional operation. Basic technologies of 3-D IC are to fabricate SOI layers and to stack them monolithically. Crystallinity of the recrystallized layer in SOI has increasingly become better, and very recently crystalaxis controlled, defect-free single-crystal area has been obtained in chip size level by laser recystallization technology. Some basic functional medels showing the concept or image of a future 3-D IC were fabricated in two or three stacked active layers. Some other proposals of subsystems in the application of 3-D structure, and the technical issues for realizing practical 3-D IC, i.e., the technology for fabricating high-quality SOI crystal on complicated surface topology, crosstalk of the signals between the stacked layers, total power consumption and cooling of the chip, will also be discussed in this paper.     

Fabrication and characterization of SPR chips with the modified bovine serum albumin

A facile surface plasmon resonance (SPR) chip is developed for small molecule determination and analysis. The SPR chip was prepared based on a self assembling principle, in which the modified bovine serum albumin (BSA) was directly self-assembled onto the bare gold surface. The surface morphology of the chip with the modified BSA was investigated by atomic force microscopy (AFM) and its optical properties were characterized. The surface binding capacity of the bare facile SPR chip with a uniform morphology is 8 times of that of the bare control SPR chip. Based on the experiments of immune reaction between cortisol antibody and cortisol derivative, the sensitivity of the facile SPR chip with the modified BSA is much higher than that of the control SPR chip with the un-modified BSA. The facile SPR chip has been successfully used to detect small molecules. The lowest detection limit is 5 ng/mL with a linear range of 5—100 ng/mL for cortisol analysis. The novel facile SPR chip can also be applied to detect other small molecules.     

Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks

Three-dimensional chip (3-D) stacking technology provides a new approach to address the so-called memory wall problem. Memory processor chip stacking reduces this memory wall problem, permitting faster clock rates (with suitable processor logic) or permitting multicore access to shared memory using a large number of vertical vias between tiers in the stack, for ultrawide bit path transfer of data and address information to and from various levels of cache. Although a limited amount of parallel access is possible using conventional two-dimensional (2-D) chip memory-processor approaches, 3-D memory-processor stacking greatly extends this to much larger capacity memories. We evaluate high-clock-rate processors as well as shared memory processors with a large number of cores. Various architectural design options to reduce the impact of the memory wall on the processor performance are explored and validated through simulations. Certain architectural features can be implemented in a 3-D chip, such as an ultrawide, ultrashort vertical bus with low parasitic resistance and the elimination of conventional electrostatic discharge, and packaging parasitics required in multiple package 2-D solutions. The objective is to reduce the clocks per instruction figure of merit for high clock speeds in order to deliver significant performance levels. High-clock-rate processors can be designed with SiGe heterostructure bipolar transistors to obtain processors operating on the order of 16 or 32 GHz.      

A new CCD architecture of high-resolution and sensitivity for colordigital still picture

A new charged-coupled device (CCD) architecture developed for building high-resolution and high-sensitivity image sensors suitable for color digital still picture applications is presented. The sensor is based on the interline CCD structure. Both the interline pixels and the vertical charge transfer lines are utilized as light-sensing elements to improve simultaneously the resolution and sensitivity. This device is named the sea-of-photosensor array (SPA-CCD). A camera and supporting digital system were designed and built specifically to evaluate the device. Digital picture processing for white balance adjustment, chromatic correction, and high-frequency luminance was performed to improve color reproduction and picture resolution. An increased light sensitivity and limiting resolutions of 550 horizontal lines and 400 vertical lines on a TV screen were confirmed with an SPA-CCD of the same chip size as a conventional 190-k pixel IT-CCD. The new design of the SPA-CCD overcomes both the sensitivity and the resolution limitations of previous approaches     

30Gbit/s并行光接收模块

报道了一种基于CMOS工艺接收电路芯片和GaAs工艺1×12光电探测器阵列的30Gbit/s并行光接收模块.该模块采用并行光通信方案,利用中高速光电子器件实现信号的高速传输.直接使用未经封装的接收电路裸片和光探测器裸片,采用电路板上芯片技术封装制作模块,并通过倒装焊的方式实现了探测器阵列与列阵光纤的精确对准并形成了可插拔的光接口.测试结果表明模块的接收能力可以达到30Gbit/s.误码率小于10-13时,接收模块的灵敏度可以达到-13.6dBm.     

30Gbit/s Parallel Optical Receiver Module

报道了一种基于CMOS工艺接收电路芯片和GaAs工艺1×12光电探测器阵列的30Gbit/s并行光接收模块.该模块采用并行光通信方案,利用中高速光电子器件实现信号的高速传输.直接使用未经封装的接收电路裸片和光探测器裸片,采用电路板上芯片技术封装制作模块,并通过倒装焊的方式实现了探测器阵列与列阵光纤的精确对准并形成了可插拔的光接口.测试结果表明模块的接收能力可以达到30Gbit/s.误码率小于10-13时,接收模块的灵敏度可以达到-13.6dBm.     

干涉型集成光学加速度计信号处理及SOPC设计

介绍了集成光学芯片、光纤质量块简谐振子和可编程片上系统(SOPC)混合集成光学加速度计的设计方法。采用迈克尔逊干涉方法实现加速度信号光相位调制,综合交流相位跟踪零差补偿技术(PTAC)和合成外差信号解调技术(SHSD)补偿误差并解调出加速度信号,应用SOPC技术设计和实现数字信号处理(DSP)系统,同时实现DSP和智能化数据传输接口并行工作,使系统实时、线性地跟踪到加速度信号。系统设计灵敏度达4.8902V/g。实际测量灵敏度达4.62V/g,工作频带10~1066Hz。     

Integrated sensor chip for interferometric displacementmeasurements

A simple sensor chip incorporating a vertical cavity surface emitting laser and a monolithically integrated resonant photodetector has been developed and mounted in a self-mixing interferometer. An investigation into the effect of feedback on the laser power is presented and the applicability of the sensor for displacement measurements described