共查询到18条相似文献,搜索用时 312 毫秒
1.
设计了一种偏压可调电流镜积分(Current Mirroring Integration,CMI)红外量子阱探测器焦平面CMOS读出电路。该电路适应根据偏压调节响应波段的量子阱探测器,其中探测器偏压从0.61 V到1.55V范围内可调。由于CMI的电流反馈结构,使得输入阻抗接近0,注入效率达0.99;且积分电容可放在单元电路外,从而可以在一定的单元面积下,增大积分电容,提高了电荷处理能力和动态范围;为提高读出电路的性能,电路加入撇除(Skimming)方式的暗电流抑制电路。采用特许半导体(Chartered)0.35 m标准CMOS工艺对所设计的电路(16×1阵列)进行流片,测试结果表明:在电源电压为3.3V,积分电容为1.25pF时,电荷处理能力达到1.3×107个电子;输出摆幅达到1.76V;功耗为25mW;动态范围为75dB;测试结果显示CMI可应用于高性能FPA。 相似文献
2.
3.
4.
甚长波红外(VLWIR)波段富含大气湿度、CO2含量及云层结构和温度轮廓等大量信息,是大气遥感的重要组成部分。为了满足现阶段甚长波红外探测器对读出电路高注入效率、大动态范围、稳定的探测器偏压、长积分时间等需求,设计了一种具有记忆功能背景抑制结构的共享型读出电路。该电路采用22四个相邻的探测器像元共用一个读出电路单元的共享缓冲直接注入级(SBDI)结构,增大了单元电路的面积,在单元内实现了具有记忆功能背景抑制结构的设计,其总积分电容达到8.8 pF,有效延长了积分时间和红外焦平面的信噪比(SNR),并改善了动态范围和对比度。基于HHNEC CZ6H 0.35 m 1P4M标准CMOS工艺,完成了电路的流片制造。仿真及测试结果表明:在50 K温度下电路功能正常,其动态范围大于90 dB,线性度优于99.9%,积分时间可达74 s,达到了设计要求。该读出电路适用于甚长波红外探测器。 相似文献
5.
6.
GaAs/InGaAs量子点光电探测器,在633 nm激光辐射3.5 nW条件下,器件偏压-1.4 V时,测得响应电流8.9×10-9A,电流响应率达到2.54 A/W,量子注入效率超过90%。基于GaAs/InGaAs量子点光电探测器的高量子注入效率、高灵敏度等特点,采用具有稳定的电压偏置,高注入效率和低噪声特点的CTIA(电容互阻跨导放大器)作为列放大器读出结构,输出部分采用相关双采样(CDS)结构去除系统和背景噪声。实验结果表明,在3.5 nW的微光辐射下,器件偏压为-2.5 V时,50μm×50μm像素探测器与读出电路互联后有7.14×107V/W的电压响应率。 相似文献
7.
为提高紫外焦平面组件成像质量,提出了可用于紫外焦平面的像素级数字化读出电路结构。针对紫外信号微弱及焦平面探测器像素面积小的特点,设计了基于电容反馈跨阻放大器(Capacitive Trans-Impedance Amplifier,CTIA)结构、模数转换器和锁存器的紫外焦平面像素级模数转换读出电路,并给出了实现像素内模数转换的工作原理。详细讨论了像素内模数转换的实现方法,各模块的设计要求及其具体实现,并基于0.35μm DP4M CMOS工艺设计制造了面阵规模128×128、像素单元面积50μm×50μm的读出电路芯片。电路性能测试与成像实验表明:电路的精度达到1mV以下,有效位数达到11位,实现了紫外焦平面读出电路的低噪声数字化输出。 相似文献
8.
9.
介绍了一种面向384×288 CMOS面阵性红外读出电路的低功耗设计.针对探测器的特点(输出阻抗约100kΩ,积分电流约100nA),新提出并实现了一种四像素共用BDI的QSBDI(Quad-share BDI)像素结构.在QSBDI结构中,4个相邻的像素共用一个反馈放大器,从而实现了高注入效率、稳定的偏置、较好的FPN特性和低功耗.另外该384×288读出电路还支持积分然后读出、积分同时读出功能,还有两个可选择的增益以及4种窗口读出模式.128×128的测试读出电路已完成设计、加工和测试.电路使用CSMC0.5μm DPTM工艺流片,测试结果表明在每个子阵列输出的峰峰差异仅为10mV.在4MHz的工作频率下,像素级引入的功耗仅为1mW,芯片的整体功耗也只有37mW,实现了低功耗设计. 相似文献
10.
介绍了一种面向384×288 CMOS面阵性红外读出电路的低功耗设计.针对探测器的特点(输出阻抗约100kΩ,积分电流约100nA),新提出并实现了一种四像素共用BDI的QSBDI(Quad-share BDI)像素结构.在QSBDI结构中,4个相邻的像素共用一个反馈放大器,从而实现了高注入效率、稳定的偏置、较好的FPN特性和低功耗.另外该384×288读出电路还支持积分然后读出、积分同时读出功能,还有两个可选择的增益以及4种窗口读出模式.128×128的测试读出电路已完成设计、加工和测试.电路使用CSMC0.5μm DPTM工艺流片,测试结果表明在每个子阵列输出的峰峰差异仅为10mV.在4MHz的工作频率下,像素级引入的功耗仅为1mW,芯片的整体功耗也只有37mW,实现了低功耗设计. 相似文献
11.
A high injection, large dynamic range, stable detector bias, small area and low power consumption CMOS readout circuit with background current suppression and correlated double sampling (CDS) for a high-resolution infrared focal plane array applications is proposed. The detector bias error in this structure is less than 0.1 mV. The input resistance is ideally zero, which is important to obtain high injection efficiency. Unit-cell occupies 10 μm× 15 μm area and consumes less than 0.4 mW power. Charge storage... 相似文献
12.
A high-performance CMOS readout integrated circuit (ROIC) with a new temperature and power supply independent background current
and dark current suppression technique for room-temperature infrared focal plane array applications is proposed. The structure
is composed of an improved switched current integration stage, a new current-mode background suppression circuit, and a high
linearity, high voltage swing output stage. An experimental readout chip has been designed and fabricated using the Chartered
0.35 μm CMOS process. Both the function and performance of the proposed readout circuit have been verified by experimental
results. The test results show that the detector bias error in this structure is less than 0.1 mV. The input resistance is
close to an ideal value of zero, and the injection efficiency is almost 100%. The output voltage linearity of the designed
circuit is more than 99%. The background suppression level is tunable between 8 nA–1.5 μA, and the background suppression
uniformity is as high as 100%. A unit-cell occupies a 10 μm × 15 μm area and consumes less than 0.07 mW power. 相似文献
13.
In this paper an integrated CMOS readout circuit for a radiation detector in a personal dosimeter is presented. High counting rate and low power requirements make the stability of the conventional high-pass pulse shaper a big problem. A novel phase-shift compensation method is proposed to improve the phase margin. The principle of the compensation circuit and its influence on noise performance are analyzed theoretically. A readout chip with two channels of conventional structure and one channel of the proposed structure has been implemented in a 0.35 μm CMOS technology. It occupies an area of 2.113×0.81 mm2. Measurement results show that the proposed channel can process up to 1 MHz counting rate and provide a conversion gain of about 170 mV/fC at a power dissipation of 330 μW with a 3.3 V power supply. Ac-coupled to a silicon PIN detector, it successfully detects β-rays. 相似文献
14.
一个128×128CMOS快照模式焦平面读出电路设计 总被引:3,自引:0,他引:3
本文介绍了一个工作于快照模式的CMOS焦平面读出电路新结构——DCA(Direct-injection Charge Amplifier)结构.该结构像素电路仅用4个MOS管,采用特殊的版图设计并用PMOS管做复位管,既可保证像素内存储电容足够大,又可避免复位电压的阈值损失,从而提高了读出电路的电荷处理能力.由于像素电路非常简单,且该结构能有效消除列线寄生电容Cbus的影响,因此该结构非常适用于小像素、大规模的焦平面读出电路.采用DCA结构和1.2μm双硅双铝(DPDM-Double-Poly Double-Metal)标准CMOS工艺设计了一个128×128规模焦平面读出电路试验芯片,其像素尺寸为50×50μm2,电荷处理能力达11.2pC.本文详细介绍了该读出电路的体系结构、像素电路、探测器模型和工作时序,并给出了精确的HSPICE仿真结果和试验芯片测试结果. 相似文献
15.
扫描式红外成像传感器在遥测遥感、卫星成像等远距离成像领域具有广泛的应用。为了缓解信噪比相对较低而影响图像质量的问题,提出了一种时间延时积分(TDI)型读出电路。该读出电路由电容跨阻放大器(CTIA)像素电路阵列、并行TDI电路、多路开关选择电路和输出缓冲器等组成。为实现对宽动态范围光电流的处理,CTIA电路设计有多档可选增益,且非线性度小于0.3%。该读出电路采用0.35 μm CMOS工艺设计与制造,芯片面积约为1.3 mm×20 mm,采用5 V电源时功耗小于60 mW。为了评估1024×3 TDI读出电路的功能,采用了对TDI输入端注入不同电压激励的方式进行测试,测试结果验证了所提出的设计方案。 相似文献
16.
《半导体学报》2010,31(2)
The design and measurement of a snap-shot mode cryogenic readout circuit (ROIC) for GaAs/AlGaAs QWIP FPAs was reported. CTIA input circuits with pixel level built-in electronic injection transistors were proposed to test the chip before assembly with a detector array. Design optimization techniques for cryogenic and low power are analyzed. An experimental ROIC chip of a 128 × 128 array was fabricated in 0.35μm CMOS technology. Measure-ments showed that the ROIC could operate at 77 K with low power dissipation of 35 mW. The chip has a pixel charge capacity of 2.57 × 10~6 electrons and transimpedance of 1.4 × 10~7 Ω. Measurements showed that the transimpedance non-uniformity was less than 5% with a 10 MHz readout speed and a 3.3 V supply voltage. 相似文献
17.
Xiqu Chen Xinjian Yi Ying Yang Yi Li 《Journal of Infrared, Millimeter and Terahertz Waves》2006,27(9):1281-1291
A new CMOS readout circuit for VO2-based uncooled FPAs is presented in this paper. The on-chip readout circuit consists of three major parts: An input circuit of BCDI structure, a column-shared integration circuit of CTIA structure, and a common CDS output circuit. The simple configuration of the input circuit makes it possible to operate more circuits in parallel, and increases the integration time and number of pixels, the column-shared integration circuit which is suitable for small pixel size provides low noise, high gain, a highly stable detector bias, and high photon current injection efficiency, and the common CDS output circuit is utilized to reduce or eliminate low-frequency noise of the readout circuit. An experimental readout chip for 50-μm-pitch 32×32 element VO2-based uncooled FPAs has been fabricated. The measurement results of the fabricated readout chip have successfully verified its readout function and excellent performance. 相似文献