A simple approach to modeling cross-talk in integrated circuits

A simple engineering approach for rapid simulation of cross-talk in mixed-mode IC's using SPICE is presented. A side-by-side comparison of several cross-talk reduction schemes has shown that while an SOI-based process provides high isolation from cross-talk at low operating frequencies, its benefit is lost at high frequencies. Simple guard ring substrate contacts appear to be the technique best suited for preventing cross-talk at high operating frequencies. Lumped parameter equivalent circuits have also been developed to represent different isolation schemes in SPICE. The isolation characteristics of test structures employing the above techniques are computed using SPICE and the results compared with two-dimensional device simulation. The results are also compared with experimental measurements on actual silicon to validate the models     

A COMPUTER-AIDED UNIFIED APPROACH TO MODELING PWM AND RESONANT CONVERTERS

This letter puts forward a method of modeling for the steady-state and small signal dynamic analysis on PWM, quasi-resonant and series/（parallel） resonant switching converters based on pulse-waveform integral approach. As an example, PWM and quasi-resonant converters are used to discuss the principle of the approach. The results are compared with those in the relative literatures. Computer aided analysis are made to confirm the correctness.     

Analog circuits for modeling biological neural networks: design andapplications

Computational neuroscience is emerging as a new approach in biological neural networks studies. In an attempt to contribute to this field, we present here a modeling work based on the implementation of biological neurons using specific analog integrated circuits. We first describe the mathematical basis of such models, then present analog emulations of different neurons. Each model is compared to its biological real counterpart as well as its numerical computation. Finally, we demonstrate the possible use of these analog models to interact dynamically with real cells through artificial synapses within hybrid networks. This method is currently used to explore neural networks dynamics.     

Modeling of quantum-well lasers for computer-aided analysis ofoptoelectronic integrated circuits

A two-port circuit model for quantum-well (QW) lasers has been developed from rate equations. With emphasis on the physical principles, the phenomena of the recombination process of electron-hole pairs and the light wave resonance in the active region have been incorporated into this new model. The model has been implemented in a circuit simulator and validated with measured DC and transient laser characteristics. The frequency effects on the modulation properties of QW lasers have been studied and analyzed using a small-signal model. Simulation results show excellent agreement with experimental data     

FIRGEN: a computer-aided design system for high performance FIRfilter integrated circuits

The authors describe automatic architecture and floorplan generation techniques for integrated circuit fixed-coefficient FIR (finite impulse response) filters that can achieve high sample rates with compact layouts. These techniques have been implemented in a filter design system called FIRGEN that can automate the entire design from filter specifications to final chip layout. It can be retargeted to new cell libraries and place and route tools. Result on four chips designed with FIRGEN are presented. These achieve sample rates ranging from 25 MHz to 112 MHz     

Systematic computer-aided multidimensional modeling of integrated bipolar devices

A general, systematic method for modeling three-dimensional bulk effects in integrated bipolar devices is developed. The application of the technique to a device results in a hierarchy of large-signal models-based on linear differential equations-of variable accuracy and complexity from which the simplest but sufficiently accurate model of the device and its interactions with neighboring devices can be selected.The models produced consist of lumped elements which are directly related to the device morphology and to physical processes occurring in the device. The analogies existing between the terminal characteristics of the lumped elements and those of electrical elements are utilized in the formulation of a general lumped-to-electrical transformation technique by which equivalent electrical models, amenable to analysis by existing network analysis programs, can be obtained.The derived modeling theory is applied to several devices of variable complexity, and resulting models are verified experimentally.Finally, discussions concerning modifications of linear models to include, at least on first-order bases, several nonlinear effects, some associated with pn junctions, are given.     

Automated topology synthesis of analog and RF integrated circuits: A survey

The puzzle of automatically synthesizing analog and radio frequency (RF) circuit topology has not yet been offered with an industrially-acceptable solution although endeavors still continue to seek a conquest in this area. This survey provides a comprehensive study of the techniques utilized for this purpose. The existing methods are analyzed from four different viewpoints, namely, structural view, conceptual view, implementation view, and application view. Different schemes are perused with their advantages and drawbacks discussed in the context of balanced performance between configuration-space coverage and search efficiency. Some prospective trends are pointed out to shed light on the upcoming research activities.     

Well-posed nonlinear problems in integrated circuits modeling

In this paper we study the problem (E) + (BC) + (IC) (see below) which represents a model for integrated circuits. We assume that the distributed parametersr(x) andc(x) are nonconstant, dielectric leakages depend on thex-coordinate as well as the voltage level, while the interconnecting multiport is nonlinear and possibly multivalued.     

The modeling of resistive interconnects for integrated circuits

Techniques for analyzing the signal transmission properties of long resistive interconnects on integrated circuits are presented. Because accurate measurements of propagation characteristics on chip are difficult to make, RC transmission line theory is used to establish exact performance. The results of various simulations are compared to this theoretical performance. Guidance is provided for selecting the number of elements needed to accurately simulate performance under various conditions.     

Distributed integrated circuits: an alternative approach tohigh-frequency design

Distributed integrated circuits are presented as a methodology to design high-frequency communication building blocks. Distributed circuits operate based on multiple parallel signal paths working in synchronization that can be used to enhance the frequency of operation, combine power, and enhance the robustness of the design. These multiple signal paths usually result in strong couplings inside the circuit that necessitate a treatment spanning architecture, circuits, devices, and electromagnetic levels of abstraction     

A design for testability approach for nano-CMOS analogue integrated circuits

Dependability requirements must be considered from the beginning when designing safety-critical systems. Therefore, testing should even be considered earlier, intertwined with the design process. The process of designing for better testability is called design for testability (DfT). This article presents two designs for testability and fault diagnosis techniques using a new design analogue checker circuit in order to improve the testability and the diagnosability of nano-CMOS (complementary metal oxide semiconductor) analogue circuits used in safety-critical applications based on the system-on-chip (SoC) approach design. The testing techniques presented in this work can be done during and after the system fabrication. The checker is implemented in full-custom 65 nm Complementary metal–oxide–semiconductor (CMOS) technology with low supply voltage and small-size capabilities. SPICE simulations of the post-layout extracted CMOS checker, which include all parasitic, are used to validate the technique and demonstrate the acceptable electrical behaviour of the checker.