Modeling and measurement of substrate coupling in Si-bipolar IC'sup to 40 GHz

Parasitic substrate coupling can severely degrade the performance of high-speed ICs and must be considered carefully in circuit design. Therefore, this paper proposes several equivalent circuits that are well suited for modeling substrate coupling up to very high frequencies with standard circuit simulators such as SPICE. Their element values can be calculated for arbitrary layout configurations from numerical simulations (using our SUbstrate SImulator SUSI), which are based on experimentally determined, specific technological/electrical data. The validity of both the simulator and the equivalent circuits has been verified by on-wafer measurements up to 40 GHz, the highest frequency reported so far for modeling of substrate coupling. For this, special test structures were designed and fabricated in an advanced Si-bipolar technology. This work is focused on substrate modeling in very-high-speed rather than in complex ICs     

Computer-aided design considerations for mixed-signal coupling inRF integrated circuits

This paper reviews computer-aided design techniques to address mixed-signal coupling in integrated circuits, particularly wireless RF circuits. Mixed-signal coupling through the chip interconnects, substrate, and package is detrimental to wireless circuit performance as it can swamp out the small received signal prior to amplification or during the mixing process. Specialized simulation techniques for the analysis of periodic circuits in conjunction with semi-analytical methods for chip substrate modeling help analyze the impart of mixed-signal coupling mechanisms on such integrated circuits. Application of these computer-aided design techniques to real-life problems is illustrated with the help of a design example. Design techniques to mitigate mixed-signal coupling can be determined with the help of these modeling and analysis methods     

Crosstalk between finite ground coplanar waveguides over polyimide layers for 3-D MMICs on Si substrates

Finite-ground coplanar (FGC) waveguide lines on top of polyimide layers are frequently used to construct three-dimensional Si-SiGe monolithic microwave/millimeter-wave integrated circuits on silicon substrates. Requirements for high-density, low-cost, and compact RF front ends on silicon can lead, however, to high crosstalk between FGC lines and overall circuit performance degradation. This paper presents theoretical and experimental results and associated design guidelines for FGC line coupling on both highand low-resistivity silicon wafers with a polyimide overlay. It is shown that a gap as small as 6 /spl mu/m between two adjacent FGC lines can reduce crosstalk by at least 10 dB, that the nature of the coupling mechanism is not the same as with microstrip lines on polyimide layers, and that the coupling is not dependent on the Si resistivity. With careful layout design, isolation values of better than -30 dB can be achieved up to very high frequencies (50 GHz).     

Performance comparison of substrate coupling effect between silicon and SOI substrates in RF-CMOS technology

Substrate coupling may severely degrade the electrical performances of high-speed and RF integrated circuits. An isolation technique study of parasitic effects due to substrate coupling between two blocks of integrated circuits in an RF CMOS 90 nm technology is presented. Isolation performances are compared for both bulk silicon (Si) and silicon-on-insulator (SOI) substrate. For every substrate, a compact electrical model matching well with measurement results is proposed for test structures composed of 50times50 mum cells surrounded with an appropriate guard ring. An isolation improvement of 10 dB is reached by an additional P-type guard ring placed around one cell and an isolation level of 45 dB is achieved at 1 GHz for bulk Si substrate     

Methods for measurement and simulation of weak substrate couplingin high-speed bipolar ICs

On-wafer measurements of very weak substrate coupling in high-speed integrated circuits (ICs) at high frequencies suffer from the direct crosstalk between the input and output RF probes. Two alternative methods to reduce this effect are presented and compared. The first one is based on an advanced deembedding method that eliminates the crosstalk between the RF probes after measurement. The second method utilizes an on-chip broad-band amplifier between the input probe and the substrate test structure. Thus, for a given signal amplitude at the output probe, the amplitude of the input signal can be reduced, resulting in less distortion of the output signal by the crosstalk via the probes. Both methods are compared and verified by measurements up to about 20 GHz even at substrate coupling impedances as high as 0.5 MΩ (corresponding to -80 dB in a 50-Ω system). For this, several substrate test structures (some with the 20-GHz on-chip amplifier) have been designed and fabricated in an SiGe bipolar production technology with 20-Ωcm substrate resistivity. The measurement results agree well with simulation results using our substrate simulator SUSI. As a consequence, the inflexible, expensive, and time-consuming way to determine substrate coupling experimentally is no longer required in future IC designs-not even at very weak coupling and high frequencies. In this work, however, the proposed measuring methods had to be applied to verify the suitability of substrate simulation (with SUSI) under extreme conditions     

RF circuit design aspects of spiral inductors on silicon

The design and optimization of spiral inductors on silicon substrates, the related layout issues in integrated circuits, and the effect of the inductor-Q an the performance of radio-frequency (RF) building blocks are discussed. Integrated spiral inductors with inductances of 0.5-100 nH and Q's up to 40 are shown to be feasible in very-large-scale-integration silicon technology. Circuit design aspects, such as a minimum inductor area, the cross talk between inductors, and the effect of a substrate contact on the inductor characteristics are addressed. Important RF building blocks, such as a bandpass filter, low-noise amplifier, and voltage-controlled oscillator are shown to benefit substantially from an improved inductor-Q     

Modeling substrate effects in the design of high-speed Si-bipolarICs

In the design of high-speed IC's, the influence of the substrate on circuit performance must be considered carefully. Therefore, in this paper the contribution of the p^- substrate and channel stopper to the equivalent circuits of Si-bipolar transistors and bond pads are theoretically and experimentally investigated up to very high frequencies. Improved equivalent substrate circuits, well suited for standard circuit simulators (e,g., SPICE), are derived and checked by numerical simulation using a new simulator (called SUSI). The validity of both the numerical simulation results and the equivalent circuits are verified by on-wafer measurements up to 20 GHz. Finally, the simulator was successfully applied to investigate noise coupling via the substrate     

Experimental results and modeling techniques for substrate noise inmixed-signal integrated circuits

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is the most effective. Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed     

High-Speed Si-Bipolar and GaAs Technologies

Improvements in the design and fabrication of the basic transistor devices and improvements in circuit layout and design techniques have dramatically increased the performance of high-speed bipolar integrated circuits. Refinement of standard processes like lithography and the introduction of new processes such as low-pressure epitaxy and dry-etching techniques have largely contributed to the advancement of the device technology. GaAs int&égrated circuit technologies have rapidly developed over the last few years so that both analog and digital integrated circuits are now commercially available. These circuits all use the GaAs MESFET as the basic switching or modulating transistor. Integrated circuits based on more sophisticated heterostructure components, such as the heterojunction bipolar transistor or the modulation doped FET, are currently being developed. This paper will try to give an overview of present state of the art high-speed silicon bipolar technology and compare it to competing GaAs technologies. The most recent advances in oxide isolation technology which have led to the availability of 2.6 GHz dividers and the trend to self-aligned processes which can be used to achieve even smaller geometries will be described. On the GaAs side, the various GaAs-MESFET logic technologies and the heterojunction transistor technologies will be looked at regarding their present status and what can be expected in the near future. Most of the data will relate to monolithically integrated frequency dividers where a requirement for higher input frequencies combined with low power consumption exists.     

Trends in silicon radio large scale integration: zero IF receiver!Zero I&Q transmitter! Zero discrete passives!

After 10 years of advances in silicon RF integration, what used to be an art is becoming a “normal practice”. Historically, RF design was the art of s-parameters, shielding, impedance matching, and standing wave ratios. Modern silicon RFICs are designed using the same SPICE-like tools as in low-frequency analog ICs with the addition of important software for system-level simulation and mixer circuit noise analysis. New RF design practices away from the 50 ohm culture, novel chip architectures, and powerful technological advances will drive radio integration toward the ultimate single-chip phone. The obstacles in this quest are high system requirements on noise figure, substrate crosstalk, and parasitic coupling, not the silicon IC technology     

Substrate transfer for RF technologies

The constant pressure on performance improvement in RF processes is aimed at higher frequencies, less power consumption, and a higher integration level of high quality passives with digital active devices. Although excellent for the fabrication of active devices, it is the silicon substrate as a carrier that is blocking breakthroughs. Since all devices on a silicon wafer have a capacitive coupling to the resistive substrate, this results in a dissipation of RF energy, poor quality passives, cross-talk, and injection of thermal noise. We have developed a low-cost wafer-scale post-processing technology for transferring circuits, fabricated with standard IC processing, to an alternative substrate, e.g., glass. This technique comprises the gluing of a fully processed wafer, top down, to an alternative carrier followed by either partial or complete removal of the original silicon substrate. This effectively removes the drawbacks of silicon as a circuit carrier and enables the integration of high-quality passive components and eliminates cross-talk between circuit parts. A considerable development effort has brought this technology to a production-ready level of maturity. Batch-to-batch production equipment is now available and the technology and know-how are being licensed. In this paper, we present four examples to demonstrate the versatility of substrate transfer for RF applications.     

RF Performance of a Commercial SOI Technology Transferred Onto a Passivated HR Silicon Substrate

In this paper, we investigate the impact of a passivation layer on the performance of a commercial high-resistivity (HR) SOI CMOS technology. The passivation layer consists of a 300-nm-thick polysilicon cover located directly below the buried oxide (BOX). Both passive and active devices are studied. It is demonstrated that substrate passivation completely suppresses substrate losses that are usually induced by parasitic surface conduction at the substrate/BOX interface in oxidized HR Si substrates. We also report no effect of the underlying polysilicon on the dc and RF behavior of MOSFETs devices. The results shown here strongly suggest that substrate passivation using polysilicon is a promising tool to eradicate substrate losses in HR SOI wafers, thereby increasing the performance of functional SOI logic and high-speed circuits.     

应用于微波和RF电路中的厚膜材料和工艺

介绍了应用于微波和 RF电路中的厚膜材料和工艺。无玻璃的厚膜导体材料 (如金、银等 )的电阻率极低。氧化铝 (96% ,99% )、氧化铍和氮化铝陶瓷的高频损耗很低 ,是优良的微波和 RF电路用基板。采用先进的厚膜细线技术 ,使厚膜导体的线分辨率几乎达到了薄膜工艺的水平。新开发的低损耗、低介电常数的低温共烧陶瓷 (L TCC)材料最适合做微波 MCM的基板材料。     

A second-harmonic LC-quadrature voltage controlled oscillator with direct connection of MOSFETs’ substrate

This work introduces a new low noise second-harmonic quadrature voltage controlled oscillator (QVCO) made by coupling two identical cross-connected LC voltage controlled oscillators. In each of the core oscillators the substrate nodes of the MOS varactors, and also the substrate nodes of the cross-connected MOSFETs are configured in such a way that they act as common mode nodes. Then the core oscillators are coupled together via direct connection of the substrates of the MOS varactors in one of the core oscillators to the substrates of the cross-connected MOSFETs in the other core oscillator, and vice versa. No extra elements are used for coupling of the two core oscillators and therefore no extra noise sources are imposed on the circuit. Operation of the proposed QVCO was investigated with simulation using a commercial 0.18 μm RF CMOS technology: it shows a power dissipation of 9.7 mW from a 1.8 V supply voltage and a simulated phase noise of −125.5 dBc/Hz at 1 MHz offset from center oscillation frequency of 5 GHz. Since the tail transistor can be eliminated, the proposed QVCO can operate with supply voltages as low as 0.5 V, as confirmed with simulation.     

Reliability optimization of analog integrated circuits considering the trade-off between lifetime and area

The reliability of analog integrated circuits becomes a major concern for the semiconductor industry as technology continuously scales. Among the many contributing factors, manufacturing process induced parameter variations and lifetime operational-condition-dependent transistor aging are two major hurdles limiting the reliability of analog circuits. Process variations mainly influence the parametric yield value of the fresh circuits, while transistor aging due to physical effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), will cause another yield loss during circuit lifetime. In the past decades, the two issues were mainly studied separately by various communities, but analog designers nowadays need an accurate yet efficient method to analyze and optimize their circuits during the design phase, to ensure a more robust design tolerant of such joint effects.This paper proposes an efficient method for sizing of analog circuits for reliability. It is based on the analysis and optimization of the fresh worst-case distance value for each circuit performance, which can be used to characterize the robustness of circuits considering process variations and aging effects in terms of x-sigma. The fresh and aged sizing rules as well as the maximum area constraints are checked during the optimization. The trade-off between the circuit lifetime and the price we pay in terms of layout area is studied in detail. According to the result of this trade-off analysis, a longer circuit lifetime requires more total area to be spent in layout, and designers can ensure the circuit robustness with certain layout area consumption.     

混合信号衬底耦合噪声的传播及抑制方法

介绍了衬底噪声耦合效应在不同工艺衬底中的传播,应用medici模拟了不同衬底中,噪声发生端和噪声接收端噪声在不同间距下噪声传播的情况,并从工艺和电路设计两个方面介绍了一系列抑制衬底噪声的方法。     

CMOS substrate coupling modeling and analysis flow for submicron SoC design

CMOS technology substrate crosstalk modeling and a respective analysis flow that captures the affected circuit performance is described. The proposed methodology can be seamlessly integrated into any industrial Analog/RF circuit design flow, and be compatible within standard design environments. It provides accurate estimation of the substrate coupling effects and can estimate adequately all the mask design level isolation performance trends by adapting an advanced substrate modeling concept based on geometrical and process data. Different substrate model accuracy constraints can be invoked depending on the design phase and the simulation time needs. The provided accuracy is validated by correlating simulation results versus on wafer silicon measurements in a 28 nm CMOS set of ring oscillators with carrier frequency of 670 MHz. The mean error of the proposed method is 665 μV while the error sigma is 765 μV.     

CMOS结构中的闩锁效应

本文较为详细地阐述了体硅CMOS结构中的闩锁效应，分析了CMOS结构中的闩锁效应的起因，提取了用于分析闩锁效应的集总组件模型，给出了产生闩锁效应的必要条件与闩锁的触发方式。通过分析表明，只要让CMOS电路工作在安全区，闩锁效应是可以避免的，这可以通过版图设计规则和工艺技术，或者两者相结合的各种措施来实现。本文最后给出了防止闩锁效应的关键设计技术。     

SOI在射频电路中的应用

随着射频电路(RF)工作频率和集成度的提高,衬底材料对电路性能的影响越来越大.SOI(Silicon-on-Insulator)结构以其良好的电学性能,为系统设计提供了灵活性.与CMOS工艺的兼容使它能将数字电路与模拟电路混合,在射频电路应用方面显示巨大优势.文章分析了RF电路发展中遇到的挑战和SOI在RF电路中的应用优势,综述了SOI RF电路的最新进展.     

A micromachining technology for integrating low-loss GHz RF passives on non-high-resistivity low-cost silicon MCM substrate

A micromachining technology for integrating high-performance radio-frequency (RF) passives on CMOS-grade low-cost silicon substrates is developed. The technology can form a thick solid-state dielectric isolation layer on silicon substrate through high-aspect-ratio trench etch and refill. On the non-high-resistivity but low-loss substrate, two metal layers with an inter-metal dielectric layer are formed for integrating embedded RF components and passive circuits. Using the technology, two types of integrated RF filters are fabricated that are band-pass filter and image-reject filter. The band-pass filter shows measured minimum insertion loss of 3.8 dB and return loss better than 15 dB, while the image-reject filter exhibits steeper band selection and achieves better than −30 dB image rejection. A 50 Ω co-planar waveguide (CPW) on the substrate is also demonstrated, showing low loss and low dispersion over the measured frequency range up to 40 GHz. The developed technology proves a viable solution to implementing silicon-based multi-chip modules (MCM) substrates for RF system-in-package (RF-SiP).